CN103227276B - Light emitting semiconductor device and manufacture method thereof - Google Patents
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- CN103227276B CN103227276B CN201310108640.XA CN201310108640A CN103227276B CN 103227276 B CN103227276 B CN 103227276B CN 201310108640 A CN201310108640 A CN 201310108640A CN 103227276 B CN103227276 B CN 103227276B
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Abstract
The invention provides a kind of light emitting semiconductor device and manufacture method thereof, light emitting semiconductor device comprises the substrate with first surface and second surface, and described first surface is provided with semiconductor luminous chip; Except the light output surface of described semiconductor luminous chip, all exposed, that the there is conductivity surface of described semiconductor luminous chip and side wrap up by least one insulating barrier, described insulating barrier partly or entirely containing a reflection layer; Described reflection layer is positioned at described insulating barrier or is positioned at the exposed surface of described insulating barrier, and and insulated from each other between described semiconductor luminous chip.Structure of the present invention is simple, light extraction efficiency and the uniformity high, excellent heat dissipation performance; And manufacture method is simple and convenient.
Description
Technical field
The present invention relates to a kind of light emitting semiconductor device, relate to the high light emitting semiconductor device of a kind of light extraction efficiency and manufacture method thereof further.
Background technology
Along with the lifting of semiconductor light emitting efficiency, the decline of manufacturing cost and the raising in useful life, its range of application has contained the fields such as display, backlight and illumination.
In common light emitting semiconductor device, comprise substrate, N-shaped conductive layer, luminescent layer, p-type electric-conducting layer, n-type electrode, p-type electrode, conductor wire, insulating barrier, pad etc., N-shaped conductive layer, luminescent layer and p-type electric-conducting layer jointly form and are semiconductor laminatedly arranged on substrate, n-type electrode and p-type electrode conduct electricity respectively and are connected N-shaped conductive layer and p-type electric-conducting layer, realize n-type electrode and the connection between p-type electrode and weld pad by conductor wire.But poor, the easy fracture of conductor wire heat-conducting effect in existing light emitting semiconductor device, and defect and the problem such as light extraction efficiency is low, therefore, be necessary to design the high light emitting semiconductor device of a kind of light extraction efficiency.
Summary of the invention
The technical problem to be solved in the present invention is, provides that a kind of light extraction efficiency is high, the light emitting semiconductor device of excellent heat dissipation performance and manufacture method thereof.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of light emitting semiconductor device, comprises the substrate with first surface and second surface, and described first surface is provided with semiconductor luminous chip; Except the light output surface of described semiconductor luminous chip, all exposed, that the there is conductivity surface of described semiconductor luminous chip and side wrap up by least one insulating barrier, described insulating barrier partly or entirely containing a reflection layer; Described reflection layer is positioned at described insulating barrier or is positioned at the exposed surface of described insulating barrier, and and insulated from each other between described semiconductor luminous chip.
In light emitting semiconductor device of the present invention, the light output surface of described semiconductor luminous chip or the light output surface of described semiconductor luminous chip and be enclosed with described insulating barrier the surrounding side of described semiconductor luminous chip wrap up by one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body.
In light emitting semiconductor device of the present invention, described semiconductor luminous chip comprises at least one semiconductor laminated; Describedly semiconductor laminatedly comprise folded N-shaped conductive layer, luminescent layer and the p-type electric-conducting layer established successively, describedly semiconductor laminatedly be arranged on the first surface of described substrate with its p-type electric-conducting layer towards described substrate, the surface of described N-shaped conductive layer described substrate is dorsad the light output surface of described semiconductor luminous chip;
The n-type electrode step that described p-type electric-conducting layer surface has at least one to expose partially n-type conductive layer, n-type electrode shrinkage pool and/or n-type electrode groove; Described p-type electric-conducting layer surface, semiconductor laminated side, n-type electrode ledge surface and side, n-type electrode shrinkage pool bottom surface and side, n-type electrode groove floor and side all wrap up by described insulating barrier.
In light emitting semiconductor device of the present invention, described surface of insulating layer is exposed at least one p-type electrode and at least one n-type electrode; Described p-type electrode runs through described insulating barrier and conducts electricity with described p-type electric-conducting layer and be connected, and insulate with described luminescent layer and N-shaped conductive layer; Described n-type electrode runs through described insulating barrier and is located in described n-type electrode step, n-type electrode shrinkage pool and/or n-type electrode groove, and conducts electricity with described N-shaped conductive layer and be connected, and insulate with described luminescent layer and p-type electric-conducting layer.
In light emitting semiconductor device of the present invention, described substrate first surface is provided with at least one p-type weld pad and at least one N-shaped weld pad; Described p-type electrode and n-type electrode are conducted electricity with described p-type weld pad and N-shaped weld pad respectively and are connected, and described semiconductor luminous chip is fixed on the first surface of described substrate.
In light emitting semiconductor device of the present invention, between described p-type electrode and p-type weld pad, have at least one p-type layer, described p-type layer is close to described surface of insulating layer, and its area is greater than described p-type electrode, and conducts electricity with described p-type electrode and p-type weld pad and be connected; And/or
Between described n-type electrode and N-shaped weld pad, have at least one N-shaped layer, described N-shaped layer is close to described surface of insulating layer, and its area is greater than described n-type electrode, and conducts electricity with described n-type electrode and N-shaped weld pad and be connected.
In light emitting semiconductor device of the present invention, described substrate is also provided with at least one p-type pad and at least one N-shaped pad;
Described p-type pad is arranged on described substrate first surface, described second substrate surface and/or described substrate side surfaces, and to be conducted electricity with described p-type weld pad by the p-type interconnecting metal that is arranged on described substrate first surface, described second substrate surface and/or described substrate side surfaces and/or runs through described substrate and be connected; Or described p-type pad is conduct electricity through described substrate and described p-type weld pad the p-type needle-like pad be connected;
Described N-shaped pad is arranged on described substrate first surface, described second substrate surface and/or described substrate side surfaces, and to be conducted electricity with described N-shaped weld pad by the N-shaped interconnecting metal that is arranged on described substrate first surface, described second substrate surface and/or described substrate side surfaces and/or runs through described substrate and be connected; Or described N-shaped pad is conduct electricity through described substrate and described N-shaped weld pad the N-shaped needle-like pad be connected.
In light emitting semiconductor device of the present invention, be provided with at least one n-type electrode interconnection layer in described insulating barrier, described n-type electrode comprises at least one first n-type electrode and at least one second n-type electrode; Described first n-type electrode runs through the described insulating barrier being positioned at described n-type electrode upperside interconnection layer and conducts electricity with described n-type electrode interconnection layer and be connected, and described n-type electrode interconnection layer to be conducted electricity with described N-shaped conductive layer by least one described second n-type electrode running through the described insulating barrier be positioned at below described n-type electrode interconnection layer and is connected; Described second n-type electrode is located in described n-type electrode step, n-type electrode shrinkage pool and/or n-type electrode groove; Described n-type electrode interconnection layer and insulated from each other between described p-type electrode and reflection layer; And/or,
Be provided with at least one p-type electrode interconnect layers in described insulating barrier, described p-type electrode comprises at least one first p-type electrode and at least one second p-type electrode; Described first p-type electrode runs through the described insulating barrier be positioned at above described p-type electrode interconnect layers and conducts electricity with described p-type electrode interconnect layers and be connected, and described p-type electrode interconnect layers to be conducted electricity with described p-type electric-conducting layer by the described second p-type electrode that runs through the described insulating barrier be positioned at below described p-type electrode interconnect layers and is connected; Described p-type electrode interconnect layers and insulated from each other between described n-type electrode and reflection layer.
In light emitting semiconductor device of the present invention, be provided with p-type current extending between described p-type electric-conducting layer surface and described insulating barrier, described p-type current extending is connected with described p-type electrodes conduct; Described p-type current extending comprise in p-type metal diffusion barrier layer, p-type electric-conducting extension layer, p-type reflector, P type contact layer one or more; And/or,
Be provided with N-shaped current extending between the bottom surface of the surface of described n-type electrode step, the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove and described insulating barrier, described N-shaped current extending conducts electricity with described second n-type electrode and is connected; Described N-shaped current extending comprise in N-shaped metal diffusion barrier layer, N-shaped conductive extension layer, N-shaped reflector, n-contact layer one or more.
In light emitting semiconductor device of the present invention, the light output surface of described semiconductor luminous chip is smooth finished surfaces or patterned surface; Described patterned surface comprise in taper rough surface, convex-concave surface, pyramid shape surface one or more;
Described semiconductor laminated side, n-type electrode step side, n-type electrode shrinkage pool side and/or n-type electrode groove side are vertical with described light output surface or the smooth flat of oblique, smooth surface, structuring plane or structuring curved surface; Described structuring comprise in concavo-convex, sawtooth one or more.
In light emitting semiconductor device of the present invention, described substrate is electrically-conductive backing plate, at described p-type weld pad, p-type interconnecting metal, p-type pad, N-shaped weld pad, N-shaped interconnecting metal, is provided with at least one substrate insulating layer between N-shaped pad and described substrate.
The present invention also provides a kind of manufacture method of above-mentioned light emitting semiconductor device, at least comprises the following steps:
S1, at extension substrate surface, semiconductor laminated described in epitaxial growth successively by the order of N-shaped conductive layer, luminescent layer, p-type electric-conducting layer; By shape and the size of described semiconductor luminous chip, with at least one semiconductor luminous chip of semiconductor laminated preparation in described epitaxial substrate;
Except the light output surface of described semiconductor luminous chip, at all exposed, that there is conductivity surface and at least one insulating barrier of side wrap of described semiconductor luminous chip, and in part or all of described insulating barrier or exposed surface one reflection layer is set; Insulated from each other between described reflection layer and described semiconductor luminous chip;
S2, the first surface preparation conducting channel corresponding with the described semiconductor luminous chip in described epitaxial substrate at substrate, or, after the first surface of the described substrate of tool conductive characteristic prepares described substrate insulating layer, then prepare the conducting channel corresponding with the described semiconductor luminous chip in described epitaxial substrate on described substrate insulating layer surface; Described conducting channel comprises at least one N-shaped weld pad, at least one N-shaped interconnecting metal, at least one N-shaped pad, at least one p-type weld pad, at least one p-type interconnecting metal and at least one p-type pad;
S3, connect described semiconductor luminous chip and substrate: described semiconductor luminous chip is with its semiconductor laminated first surface being arranged on described substrate towards described substrate; The p-type electrode of described semiconductor luminous chip and n-type electrode are close to mutually with p-type weld pad and N-shaped weld pad respectively, and strong bonded conducting;
S4, the epitaxial substrate removed on described semiconductor luminous chip;
S5, along described semiconductor luminous chip periphery, to cut and/or the described substrate that bursts apart obtains discrete semiconductor luminescent device.
The present invention also provides the manufacture method of another kind of above-mentioned light emitting semiconductor device, at least comprises the following steps:
S1, at extension substrate surface, after semiconductor laminated described in epitaxial growth successively by the order of N-shaped conductive layer, luminescent layer, p-type electric-conducting layer, by shape and the size of described semiconductor luminous chip, with at least one semiconductor luminous chip of semiconductor laminated preparation in described epitaxial substrate; Except the light output surface of described semiconductor luminous chip, at all exposed, that there is conductivity surface and at least one insulating barrier of side wrap of described semiconductor luminous chip, and in part or all of described insulating barrier or exposed surface one reflection layer is set; Insulated from each other between described reflection layer and described semiconductor luminous chip;
After S2, thinning described epitaxial substrate, along the periphery of described semiconductor luminous chip, cut and/or described epitaxial substrate of bursting apart, obtain the semiconductor luminous chip of discrete band substrate;
S3, prepare the corresponding conducting channel of at least one and described semiconductor luminous chip at the first surface of substrate, or, after the first surface of the described substrate of tool conductive characteristic prepares described substrate insulating layer, then in the conducting channel that described substrate insulating layer surface preparation is at least one and described semiconductor luminous chip is corresponding; Described conducting channel comprises at least one N-shaped weld pad, at least one N-shaped interconnecting metal, at least one N-shaped pad, at least one p-type weld pad, at least one p-type interconnecting metal and at least one p-type pad;
S4, connect described semiconductor luminous chip and substrate: the semiconductor luminous chip of described discrete band substrate is with its semiconductor laminated first surface being arranged on described substrate towards described substrate; The p-type electrode of described semiconductor luminous chip and n-type electrode are close to mutually with p-type weld pad and N-shaped weld pad respectively, and strong bonded conducting;
S5, the epitaxial substrate removed on described semiconductor luminous chip;
S6, along described semiconductor luminous chip periphery, to cut and/or the described substrate that bursts apart obtains discrete semiconductor luminescent device.
In the manufacture method of light emitting semiconductor device of the present invention, after removing the epitaxial substrate on described semiconductor luminous chip, also comprise: the light output surface of described semiconductor luminous chip or described semiconductor luminous chip light output surface and be enclosed with the surrounding side of described semiconductor luminous chip of described insulating barrier, one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body are set;
Before described light output surface arranges one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body, structuring is carried out to described light output surface, make it to form taper rough surface or convex-concave surface.
In the manufacture method of light emitting semiconductor device of the present invention, described step S1 comprises:
S1.1, at extension substrate surface, by N-shaped conductive layer, luminescent layer, p-type electric-conducting layer order successively epitaxial growth formed semiconductor laminated;
S1.2, described semiconductor laminated on, prepare the corresponding n-type electrode step of at least one semiconductor luminous chip, n-type electrode shrinkage pool and/or n-type electrode groove; The surface of described n-type electrode step is positioned at described N-shaped conductive layer or is positioned at described N-shaped conductive layer surface, and described n-type electrode shrinkage pool and/or n-type electrode groove run through in described p-type electric-conducting layer and luminescent layer to described N-shaped conductive layer or described N-shaped conductive layer surface;
Before or after preparation described n-type electrode step, n-type electrode shrinkage pool and/or n-type electrode groove, prepare cut-in groove along described semiconductor luminous chip periphery; The bottom surface of described cut-in groove is positioned at described epitaxial substrate surface or described epitaxial substrate;
S1.3, described semiconductor laminated outside, comprise the exposed epitaxial substrate surface in described semiconductor laminated surface and side, described cut-in groove place or epitaxial substrate is surperficial and side part or all of, the first insulating barrier be set;
S1.4, on described first insulating barrier for the preparation of the N-shaped through hole arranging n-type electrode, through described first insulating barrier of described N-shaped through hole to the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or described n-type electrode groove;
S1.5, on described first insulating barrier for the preparation of the p-type through hole arranging p-type electrode, through described first insulating barrier of described p-type through hole is to described p-type electric-conducting layer surface; Described first insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier of side;
S1.6, in described N-shaped through hole and described p-type through hole, prepare described n-type electrode and described p-type electrode respectively, described n-type electrode is conducted electricity with described N-shaped conductive layer and is connected, and described p-type electrode conducts electricity with described p-type electric-conducting layer and is connected.
In the manufacture method of light emitting semiconductor device of the present invention, described step S1.3 comprises:
S1.3.1, described semiconductor laminated outside, comprise the exposed epitaxial substrate surface in described semiconductor laminated surface and side, described cut-in groove place or epitaxial substrate is surperficial and side part or all of, the ground floor of described first insulating barrier be set;
S1.3.2, at the described reflection layer of described ground floor surface preparation, described reflection layer is along the exposed epitaxial substrate surface in described semiconductor laminated surface and side and described cut-in groove place or epitaxial substrate is surperficial and side distribution, and with described semiconductor laminated insulation;
S1.3.3, arrange the second layer of described first insulating barrier of the described reflection layer of parcel on the first layer, the described second layer and described ground floor form described first insulating barrier jointly.
In the manufacture method of light emitting semiconductor device of the present invention, described n-type electrode comprises at least one first n-type electrode and at least one second n-type electrode;
Described step S1.4 comprises:
S1.4.1, on described first insulating barrier for the preparation of the second N-shaped through hole arranging the second n-type electrode, through described first insulating barrier of described second N-shaped through hole to the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or described n-type electrode groove;
S1.4.2, in described second N-shaped through hole, prepare described second n-type electrode, conduct electricity in the preparation of the surface of described first insulating barrier and described second n-type electrode the n-type electrode interconnection layer be connected; Described second n-type electrode is conducted electricity with described N-shaped conductive layer and is connected;
S1.4.3, the second insulating barrier is set on described first insulating barrier, for the preparation of arranging the first n-type electrode, through the first N-shaped through hole to described n-type electrode interconnection layer on described second insulating barrier;
In described step S1.5, for the preparation of arranging p-type electrode, through described second insulating barrier and the first insulating barrier p-type through hole to described p-type electric-conducting layer on described second insulating barrier; Described first, second insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier of side;
In described step S1.6, described first n-type electrode and described p-type electrode is prepared respectively in described first N-shaped through hole and described p-type through hole, described first n-type electrode is conducted electricity with described n-type electrode interconnection layer and is connected, and described p-type electrode conducts electricity with described p-type electric-conducting layer and is connected.
In the manufacture method of light emitting semiconductor device of the present invention, described p-type electrode comprises at least one first p-type electrode and at least one second p-type electrode;
Described step S1.4 comprises:
S1.4.1, on described first insulating barrier for the preparation of the second p-type through hole arranging the second p-type electrode, through described first insulating barrier of described second p-type through hole is to described p-type electric-conducting layer surface;
S1.4.2, in described second p-type through hole, prepare described second p-type electrode, prepare the p-type electrode interconnect layers be connected with described second p-type electrodes conduct on the surface of described first insulating barrier; Described second p-type electrode conducts electricity with described p-type electric-conducting layer and is connected;
S1.4.3, the second insulating barrier is set on described first insulating barrier, for the preparation of arranging the first p-type electrode, through the first p-type through hole to described p-type electrode interconnect layers on described second insulating barrier;
In described step S1.5, for the preparation of the N-shaped through hole arranging n-type electrode on described second insulating barrier, through described second insulating barrier of described N-shaped through hole and the first insulating barrier to the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or described n-type electrode groove; Described first, second insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier of side;
In described step S1.6, described n-type electrode and described first p-type electrode is prepared respectively in described N-shaped through hole and described first p-type through hole, described first p-type electrode conducts electricity with described p-type electrode interconnect layers and is connected, and described n-type electrode is conducted electricity with described N-shaped conductive layer and is connected.
In the manufacture method of light emitting semiconductor device of the present invention, described step S1.2 also comprises: at described p-type electric-conducting layer surface coverage p-type current extending; And/or on the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove covers N-shaped current extending;
In described step S1.6, the bottom surface of described p-type electrode is all positioned on described p-type current extending or is all positioned on described p-type electric-conducting layer or is partly positioned at another part on described p-type current extending and is positioned on described p-type electric-conducting layer;
The bottom surface of described n-type electrode is all positioned on described N-shaped current extending or is all positioned on the bottom surface of the surface of described n-type electrode step and/or the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove or is partly positioned at another part on described N-shaped current extending and is positioned on the bottom surface of the surface of described n-type electrode step and/or the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove.
Semiconductor luminescent device structure of the present invention is simple, by arranging insulating barrier and reflection layer, improves light extraction efficiency and the uniformity, excellent heat dissipation performance; And manufacture method is simple and convenient.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the structural representation of light emitting semiconductor device one embodiment of the present invention;
Fig. 2 is the n-type electrode interconnection layer of light emitting semiconductor device shown in Fig. 1 and the structural representation of the second n-type electrode;
Fig. 3 is the structural representation of another embodiment of light emitting semiconductor device of the present invention.
Embodiment
As shown in Figure 1, be the light emitting semiconductor device of one embodiment of the invention, comprise substrate 10 and semiconductor luminous chip.This substrate 10 has first surface and second surface, and described first surface has at least one conducting channel.Described conducting channel is made up of p-type weld pad 19, p-type interconnecting metal 192, p-type pad 191, N-shaped weld pad 18, N-shaped interconnecting metal 182 and N-shaped pad 181.Described semiconductor luminous chip comprises and is arranged at least one semiconductor laminated 11 of first surface.Except the light output surface of semiconductor luminous chip, all exposed, that the there is conductivity surface of this semiconductor luminous chip and side wrap up by least one insulating barrier 12, insulating barrier 12 partly or entirely containing a reflection layer 16; Reflection layer 16 is positioned at insulating barrier 12 or is positioned at the exposed surface of insulating barrier 12, and and insulated from each other between semiconductor luminous chip.
Semiconductor laminated 11 comprise N-shaped conductive layer 11a, the luminescent layer 11b and p-type electric-conducting layer 11c that fold successively and establish, semiconductor laminated 11 are arranged on substrate 10 first surface with its p-type electric-conducting layer towards substrate 10, and the surface of N-shaped conductive layer 11a substrate 10 is dorsad as light output surface.This light output surface can be smooth finished surfaces or patterned surface; Described patterned surface comprise in taper rough surface, convex-concave surface, pyramid shape surface one or more.Patterned surface can increase the forward light extraction efficiency on this N-shaped conductive layer 11a surface.Generally, light output surface can be formed on N-shaped conductive layer; Or be provided with semiconductor transition zone on N-shaped conductive layer, light output surface can be arranged on semiconductor-transition layer.
At least one passivation layer 110 can be had, to keep light output surface from external influence at described light output surface.Described passivation layer 110 adopts printing opacity insulating material, comprises one or more in silica gel, resin, glass, pottery, oxide, nitride.This passivation layer 110 also can wrap up light output surface and have the surrounding side of described semiconductor luminous chip of insulating barrier 12.
P-type electric-conducting layer 11c surface is provided with at least one n-type electrode step, n-type electrode through hole and/or the n-type electrode groove for arranging n-type electrode 14, to expose partially n-type conductive layer 11a, the bottom surface of n-type electrode step, n-type electrode through hole and/or n-type electrode groove is positioned at N-shaped conductive layer 11a or surperficial; Described n-type electrode groove can be the groove of strip, and the opposite end of groove can be closed or open wide; Described n-type electrode through hole can be the hole of circle, the shape such as square.Semiconductor laminated 11 sides, n-type electrode step side, n-type electrode through hole side and/or n-type electrode groove side are vertical with described N-shaped conductive layer 11a surface or the smooth flat of oblique, smooth surface, structuring plane or structuring curved surface; Described structuring comprise in concavo-convex, sawtooth one or more.For reducing the minimizing of luminescent layer 11b area to greatest extent, it is little that the bore of the n-type electrode through hole of making or the width of N-shaped groove should be tried one's best.
At least one p-type electrode 15 and at least one n-type electrode 14 exposed insulating barrier 12 surface and through insulating barrier 12, respectively conduction be connected to p-type electric-conducting layer 11c and N-shaped conductive layer 11a.And p-type electrode 15 and n-type electrode 14 insulate to each other, p-type electrode 15 and luminescent layer 11b, N-shaped conductive layer 11a insulate; N-type electrode 14 is arranged in n-type electrode step, n-type electrode through hole and/or n-type electrode groove, and insulate with luminescent layer 11b and p-type electric-conducting layer 11c.
Due to insulating barrier 12 normally printing opacity thin layer, in order to prevent light by penetrating outside insulating barrier 12, the part or all of of insulating barrier 12 contains a reflection layer 16.This reflection layer 16 is embedded in insulating barrier 12 along semiconductor laminated 11 surfaces and side distribution or is deposited on the exposed surface of insulating barrier 12.Described reflection layer 16 comprise in silver layer, aluminium lamination, Prague total reflection film (DBR) one or more.This reflection layer 16 insulate with semiconductor laminated 11, p-type electrode and n-type electrode.Due to the setting of reflection layer 16, the light that in described semiconductor laminated 11, luminescent layer 11b sends acts on through reflection layer 16, can all be reflexed to light output surface direction, improves light extraction efficiency.
In the present embodiment, n-type electrode comprises at least one first n-type electrode 141 and at least one second n-type electrode 142, between the first n-type electrode 141 and the second n-type electrode 142, be provided with the n-type electrode interconnection layer 171 insulated with reflection layer 16.Described first n-type electrode 141, second n-type electrode 142, n-type electrode interconnection layer 171 and p-type electrode 15 are all wrapped in described insulating barrier 12.Insulating barrier 12 surface covering semiconductor laminated 11 surfaces forms the composition surface of described semiconductor luminous chip and described substrate 10 first surface.At least one p-type electrode 15 and at least one first n-type electrode 141 exposed insulating barrier 12 surface.Wherein, p-type electrode 15 runs through insulating barrier 12 and conducts electricity with p-type electric-conducting layer 11c and be connected; First n-type electrode 141 runs through above insulating barrier 12 to the n-type electrode interconnection layer 171 being positioned at insulating barrier 12, conducts electricity be connected with this n-type electrode interconnection layer 171; N-type electrode interconnection layer 171 to be conducted electricity with N-shaped conductive layer 11a by the second n-type electrode 142 of running through the insulating barrier 12 be positioned at below n-type electrode interconnection layer 171 and is connected.In the present embodiment, be provided with at least one n-type electrode through hole 111 to expose partially n-type conductive layer 11a on p-type electric-conducting layer 11c surface, the second n-type electrode 142 distribution is arranged in n-type electrode through hole 111.Due to the setting of n-type electrode interconnection layer 171, after electric current enters the first n-type electrode 141, first can through the n-type electrode interconnection layer 171 of tool excellent conductive performance, the balanced current distribution imported in all second n-type electrode 142, because described second n-type electrode 142 is evenly distributed on whole semiconductor laminated 11, make the electric current imported by the first n-type electrode 141 can be evenly distributed on whole semiconductor laminated 11, when their vertical currents are through described luminescent layer 11b, uniform luminescence will be produced.
N-type electrode interconnection layer 171 can be the conductive metal layer that the metal or alloy material with electric conductivity is made.The setting of this n-type electrode interconnection layer 171 does not limit, and can be single layer structure or sandwich construction, and its shape does not limit, such as, can be rectangle, circle etc., it may correspond to p-type electrode 15 and is provided with through hole to insulate with p-type electrode 15.N-type electrode interconnection layer 171 also can latticed conductive metal layer as shown in Figure 2, comprises the metal level 171a conducting electricity and be connected to around each second n-type electrode 142, and the bonding jumper 171b coupled together by metal level 171a.
In semiconductor laminated 11,11c is thinner for p-type electric-conducting layer, and electric conductivity is poor, in order to ensure electric current energy uniform vertical by luminescent layer 11b, can establish p-type current extending 150 on the surface at p-type electric-conducting layer 11c.P-type current extending 150 1 aspect has good conductive characteristic, on the other hand can form low resistance contacts or low-resistance Ohm contact with p-type electric-conducting layer 11c, this p-type current extending 150 comprise in p-type metal diffusion barrier layer, p-type electric-conducting extension layer, p-type reflector, P type contact layer one or more.When p-type current extending comprises p-type reflector, the amount of light from light output surface can be improved.The material that p-type metal diffusion barrier layer uses comprise in refractory metal, refractory metal nitride, refractory carbide and refractory metal ternary alloy three-partalloy one or more, refractory metal comprises one or more of W, Ti, Mo, Ta, TiW.The material that p-type electric-conducting extension layer uses comprise in ITO, Ag, Au, Al, Cr, Ti, Pt, Pd, Ni, W, ZnO one or more, the material that P type contact layer uses comprise in ITO, Al, Cr, Ti, Pt, Pd, Ni, NiO, ZnO, heavily doped low resistance P-type conductive layer one or more, the material that p-type reflector uses comprise in Ag, Al, Prague total reflection film (DBR) one or more.
In the present embodiment, p-type electrode 15 is conducted electricity with p-type electric-conducting layer 11c by p-type current extending 150 and is connected.Understandable, p-type electrode 15 also can partly run through p-type current extending 150, directly contacts to be formed to conduct electricity to connect with p-type electric-conducting layer 11c, and remainder and p-type current extending 150 directly contact to be formed to conduct electricity and connect.
Be appreciated that in n-type electrode ledge surface, n-type electrode groove and/or n-type electrode through hole bottom surface, the N-shaped current extending 140 with described p-type current extending 150 with phase same-action and function also can be set.This N-shaped current extending 140 also can comprise in N-shaped metal diffusion barrier layer, N-shaped conductive extension layer, N-shaped reflector, n-contact layer one or more.The material that N-shaped metal diffusion barrier layer uses comprise in refractory metal, refractory metal nitride, refractory carbide and refractory metal ternary alloy three-partalloy one or more, refractory metal comprises one or more of W, Ti, Mo, Ta, TiW.The material that N-shaped conductive extension layer uses comprise in ITO, Ag, Au, Al, Cr, Ti, Pt, Pd, Ni, W, ZnO one or more, the material that n-contact layer uses comprise in ITO, Al, Cr, Ti, Pt, Pd, Ni, NiO, ZnO, heavily doped low-resistance n-type conductive layer one or more, the material that N-shaped reflector uses comprise in Ag, Al, Prague total reflection film (DBR) one or more.
Shown in figure 1, in the present embodiment, the second n-type electrode 142 is conducted electricity with N-shaped conductive layer 11a by N-shaped current extending 140 and is connected.Understandable, the second n-type electrode 142 also can partly run through N-shaped current extending 140, directly contacts to be formed to conduct electricity to connect with N-shaped conductive layer 11a, and remainder and N-shaped current extending 140 directly contact to be formed to conduct electricity and connect.
When N-shaped current extending 140 comprises N-shaped reflector, and/or when p-type current extending 150 comprises p-type reflector, this N-shaped current extending 140 and/or p-type current extending 150 can not establish reflection layer 16.
Light emitting semiconductor device of the present invention, insulating barrier 12 is provided with at least one deck, except described N-shaped conductive layer 11a surface, described p-type electric-conducting layer 11c surface, semiconductor laminated 11 sides, n-type electrode ledge surface and side, n-type electrode through hole bottom surface and side, n-type electrode groove floor and side wrap up by described insulating barrier 12.Arranging of insulating barrier 12 can effectively prevent from, in whole light emitting semiconductor device preparation process, occurring short circuit and electric leakage between N-shaped conductive layer and p-type electric-conducting layer, promotes process rate and device reliability.The material preparing this insulating barrier 12 comprises silicon dioxide, alundum (Al2O3), aluminium nitride, titanium oxide and silicon nitride etc.In the present embodiment, all surfaces that is exposed, that have conductivity and side comprise p-type electric-conducting layer 11c surface, semiconductor laminated 11 sides, n-type electrode through hole 111 bottom surface and side, as shown in Figure 1 not the exposed surface of N-shaped conductive layer 11a that covers by the second n-type electrode 142 and exposed sides, the exposed surface of p-type electric-conducting layer 11c do not covered by p-type electrode 15 and/or p-type current extending 150 and exposed sides, p-type current extending 150 surface and side, the exposed sides of luminescent layer 11b and n-type electrode through hole 111 side etc.
Same material can be adopted between multilayer dielectric layer 12 also can to adopt different materials.Insulating barrier 12, second n-type electrode 142 arranged for multilayer also can multilayer be arranged, and all forms conduction by n-type electrode interconnection layer 171 and connect between every one deck second n-type electrode 142.
Substrate 10 can adopt insulated substrate, comprises ceramic substrate, glass substrate, crystallite glass substrate, plastic base or composite construction substrate.Be understandable that, substrate 10 also can adopt electrically-conductive backing plate, electrically-conductive backing plate can for metal substrate or other there is the substrate of conductive characteristic, the operable material of metal substrate comprise in iron, ferroalloy, copper, copper alloy, aluminium, aluminium alloy, molybdenum, molybdenum alloy one or more.When substrate 10 is electrically-conductive backing plate, between substrate 10 and conducting channel, i.e. substrate 10 and be provided with a substrate insulating layer between p-type weld pad 19, p-type interconnecting metal 192, p-type pad 191, N-shaped weld pad 18, N-shaped interconnecting metal 182 and N-shaped pad 181.In the present embodiment, substrate 10 is insulated substrate.The first surface of described substrate 10 can be smooth planar surface, also can with the smooth surface of concavo-convex platform.
Described conducting channel is arranged on the first surface of substrate 10, in this conducting channel, insulated from each other between p-type weld pad 19 and N-shaped weld pad 18.The position conducting electricity with p-type electrode 15 that at least one p-type layer 19a is close to the exposed p-type electrode 15 on insulating barrier 12 surface is connected, and the position conducting electricity with n-type electrode 14 that at least one N-shaped layer 18a is close to the exposed n-type electrode 14 on insulating barrier 12 surface is connected.And the area of this p-type layer 19a is greater than p-type electrode 15, it connects p-type weld pad 19 for p-type electrode 15 provides certain connection area to conduct electricity, and is convenient to the connection of p-type weld pad 19 and p-type electrode 15; The area of N-shaped layer 18a is greater than n-type electrode 14, and it connects N-shaped weld pad 18 for n-type electrode 14 provides certain connection area to conduct electricity, and is convenient to the connection of N-shaped weld pad 18 and n-type electrode 14.This p-type layer 19a and N-shaped layer 18a integrally can conduct electricity respectively and be connected to form on p-type electrode 15 and n-type electrode 14, and is close to insulating barrier 12 surface.In the present embodiment, the position conducting electricity with the first n-type electrode 141 that N-shaped layer 18a is close to exposed first n-type electrode 141 on insulating barrier 12 surface is connected.
Due to semiconductor luminous chip surface wrap up by insulating barrier 12, the expansion of the first n-type electrode 141 and p-type electrode 15 can be fully played, thus make partial insulative layer 12 be wrapped in semiconductor laminated 11 and p-type layer 19a, between semiconductor laminated 11 and N-shaped layer 18a.Understandable, p-type layer 19a and N-shaped layer 18a can be set as required simultaneously, or arrange as required wherein any one.This semiconductor laminated 11 to be conducted electricity respectively by p-type layer 19a and N-shaped layer 18a and is connected on p-type weld pad 19 and N-shaped weld pad 18, and described semiconductor luminous chip is fixed on the first surface of substrate 10.Method of attachment comprise in bonding, eutectic weldering, ultrasonic bonding, soldering one or more.
P-type weld pad 19 and N-shaped weld pad 18 are by one or more in metal foil laminated, chemical plating, plating, sputtering, evaporation, silk screen printing, mask printing process, direct preparation on the substrate 10, then is conducted electricity with p-type electrode 15 or p-type layer 19a and the first n-type electrode 141 or N-shaped layer 18a respectively and is connected.Described substrate 10 is also provided with at least one p-type pad 191 that is connected and at least one N-shaped pad 181 be connected that conducts electricity with N-shaped weld pad 18 of conducting electricity with p-type weld pad 19.Described pad can realize conducting electricity with the external world and be connected.
It is one or more that the setting position of p-type pad 191 and N-shaped pad 181 comprises in substrate 10 first surface, substrate 10 second surface, substrate 10 side; And p-type pad 191 to conduct electricity with p-type weld pad 19 by p-type interconnecting metal 192 and is connected, N-shaped pad 181 to conduct electricity with N-shaped weld pad 18 by N-shaped interconnecting metal 182 and is connected.Described p-type interconnecting metal 192 and the position of N-shaped interconnecting metal 182 process comprise described substrate 10 first surface, described substrate 10 second surface, described substrate 10 side, it is one or more to run through in described substrate 10.Or described p-type pad 191 is conduct electricity through substrate 10 and p-type weld pad 19 the p-type needle-like pad be connected, described N-shaped pad 181 is conduct electricity through substrate 10 and N-shaped weld pad 18 the N-shaped needle-like pad be connected.
In the present invention, directly N-shaped conductive layer 11a surface or one or more (not shown) that can arrange further on described passivation layer 110 surface in fluorescence coating, encapsulated layer, packaging body.Described fluorescence coating comprises phosphor powder layer, be mixed with in the layer of silica gel of fluorescent material, resin bed, glassy layer one or more.Described encapsulated layer comprise in layer of silica gel, resin bed, glassy layer one or more.Described fluorescence coating is for the preparation of white light emitting device, and described encapsulated layer or packaging body are except the described fluorescence coating of protection is from except ectocine, also can make different shapes and play the effect of getting light and optically focused.
During making, first in epitaxial substrate, form described semiconductor laminated 11 by the order epitaxial growth of N-shaped conductive layer 11a, luminescent layer 11b and p-type electric-conducting layer 11c, for guaranteeing that light is better reflected back semiconductor laminated 11 by reflection layer 16, n-type electrode through hole 111 is made inverted trapezoidal, and n-type electrode through hole 111 bottom width is less than the width of n-type electrode through hole 111 opening part.Can be provided with indent in described semiconductor luminous chip surrounding, indent is positioned at semiconductor laminated 11 sides; Or as shown in Figure 1, when preparing multiple described semiconductor luminous chip in same described epitaxial substrate, prepare cut-in groove 101 along line of cut 100 position; Cut-in groove 101 between adjacent two semiconductor luminous chips is V-type setting, and the reflection layer 16 that the prism formed in cut-in groove 101 is beneficial to the side of being located thereon better reflects.Surface or cut-in groove 101 surface of indent are also wrapped up wherein by insulating barrier 12, form insulation.
Conducting channel can first be arranged on substrate 10 first surface, then is fixed together with semiconductor laminated 11 by the substrate 10 with conducting channel.Then the mode comprising chemical stripping or the thinning rear chemical corrosion of grinding or laser lift-off can be adopted to remove epitaxial substrate.The N-shaped conductive layer 11a surface that structuring is exposed again covers passivation layer 110 afterwards or covers passivation layer, fluorescence coating, encapsulated layer, one or more in packaging body.After completing, then press the size and shape of described light emitting semiconductor device, cut along line of cut 100 or the substrate 10 that bursts apart, cut-in groove 101 is divided into two, obtains discrete flip semiconductor luminescent device.
Shown in composition graphs 1, the manufacture method of the light emitting semiconductor device of above-described embodiment, at least comprises the following steps:
S1, at extension substrate surface, by the order epitaxial semiconductor lamination 11 successively of N-shaped conductive layer 11a, luminescent layer 11b, p-type electric-conducting layer 11c; By shape and the size of semiconductor luminous chip, with at least one semiconductor luminous chip of semiconductor laminated 11 preparation in epitaxial substrate;
Except the light output surface of semiconductor luminous chip, at all exposed, that there is conductivity surface and at least one insulating barrier 12 of side wrap of semiconductor luminous chip, and in part or all of insulating barrier 12 or exposed surface one reflection layer 16 is set; Insulated from each other between reflection layer 16 and semiconductor luminous chip.
Concrete, this step S1 comprises:
S1.1, at extension substrate surface, by N-shaped conductive layer 11a, luminescent layer 11b, p-type electric-conducting layer 11c order successively epitaxial growth form semiconductor laminated 11.Understandable, N-shaped conductive layer 11a, luminescent layer 11b, p-type electric-conducting layer 11c etc. can adopt existing various technique and technology to complete in the epitaxial growth of substrate.
S1.2, on semiconductor laminated 11, prepare the corresponding n-type electrode step of at least one semiconductor luminous chip, n-type electrode shrinkage pool and/or n-type electrode groove; The surface of n-type electrode step is positioned at N-shaped conductive layer 11a or is positioned at N-shaped conductive layer 11a surface, and n-type electrode shrinkage pool and/or n-type electrode groove run through in p-type electric-conducting layer 11c and luminescent layer 11b to N-shaped conductive layer 11a or N-shaped conductive layer 11a surface.
Before or after preparation n-type electrode step, n-type electrode shrinkage pool and/or n-type electrode groove, prepare cut-in groove 101 along semiconductor luminous chip periphery; The bottom surface of cut-in groove 101 is positioned at epitaxial substrate first surface or epitaxial substrate.
This step comprises further: at the p-type electric-conducting layer 11c surface coverage p-type current extending 150 of semiconductor laminated 11, to improve electric conductivity.Form the p-type metal diffusion barrier layer of p-type electric current expansion layer 150, p-type electric-conducting extension layer, p-type reflector, P type contact layer, existing various technique can be adopted to make.In addition, also optionally also cover N-shaped current extending 140 on N-shaped conductive layer 11a surface, N-shaped current extending 140 is arranged on n-type electrode ledge surface, n-type electrode groove floor and/or n-type electrode shrinkage pool bottom surface.Form the N-shaped metal diffusion barrier layer of N-shaped electric current expansion layer 140, N-shaped conductive extension layer, N-shaped reflector, n-contact layer, existing various technique can be adopted to make.
In this step, before or after preparation described n-type electrode step, n-type electrode groove and/or n-type electrode shrinkage pool, can prepare indent or cut-in groove 101 along semiconductor luminous chip periphery, the bottom surface of cut-in groove 101 is positioned at epitaxial substrate surface or epitaxial substrate.
In the present embodiment method, forming n-type electrode shrinkage pool 111 by making on semiconductor laminated 11, exposing N-shaped conductive layer 11a.
S1.3, outside semiconductor laminated 11, comprise that the exposed epitaxial substrate in semiconductor laminated 11 surfaces and side, cut-in groove 101 place is surperficial or epitaxial substrate is surperficial and side part or all of, the first insulating barrier is set.This step comprises:
S1.3.1, outside semiconductor laminated 11, comprise that the exposed epitaxial substrate in semiconductor laminated 11 surfaces and side, described cut-in groove 101 place is surperficial or epitaxial substrate is surperficial and side part or all of, the ground floor of the first insulating barrier is set.In the present embodiment, this ground floor has wrapped up and has comprised the exposed epitaxial substrate side in exposed semiconductor laminated 11 sides in the surperficial and side of p-type current extending 150 surface and side, exposed p-type electric-conducting layer 11c surface and side, exposed n-type electrode shrinkage pool 111 bottom surface and sidewall, N-shaped current extending 140 surface and side, exposed luminescent layer 11b side, exposed N-shaped conductive layer 11a, cut-in groove 101 place and cut-in groove 101 place and bottom surface thereof etc.
S1.3.2, prepare reflection layer 16 on ground floor surface, reflection layer 16 is along the exposed epitaxial substrate surface in semiconductor laminated 11 surfaces and side and cut-in groove 101 place or epitaxial substrate is surperficial and side distributes, and insulate with semiconductor laminated 11.
S1.3.3, arrange the second layer of the first insulating barrier of parcel reflection layer 16 on the first layer, the second layer and described ground floor form the first insulating barrier jointly.
S1.4, on the first insulating barrier for the preparation of the N-shaped through hole arranging n-type electrode 14, through first insulating barrier of N-shaped through hole to the surface of n-type electrode step, the bottom surface of n-type electrode shrinkage pool and/or the bottom surface of n-type electrode groove.In the present embodiment, the bottom surface of through first insulating barrier of N-shaped through hole and reflection layer 16 to n-type electrode shrinkage pool.
S1.5, on the first insulating barrier for the preparation of the p-type through hole arranging p-type electrode 15, through first insulating barrier of p-type through hole to p-type electric-conducting layer 11c surface; First insulating barrier forms the surface that is all exposed, that have conductivity of parcel semiconductor luminous chip and the insulating barrier 12 of side.
S1.6, in N-shaped through hole and p-type through hole, prepare n-type electrode 14 and p-type electrode 15 respectively, n-type electrode 14 is led 11a with N-shaped conductive layer and is electrically connected, and p-type electrode 15 conducts electricity with p-type electric-conducting layer 11c and is connected, and n-type electrode 14 and p-type electrode 15 insulate with reflection layer 16.
The bottom surface of p-type electrode 15 is all positioned on p-type current extending 150 or is all positioned on p-type electric-conducting layer 11c or is partly positioned at another part on p-type current extending 150 and is positioned on p-type electric-conducting layer 11c.The bottom surface of n-type electrode 14 is all positioned on N-shaped current extending 140 or is all positioned on the bottom surface of the surface of n-type electrode step and/or the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove or is partly positioned at another part on N-shaped current extending 140 and is positioned on the bottom surface of the surface of n-type electrode step and/or the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove.
Wherein, n-type electrode 14 can comprise at least one first n-type electrode 141 and at least one second n-type electrode 142, and therefore step S1.4 comprises:
S1.4.1, on the first insulating barrier for the preparation of the second N-shaped through hole arranging the second n-type electrode 142, through first insulating barrier of the second N-shaped through hole to the surface of n-type electrode step, the bottom surface of n-type electrode shrinkage pool and/or the bottom surface of n-type electrode groove; As shown in Figure 1, the second N-shaped through hole is through to n-type electrode shrinkage pool 111 bottom surface.When n-type electrode shrinkage pool 111 bottom surface is provided with N-shaped current extending 140, the second N-shaped through hole bottom surface is all positioned on N-shaped current extending 140 or is partly positioned at another part on N-shaped current extending 140 and is positioned on n-electrode shrinkage pool 111 bottom surface or is all positioned on n-electrode shrinkage pool 111 bottom surface.
S1.4.2, in the second N-shaped through hole, prepare the second n-type electrode 142, conduct electricity in the preparation of the surface of the first insulating barrier and the second n-type electrode 142 the n-type electrode interconnection layer 171 be connected; Second n-type electrode 142 is conducted electricity with N-shaped conductive layer 11a and is connected.
S1.4.3, the second insulating barrier is set on the first insulating barrier, over the second dielectric for the preparation of arranging the first n-type electrode 141, through the first N-shaped through hole to n-type electrode interconnection layer 171.
In step S1.5, over the second dielectric for the preparation of arranging p-type electrode 15, through second insulating barrier and the first insulating barrier p-type through hole to p-type electric-conducting layer 11c.First, second insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier 12 of side.
In step S1.6, the first n-type electrode 141 and p-type electrode 15 is prepared respectively in the first N-shaped through hole and p-type through hole, first n-type electrode 141 is conducted electricity with n-type electrode interconnection layer 171 and is connected, and p-type electrode 15 conducts electricity with p-type electric-conducting layer 11c and is connected, and insulate with n-type electrode interconnection layer 171.P-type electrode 15 also can establish multilayer, and its method to set up can with reference to n-type electrode 14.
S2, the first surface preparation conducting channel corresponding with the semiconductor luminous chip in epitaxial substrate at substrate 10, or, after the first surface of the substrate 10 of tool conductive characteristic prepares substrate insulating layer, then prepare the conducting channel corresponding with the semiconductor luminous chip in epitaxial substrate on substrate insulating layer surface.Conducting channel by one or more preparations in metal foil laminated, chemical plating, plating, sputtering, evaporation, silk screen printing, mask printing process on the substrate 10.Conducting channel comprises at least one N-shaped weld pad 18, at least one N-shaped interconnecting metal 182, at least one N-shaped pad 181, at least one p-type weld pad 19, at least one p-type interconnecting metal 192 and at least one p-type pad 191.Wherein, p-type pad 191 and N-shaped pad 181 to conduct electricity with p-type weld pad 19 and N-shaped weld pad 18 respectively by p-type interconnecting metal 192 and N-shaped interconnecting metal 182 and are connected.
S3, connect semiconductor luminous chip and substrate 10: semiconductor luminous chip is with its semiconductor laminated 11 first surface being arranged on substrate 10 towards substrate 10; The p-type electrode 15 of semiconductor luminous chip and n-type electrode 14 are close to mutually with p-type weld pad 19 and N-shaped weld pad 18 respectively, and strong bonded conducting.Associated methods comprise in bonding, eutectic weldering, ultrasonic bonding, soldering one or more.
In the present embodiment, also prepare on the surface of insulating barrier 12 and have p-type layer 19a and N-shaped layer 18a, p-type layer 19a and N-shaped layer 18a is close to p-type electrode 15 and n-type electrode 14 place on insulating barrier 12 surface respectively, conducts electricity respectively be connected with p-type electrode 15 and n-type electrode 14.The area of this p-type layer 19a and N-shaped layer 18a is greater than p-type electrode 15 and n-type electrode 14 respectively.P-type electrode 15 and n-type electrode 14 to be conducted electricity with p-type weld pad 19 and N-shaped weld pad 18 respectively by this p-type layer 19a and N-shaped layer 18a and are connected.The preparation of this p-type layer 19a and N-shaped layer 18a, also when preparing p-type electrode 15 and n-type electrode 14, can be integrally formed in p-type electrode 15 and n-type electrode 14, and is close to insulating barrier 12 surface.
S4, the epitaxial substrate removed on semiconductor luminous chip.The mode comprising chemical stripping or the thinning rear chemical corrosion of grinding or laser lift-off can be adopted to remove epitaxial substrate.
After removal epitaxial substrate, also comprise: the light output surface of semiconductor luminous chip or semiconductor luminous chip light output surface and be enclosed with the surrounding side of semiconductor luminous chip of insulating barrier 12, one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body are set.
Before semiconductor laminated 11 surfaces and side arrange one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body.Wherein before described passivation layer etc. is set, light output surface is comprised to semiconductor laminated 11 surfaces, carries out structuring, make it to form taper rough surface or convex-concave surface.In the present embodiment, at least one passivation layer 110 is set at light output surface.Passivation layer 110 adopts printing opacity insulating material, comprises one or more in silica gel, resin, glass, pottery, oxide, nitride.
S5, along semiconductor luminous chip periphery, line of cut 100 as shown in Figure 1, cuts and/or the substrate 10 that bursts apart obtains discrete semiconductor luminescent device.
As shown in Figure 3, it is the light emitting semiconductor device of another embodiment of the present invention, comprise substrate 20, substrate insulating layer 20a, semiconductor laminated 21, insulating barrier 22, reflection layer 26, at least one p-type electrode 25, at least one n-type electrode 24, n-type electrode interconnection layer 271, p-type electrode interconnect layers 272, N-shaped weld pad 28, N-shaped layer 28a, p-type layer 29a and p-type weld pad 29.Wherein, semiconductor laminated 21, insulating barrier 22, p-type electrode 25, n-type electrode 24, n-type electrode interconnection layer 271, p-type electrode interconnect layers 272, N-shaped layer 28a and p-type layer 29a etc. are common forms described semiconductor luminous chip.Semiconductor luminous chip is arranged on substrate 20 first surface.
Except the light output surface of semiconductor luminous chip, all exposed, that the there is conductivity surface of this semiconductor luminous chip and side wrap up by least one described insulating barrier 22, reflection layer 26 is positioned at insulating barrier 22 or is positioned at the exposed surface of insulating barrier 22, and and insulated from each other between semiconductor luminous chip.
Semiconductor laminated 21 to comprise folded the N-shaped conductive layer 21a, the luminescent layer 21b that establish and p-type electric-conducting layer 21c, N-shaped conductive layer 21a surface be successively light output surface.N-type electrode 24 comprises at least one first n-type electrode 241 and at least one second n-type electrode 242; Second n-type electrode 242 is conducted electricity with N-shaped conductive layer 21a and is connected, and n-type electrode interconnection layer 271 conducts electricity and connects first, second n-type electrode 241,242, and p-type electrode 25 conducts electricity with p-type electric-conducting layer 21c and is connected; Described p-type electrode 25 and the first n-type electrode 241, insulated from each other between n-type electrode interconnection layer 271 and the second n-type electrode 242.
Be different from above-described embodiment of this embodiment, described light emitting semiconductor device also comprises p-type electrode interconnect layers 272, this p-type electrode interconnect layers 272 is wrapped in insulating barrier 22, conducts electricity be connected with p-type electrode 25, and insulate with reflection layer 26 and n-type electrode interconnection layer 271 insulate.Described p-type electrode 25 can comprise at least one first p-type electrode 251 and at least one second p-type electrode 252, first p-type electrode 251 is exposed on insulating barrier 24 surface, and run through the insulating barrier 22 be positioned at above p-type electrode interconnect layers 272 and conduct electricity with p-type electrode interconnect layers 272 and be connected, second p-type electrode 252 runs through the insulating barrier 22 be positioned at below p-type electrode interconnect layers 272 and conducts electricity with p-type electric-conducting layer 21c and be connected, and p-type electrode interconnect layers 272 is conducted electricity with p-type electric-conducting layer 21c by the second p-type electrode 252 and is connected; And the second p-type electrode 252 insulate with n-type electrode interconnection layer 271, luminescent layer 21b and N-shaped conductive layer 21a.
This p-type electrode interconnect layers 272 has identical function with n-type electrode interconnection layer 271, by the setting of p-type electrode interconnect layers 272, ensure that electric current is evenly distributed in p-type electric-conducting layer 21c, when electric current imports the first p-type electrode 251, namely electric current is evenly circulated to all second p-type electrodes 252 by p-type electrode interconnect layers 272, make uniform current on whole p-type electric-conducting layer 21c surface, to realize the uniformly light-emitting of semiconductor luminous chip.P-type electrode interconnect layers 272 can be the conductive metal layer that the metal or alloy material with electric conductivity is made, and its setting can refer to n-type electrode interconnection layer 271.
Insulating barrier 22, the second p-type electrode 252 arranged for multilayer also can multilayer be arranged, and all forms conduction by p-type electrode interconnect layers 272 and connect between every one deck second p-type electrode 252.
In the present embodiment, substrate 20 is electrically-conductive backing plate, a substrate insulating layer 20a is had at described substrate 20 first surface, conducting channel is prepared on described substrate insulating layer 20a, and conducting channel comprises N-shaped weld pad 28, N-shaped interconnecting metal 282, N-shaped pad 281, p-type weld pad 29, p-type interconnecting metal 292 and p-type pad 291.Insulated from each other between this p-type weld pad 29 and N-shaped weld pad 28.P-type layer 29a is close to the position conducting electricity with the first p-type electrode 251 that insulating barrier 22 surface exposure the first p-type electrode 251 and is connected, and N-shaped layer 28a is close to the position conducting electricity with the first n-type electrode 241 that insulating barrier 22 surface exposure the first n-type electrode 241 and is connected.P-type layer 29a and N-shaped layer 28a conduct electricity with p-type weld pad 29 and N-shaped weld pad 28 respectively and are connected, and described semiconductor luminous chip is fixedly connected on the first surface of described substrate 20.Method of attachment comprise in bonding, eutectic weldering, ultrasonic bonding, soldering one or more.
Described p-type pad 291 and N-shaped pad 281 realize conducting electricity with the external world and are connected.It is one or more that the setting position of p-type pad 291 and N-shaped pad 281 comprises in substrate 20 first surface, substrate 20 second surface, substrate 20 side; And p-type pad 291 to conduct electricity with p-type weld pad 29 by p-type interconnecting metal 292 and is connected, N-shaped pad 281 to conduct electricity with N-shaped weld pad 28 by N-shaped interconnecting metal 282 and is connected.Described p-type interconnecting metal 292 and the position of N-shaped interconnecting metal 282 process comprise substrate 20 first surface, substrate 20 second surface, substrate 20 side, it is one or more to run through in substrate 20.Or described p-type pad 291 is conduct electricity through substrate 20 and p-type weld pad 29 the p-type needle-like pad be connected, described N-shaped pad 281 is conduct electricity through substrate 20 and N-shaped weld pad 28 the N-shaped needle-like pad be connected.In the present embodiment, N-shaped weld pad 28, N-shaped interconnecting metal 282, N-shaped pad 281, p-type weld pad 29, p-type interconnecting metal 292 and p-type pad 291 are all arranged on the substrate insulating layer 20a of the first surface of substrate 20.
Arrange conduction as required connect the N-shaped current extending 240 of n-type electrode 24 and conduct electricity and be connected the p-type electrode extension layer 250 of p-type electrode 25, wherein any one or two kinds can be set and all arrange.
From different being also embodiment illustrated in fig. 1, in the present embodiment, at least one described semiconductor luminous chip forming single light emitting semiconductor device is independently arranged on the surface of described substrate insulating layer 20a.Whole semiconductor luminous chip, comprises light output surface, is passivated layer 210, fluorescence coating 220, and packaging body 230 wrap up (as Fig. 3).Packaging body, except protection fluorescence coating is from except ectocine, also can be made different shapes and play the effect of getting light and optically focused.
During making, first form semiconductor laminated 21 at epitaxial substrate Epitaxial growth, arrange cut-in groove along described semiconductor laminated 21 surroundings, conducting channel can first be arranged on substrate 20 first surface; After semiconductor luminous chip processing technology completes, thinning epitaxial substrate, then along cut-in groove cutting or described epitaxial substrate of bursting apart, obtain the semiconductor luminous chip of discrete band epitaxial substrate.Then, described semiconductor luminous chip and substrate 20 are fixed together.Remove epitaxial substrate, the N-shaped conductive layer 21a that structuring is exposed, then prepare passivation layer 210, core photosphere 220 and packaging body 230 on described N-shaped conductive layer 21a.Finally, by the size and shape of described light emitting semiconductor device, cut along line of cut 200 or the substrate 20 that bursts apart, obtain discrete semiconductor luminescent device.
The manufacture method of above-mentioned light emitting semiconductor device embodiment illustrated in fig. 3, at least comprises the following steps:
S1, at extension substrate surface, by the order of N-shaped conductive layer 21a, luminescent layer 21b, p-type electric-conducting layer 21c successively described in epitaxial growth after semiconductor laminated 21, by shape and the size of semiconductor luminous chip, with at least one semiconductor luminous chip of semiconductor laminated 21 preparation in epitaxial substrate.
Except the light output surface of semiconductor luminous chip, at all exposed, that there is conductivity surface and at least one insulating barrier 22 of side wrap of semiconductor luminous chip, and in part or all of described insulating barrier 22 or exposed surface one reflection layer 26 is set; Insulated from each other between reflection layer 26 and described semiconductor luminous chip.
After S2, thinning epitaxial substrate, along the periphery of semiconductor luminous chip, cut and/or epitaxial substrate of bursting apart, obtain the semiconductor luminous chip of discrete band substrate.
S3, prepare at least one conducting channel corresponding with semiconductor luminous chip at the first surface of substrate 20, or, as shown in Figure 3, in the present embodiment, substrate 20 is electrically-conductive backing plate, after the first surface of the substrate 20 of tool conductive characteristic prepares substrate insulating layer 20a, then at least one conducting channel corresponding with semiconductor luminous chip of substrate insulating layer 20a surface preparation.Conducting channel comprises at least one N-shaped weld pad 28, at least one N-shaped interconnecting metal 282, at least one N-shaped pad 281, at least one p-type weld pad 29, at least one p-type interconnecting metal 292 and at least one p-type pad 291.The setting of substrate insulating layer 20a can adopt existing techniques in realizing.
S4, connect semiconductor luminous chip and substrate 20: the semiconductor luminous chip of discrete band substrate is with its semiconductor laminated 21 first surface being arranged on substrate 20 towards substrate 20; The p-type electrode 25 of semiconductor luminous chip and n-type electrode 24 are close to mutually with p-type weld pad 29 and N-shaped weld pad 28 respectively, and strong bonded conducting.In the present embodiment, p-type electrode 25 and n-type electrode 24 to be conducted electricity with p-type weld pad 29 and N-shaped weld pad 28 by the p-type layer 29a of the p-type electrode 25 with n-type electrode 24 place that are separately positioned on insulating barrier 22 surface and N-shaped layer 28a and are connected.
S5, the epitaxial substrate removed on semiconductor luminous chip.
S6, along semiconductor luminous chip periphery, as line of cut 200, to cut and/or the substrate 20 that bursts apart obtains discrete semiconductor luminescent device.
The concrete operations of the present embodiment manufacture method can refer to the manufacture method of above-described embodiment, and different being: p-type electrode 25 includes the first p-type electrode 251 and the second p-type electrode 252, prepares p-type electrode interconnect layers 272 and realize between the second p-type electrode 252 and to be connected with conducting electricity between the first p-type electrode 251 between the second p-type electrode 252.
Therefore, the S1.4 of step S1 comprises:
S1.4.1, on the first insulating barrier for the preparation of the second p-type through hole arranging the second p-type electrode 252, through first insulating barrier of the second p-type through hole to p-type electric-conducting layer 21c surface.
S1.4.2, in the second p-type through hole, prepare the second p-type electrode 252, conduct electricity in the preparation of the surface of the first insulating barrier and the second p-type electrode 252 the p-type electrode interconnect layers 272 be connected.Second p-type electrode 252 conducts electricity with p-type electric-conducting layer 21c and is connected.
S1.4.3, the second insulating barrier is set on the first insulating barrier, over the second dielectric for the preparation of arranging the first p-type electrode 251, through the first p-type through hole to p-type electrode interconnect layers 272.
In step S1.5, over the second dielectric for the preparation of the N-shaped through hole arranging n-type electrode 24, through second insulating barrier of N-shaped through hole and the first insulating barrier to the surface of n-type electrode step, the bottom surface of n-type electrode shrinkage pool and/or the bottom surface of described n-type electrode groove; First, second insulating barrier forms the surface that is all exposed, that have conductivity of parcel semiconductor luminous chip and the insulating barrier 22 of side.
In step S1.6, in N-shaped through hole and the first p-type through hole, prepare n-type electrode 24 and the first p-type electrode 25, first p-type electrode 241 respectively conduct electricity with p-type electrode interconnect layers 272 and be connected, n-type electrode 24 is conducted electricity with N-shaped conductive layer 21a and is connected.
When n-type electrode 24 comprises at least one first n-type electrode 241 and at least one second n-type electrode 242, can by insulating barrier 22 points three layers setting, set-up mode does not limit, such as: first arrange containing the ground floor of reflection layer 26, then the second N-shaped through hole is prepared, in the second N-shaped through hole, prepare the second n-type electrode 241 of this ground floor through, and in the second n-type electrode 241, prepare the n-type electrode interconnection layer 271 be connected with its conduction; Then the second layer of insulating barrier 22 is prepared on the first layer, prepare the second p-type through hole of first, second layer through, the second p-type electrode 252 is prepared in the second p-type through hole, p-type electrode interconnect layers 272, the second p-type electrode 252 that preparation is connected with its conduction on the second p-type electrode 252, p-type electrode interconnect layers 272 all insulate with n-type electrode interconnection layer 271; Prepare the third layer of insulating barrier 22 more on the second layer, third layer is prepared the first p-type through hole of through p-type electrode interconnect layers 272, and prepare the first N-shaped through hole of the through second layer to n-type electrode interconnection layer 271, in the first p-type through hole and the first N-shaped through hole, prepare the first p-type electrode 251 and the first n-type electrode 241 respectively, thus complete the preparation of n-type electrode 24 and p-type electrode 25.
In step S5, after removal epitaxial substrate, also comprise: the light output surface of semiconductor luminous chip or semiconductor luminous chip light output surface and be enclosed with the surrounding side of semiconductor luminous chip of insulating barrier 22, one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body are set.In the manufacture method of the present embodiment, be provided with passivation layer 210.Passivation layer 210 wraps up whole semiconductor luminous chip, comprises light output surface and has the surrounding side of semiconductor luminous chip of insulating barrier 22.Passivation layer 210 is disposed with fluorescence coating 220 and packaging body 230.Fluorescence coating comprises phosphor powder layer, be mixed with in the layer of silica gel of fluorescent material, resin bed, glassy layer one or more.Packaging body 230, except protection fluorescence coating 220 is from except ectocine, also can be made different shapes and play the effect of getting light and optically focused.
Understandable, each technical characteristic of the various embodiments described above can combination in any to use and unrestricted.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (22)
1. a light emitting semiconductor device, comprises the substrate with first surface and second surface, and described first surface is provided with semiconductor luminous chip; It is characterized in that, except the light output surface of described semiconductor luminous chip, all exposed, that the there is conductivity surface of described semiconductor luminous chip and side wrap up by least one insulating barrier, described insulating barrier partly or entirely containing a reflection layer; Described reflection layer is positioned at described insulating barrier or is positioned at the exposed surface of described insulating barrier, and and insulated from each other between described semiconductor luminous chip;
Described semiconductor luminous chip comprises at least one semiconductor laminated; Describedly semiconductor laminatedly comprise folded N-shaped conductive layer, luminescent layer and the p-type electric-conducting layer established successively, describedly semiconductor laminatedly be arranged on the first surface of described substrate with its p-type electric-conducting layer towards described substrate, the surface of described N-shaped conductive layer described substrate is dorsad the light output surface of described semiconductor luminous chip;
The n-type electrode step that described p-type electric-conducting layer surface has at least one to expose partially n-type conductive layer, n-type electrode shrinkage pool and/or n-type electrode groove; Described p-type electric-conducting layer surface, semiconductor laminated side, n-type electrode ledge surface and side, n-type electrode shrinkage pool bottom surface and side, n-type electrode groove floor and side all wrap up by described insulating barrier.
2. light emitting semiconductor device according to claim 1, it is characterized in that, the light output surface of described semiconductor luminous chip or described semiconductor luminous chip, comprise described light output surface and be enclosed with the surrounding side of described semiconductor luminous chip of described insulating barrier, wrap up by one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body.
3. light emitting semiconductor device according to claim 1, is characterized in that, described surface of insulating layer is exposed at least one p-type electrode and at least one n-type electrode; Described p-type electrode runs through described insulating barrier and conducts electricity with described p-type electric-conducting layer and be connected, and insulate with described luminescent layer and N-shaped conductive layer; Described n-type electrode runs through described insulating barrier and is located in described n-type electrode step, n-type electrode shrinkage pool and/or n-type electrode groove, and conducts electricity with described N-shaped conductive layer and be connected, and insulate with described luminescent layer and p-type electric-conducting layer.
4. light emitting semiconductor device according to claim 3, is characterized in that, described substrate first surface is provided with at least one p-type weld pad and at least one N-shaped weld pad; Described p-type electrode and n-type electrode are conducted electricity with described p-type weld pad and N-shaped weld pad respectively and are connected, and described semiconductor luminous chip is fixed on the first surface of described substrate.
5. light emitting semiconductor device according to claim 4, it is characterized in that there is at least one p-type layer between described p-type electrode and p-type weld pad, described p-type layer is close to described surface of insulating layer, its area is greater than described p-type electrode, and conducts electricity with described p-type electrode and p-type weld pad and be connected; And/or
Between described n-type electrode and N-shaped weld pad, have at least one N-shaped layer, described N-shaped layer is close to described surface of insulating layer, and its area is greater than described n-type electrode, and conducts electricity with described n-type electrode and N-shaped weld pad and be connected.
6. light emitting semiconductor device according to claim 4, is characterized in that, described substrate is also provided with at least one p-type pad and at least one N-shaped pad;
It is one or more that the position that described p-type pad is arranged comprises in described substrate first surface, second surface, side; Described p-type pad to be conducted electricity with described p-type weld pad by least one p-type interconnecting metal and is connected, and the position of described p-type interconnecting metal process comprises described substrate first surface, second surface, side, it is one or more to run through in described substrate; Or described p-type pad is conduct electricity through described substrate and described p-type weld pad the p-type needle-like pad be connected;
It is one or more that the position that described N-shaped pad is arranged comprises in described substrate first surface, second surface, side; Described N-shaped pad is conducted electricity with described N-shaped weld pad be connected by least one N-shaped interconnecting metal, and the position of described N-shaped interconnecting metal process comprises described substrate first surface, second surface, side, it is one or more to run through in described substrate; Or described N-shaped pad is conduct electricity through described substrate and described N-shaped weld pad the N-shaped needle-like pad be connected.
7. light emitting semiconductor device according to claim 6, it is characterized in that, at least one n-type electrode interconnection layer is provided with in described insulating barrier, described n-type electrode comprises at least one first n-type electrode and at least one second n-type electrode, described first n-type electrode runs through the described insulating barrier being positioned at described n-type electrode upperside interconnection layer and conducts electricity with described n-type electrode interconnection layer and be connected, and described n-type electrode interconnection layer to be conducted electricity with described N-shaped conductive layer by least one described second n-type electrode running through the described insulating barrier be positioned at below described n-type electrode interconnection layer and is connected; Described second n-type electrode is located in described n-type electrode step, n-type electrode shrinkage pool and/or n-type electrode groove; Described n-type electrode interconnection layer and insulated from each other between described p-type electrode and reflection layer; And/or,
At least one p-type electrode interconnect layers is provided with in described insulating barrier, described p-type electrode comprises at least one first p-type electrode and at least one second p-type electrode, described first p-type electrode runs through the described insulating barrier be positioned at above described p-type electrode interconnect layers and conducts electricity with described p-type electrode interconnect layers and be connected, and described p-type electrode interconnect layers to be conducted electricity with described p-type electric-conducting layer by the described second p-type electrode that runs through the described insulating barrier be positioned at below described p-type electrode interconnect layers and is connected; Described p-type electrode interconnect layers and insulated from each other between described n-type electrode and reflection layer.
8. light emitting semiconductor device according to claim 6, is characterized in that, be provided with p-type current extending between described p-type electric-conducting layer surface and described insulating barrier, described p-type current extending is connected with described p-type electrodes conduct; Described p-type current extending comprise in p-type metal diffusion barrier layer, p-type electric-conducting extension layer, p-type reflector, P type contact layer one or more; And/or,
Be provided with N-shaped current extending between the bottom surface of the surface of described n-type electrode step, the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove and described insulating barrier, described N-shaped current extending conducts electricity with described n-type electrode and is connected; Described N-shaped current extending comprise in N-shaped metal diffusion barrier layer, N-shaped conductive extension layer, N-shaped reflector, n-contact layer one or more.
9. light emitting semiconductor device according to claim 1, is characterized in that, the light output surface of described semiconductor luminous chip is smooth finished surfaces or patterned surface; Described patterned surface comprise in taper rough surface, convex-concave surface, pyramid shape surface one or more;
Described semiconductor laminated side, n-type electrode step side, n-type electrode shrinkage pool side and/or n-type electrode groove side are vertical with described light output surface or the smooth flat of oblique, smooth surface, structuring plane or structuring curved surface; Described structuring comprise in concavo-convex, sawtooth one or more.
10. light emitting semiconductor device according to claim 6, it is characterized in that, described substrate is electrically-conductive backing plate, at described p-type weld pad, p-type interconnecting metal, p-type pad, N-shaped weld pad, N-shaped interconnecting metal, is provided with at least one substrate insulating layer between N-shaped pad and described substrate.
The manufacture method of 11. 1 kinds of light emitting semiconductor devices, is characterized in that, at least comprises the following steps:
S1, at extension substrate surface, by the order epitaxial semiconductor lamination successively of N-shaped conductive layer, luminescent layer, p-type electric-conducting layer; By shape and the size of semiconductor luminous chip, with at least one semiconductor luminous chip of semiconductor laminated preparation in described epitaxial substrate;
Except the light output surface of described semiconductor luminous chip, at all exposed, that there is conductivity surface and at least one insulating barrier of side wrap of described semiconductor luminous chip, and in part or all of described insulating barrier or exposed surface one reflection layer is set; Insulated from each other between described reflection layer and described semiconductor luminous chip;
S2, the first surface preparation conducting channel corresponding with the described semiconductor luminous chip in described epitaxial substrate at substrate, or, after the first surface of the described substrate of tool conductive characteristic prepares described substrate insulating layer, then prepare the conducting channel corresponding with the described semiconductor luminous chip in described epitaxial substrate on described substrate insulating layer surface; Described conducting channel comprises at least one N-shaped weld pad, at least one N-shaped interconnecting metal, at least one N-shaped pad, at least one p-type weld pad, at least one p-type interconnecting metal and at least one p-type pad;
S3, connect described semiconductor luminous chip and substrate: described semiconductor luminous chip is with its semiconductor laminated first surface being arranged on described substrate towards described substrate; The p-type electrode of described semiconductor luminous chip and n-type electrode are close to mutually with p-type weld pad and N-shaped weld pad respectively, and strong bonded conducting;
S4, the epitaxial substrate removed on described semiconductor luminous chip;
S5, along described semiconductor luminous chip periphery, to cut and/or the described substrate that bursts apart obtains discrete semiconductor luminescent device;
Wherein, described step S1 comprises:
S1.1, at extension substrate surface, by N-shaped conductive layer, luminescent layer, p-type electric-conducting layer order successively epitaxial growth formed semiconductor laminated;
S1.2, described semiconductor laminated on, prepare the corresponding n-type electrode step of at least one semiconductor luminous chip, n-type electrode shrinkage pool and/or n-type electrode groove; The surface of described n-type electrode step is positioned at described N-shaped conductive layer or is positioned at described N-shaped conductive layer surface, and described n-type electrode shrinkage pool and/or n-type electrode groove run through in described p-type electric-conducting layer and luminescent layer to described N-shaped conductive layer or described N-shaped conductive layer surface; Before or after preparation described n-type electrode step, n-type electrode shrinkage pool and/or n-type electrode groove, prepare cut-in groove along described semiconductor luminous chip periphery; The bottom surface of described cut-in groove is positioned at described epitaxial substrate surface or described epitaxial substrate;
S1.3, described semiconductor laminated outside, comprise the exposed epitaxial substrate surface in described semiconductor laminated surface and side, described cut-in groove place or epitaxial substrate is surperficial and side part or all of, the first insulating barrier be set;
S1.4, on described first insulating barrier for the preparation of the N-shaped through hole arranging n-type electrode, through described first insulating barrier of described N-shaped through hole to the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or described n-type electrode groove;
S1.5, on described first insulating barrier for the preparation of the p-type through hole arranging p-type electrode, through described first insulating barrier of described p-type through hole is to described p-type electric-conducting layer surface; Described first insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier of side;
S1.6, in described N-shaped through hole and described p-type through hole, prepare described n-type electrode and described p-type electrode respectively, described n-type electrode is conducted electricity with described N-shaped conductive layer and is connected, and described p-type electrode conducts electricity with described p-type electric-conducting layer and is connected.
The manufacture method of 12. light emitting semiconductor devices according to claim 11, it is characterized in that, after removing the epitaxial substrate on described semiconductor luminous chip, also comprise: the light output surface of described semiconductor luminous chip or described semiconductor luminous chip light output surface and be enclosed with the surrounding side of described semiconductor luminous chip of described insulating barrier, one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body are set;
Before described light output surface arranges one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body, structuring is carried out to described light output surface, make it to form taper rough surface or convex-concave surface.
The manufacture method of 13. light emitting semiconductor devices according to claim 11, is characterized in that, described step S1.3 comprises:
S1.3.1, described semiconductor laminated outside, comprise the exposed epitaxial substrate surface in described semiconductor laminated surface and side, described cut-in groove place or epitaxial substrate is surperficial and side part or all of, the ground floor of described first insulating barrier be set;
S1.3.2, at the described reflection layer of described ground floor surface preparation, described reflection layer is along the exposed epitaxial substrate surface in described semiconductor laminated surface and side and described cut-in groove place or epitaxial substrate is surperficial and side distribution, and with described semiconductor laminated insulation;
S1.3.3, arrange the second layer of described first insulating barrier of the described reflection layer of parcel on the first layer, the described second layer and described ground floor form described first insulating barrier jointly.
The manufacture method of 14. light emitting semiconductor devices according to claim 11, is characterized in that, described n-type electrode comprises at least one first n-type electrode and at least one second n-type electrode;
Described step S1.4 comprises:
S1.4.1, on described first insulating barrier for the preparation of the second N-shaped through hole arranging the second n-type electrode, through described first insulating barrier of described second N-shaped through hole to the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or described n-type electrode groove;
S1.4.2, in described second N-shaped through hole, prepare described second n-type electrode, conduct electricity in the preparation of the surface of described first insulating barrier and described second n-type electrode the n-type electrode interconnection layer be connected; Described second n-type electrode is conducted electricity with described N-shaped conductive layer and is connected;
S1.4.3, the second insulating barrier is set on described first insulating barrier, for the preparation of arranging the first n-type electrode, through the first N-shaped through hole to described n-type electrode interconnection layer on described second insulating barrier;
In described step S1.5, for the preparation of arranging p-type electrode, through described second insulating barrier and the first insulating barrier p-type through hole to described p-type electric-conducting layer on described second insulating barrier; Described first, second insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier of side;
In described step S1.6, described first n-type electrode and described p-type electrode is prepared respectively in described first N-shaped through hole and described p-type through hole, described first n-type electrode is conducted electricity with described n-type electrode interconnection layer and is connected, and described p-type electrode conducts electricity with described p-type electric-conducting layer and is connected.
The manufacture method of 15. light emitting semiconductor devices according to claim 11, is characterized in that, described p-type electrode comprises at least one first p-type electrode and at least one second p-type electrode;
Described step S1.4 comprises:
S1.4.1, on described first insulating barrier for the preparation of the second p-type through hole arranging the second p-type electrode, through described first insulating barrier of described second p-type through hole is to described p-type electric-conducting layer surface;
S1.4.2, in described second p-type through hole, prepare described second p-type electrode, prepare the p-type electrode interconnect layers be connected with described second p-type electrodes conduct on the surface of described first insulating barrier; Described second p-type electrode conducts electricity with described p-type electric-conducting layer and is connected;
S1.4.3, the second insulating barrier is set on described first insulating barrier, for the preparation of arranging the first p-type electrode, through the first p-type through hole to described p-type electrode interconnect layers on described second insulating barrier;
In described step S1.5, for the preparation of the N-shaped through hole arranging n-type electrode on described second insulating barrier, through described second insulating barrier of described N-shaped through hole and the first insulating barrier to the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or described n-type electrode groove; Described first, second insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier of side;
In described step S1.6, described n-type electrode and described first p-type electrode is prepared respectively in described N-shaped through hole and described first p-type through hole, described first p-type electrode conducts electricity with described p-type electrode interconnect layers and is connected, and described n-type electrode is conducted electricity with described N-shaped conductive layer and is connected.
The manufacture method of 16. light emitting semiconductor devices according to claim 11, is characterized in that, described step S1.2 also comprises: at described p-type electric-conducting layer surface coverage p-type current extending; And/or on the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove covers N-shaped current extending;
In described step S1.6, the bottom surface of described p-type electrode is all positioned on described p-type current extending or is all positioned on described p-type electric-conducting layer or is partly positioned at another part on described p-type current extending and is positioned on described p-type electric-conducting layer;
The bottom surface of described n-type electrode is all positioned on described N-shaped current extending or is all positioned on the bottom surface of the surface of described n-type electrode step and/or the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove or is partly positioned at another part on described N-shaped current extending and is positioned on the bottom surface of the surface of described n-type electrode step and/or the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove.
The manufacture method of 17. 1 kinds of light emitting semiconductor devices, is characterized in that, at least comprises the following steps:
S1, at extension substrate surface, by the order of N-shaped conductive layer, luminescent layer, p-type electric-conducting layer successively after epitaxial semiconductor lamination, by shape and the size of semiconductor luminous chip, with at least one semiconductor luminous chip of semiconductor laminated preparation in described epitaxial substrate;
Except the light output surface of described semiconductor luminous chip, at all exposed, that there is conductivity surface and at least one insulating barrier of side wrap of described semiconductor luminous chip, and in part or all of described insulating barrier or exposed surface one reflection layer is set; Insulated from each other between described reflection layer and described semiconductor luminous chip;
After S2, thinning described epitaxial substrate, along the periphery of described semiconductor luminous chip, cut and/or described epitaxial substrate of bursting apart, obtain the semiconductor luminous chip of discrete band substrate;
S3, prepare the corresponding conducting channel of at least one and described semiconductor luminous chip at the first surface of substrate, or, after the first surface of the described substrate of tool conductive characteristic prepares described substrate insulating layer, then in the conducting channel that described substrate insulating layer surface preparation is at least one and described semiconductor luminous chip is corresponding; Described conducting channel comprises at least one N-shaped weld pad, at least one N-shaped interconnecting metal, at least one N-shaped pad, at least one p-type weld pad, at least one p-type interconnecting metal and at least one p-type pad;
S4, connect described semiconductor luminous chip and substrate: the semiconductor luminous chip of described discrete band substrate is with its semiconductor laminated first surface being arranged on described substrate towards described substrate; The p-type electrode of described semiconductor luminous chip and n-type electrode are close to mutually with p-type weld pad and N-shaped weld pad respectively, and strong bonded conducting;
S5, the epitaxial substrate removed on described semiconductor luminous chip;
S6, along described semiconductor luminous chip periphery, to cut and/or the described substrate that bursts apart obtains discrete semiconductor luminescent device;
Wherein, described step S1 comprises:
S1.1, at extension substrate surface, by N-shaped conductive layer, luminescent layer, p-type electric-conducting layer order successively epitaxial growth formed semiconductor laminated;
S1.2, described semiconductor laminated on, prepare the corresponding n-type electrode step of at least one semiconductor luminous chip, n-type electrode shrinkage pool and/or n-type electrode groove; The surface of described n-type electrode step is positioned at described N-shaped conductive layer or is positioned at described N-shaped conductive layer surface, and described n-type electrode shrinkage pool and/or n-type electrode groove run through in described p-type electric-conducting layer and luminescent layer to described N-shaped conductive layer or described N-shaped conductive layer surface; Before or after preparation described n-type electrode step, n-type electrode shrinkage pool and/or n-type electrode groove, prepare cut-in groove along described semiconductor luminous chip periphery; The bottom surface of described cut-in groove is positioned at described epitaxial substrate surface or described epitaxial substrate;
S1.3, described semiconductor laminated outside, comprise the exposed epitaxial substrate surface in described semiconductor laminated surface and side, described cut-in groove place or epitaxial substrate is surperficial and side part or all of, the first insulating barrier be set;
S1.4, on described first insulating barrier for the preparation of the N-shaped through hole arranging n-type electrode, through described first insulating barrier of described N-shaped through hole to the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or described n-type electrode groove;
S1.5, on described first insulating barrier for the preparation of the p-type through hole arranging p-type electrode, through described first insulating barrier of described p-type through hole is to described p-type electric-conducting layer surface; Described first insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier of side;
S1.6, in described N-shaped through hole and described p-type through hole, prepare described n-type electrode and described p-type electrode respectively, described n-type electrode is conducted electricity with described N-shaped conductive layer and is connected, and described p-type electrode conducts electricity with described p-type electric-conducting layer and is connected.
The manufacture method of 18. light emitting semiconductor devices according to claim 17, it is characterized in that, after removing the epitaxial substrate on described semiconductor luminous chip, also comprise: the light output surface of described semiconductor luminous chip or described semiconductor luminous chip light output surface and be enclosed with the surrounding side of described semiconductor luminous chip of described insulating barrier, one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body are set;
Before described light output surface arranges one or more at least one passivation layer, at least one fluorescence coating, at least one encapsulated layer, at least one packaging body, structuring is carried out to described light output surface, make it to form taper rough surface or convex-concave surface.
The manufacture method of 19. light emitting semiconductor devices according to claim 17, is characterized in that, described step S1.3 comprises:
S1.3.1, described semiconductor laminated outside, comprise the exposed epitaxial substrate surface in described semiconductor laminated surface and side, described cut-in groove place or epitaxial substrate is surperficial and side part or all of, the ground floor of described first insulating barrier be set;
S1.3.2, at the described reflection layer of described ground floor surface preparation, described reflection layer is along the exposed epitaxial substrate surface in described semiconductor laminated surface and side and described cut-in groove place or epitaxial substrate is surperficial and side distribution, and with described semiconductor laminated insulation;
S1.3.3, arrange the second layer of described first insulating barrier of the described reflection layer of parcel on the first layer, the described second layer and described ground floor form described first insulating barrier jointly.
The manufacture method of 20. light emitting semiconductor devices according to claim 17, is characterized in that, described n-type electrode comprises at least one first n-type electrode and at least one second n-type electrode;
Described step S1.4 comprises:
S1.4.1, on described first insulating barrier for the preparation of the second N-shaped through hole arranging the second n-type electrode, through described first insulating barrier of described second N-shaped through hole to the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or described n-type electrode groove;
S1.4.2, in described second N-shaped through hole, prepare described second n-type electrode, conduct electricity in the preparation of the surface of described first insulating barrier and described second n-type electrode the n-type electrode interconnection layer be connected; Described second n-type electrode is conducted electricity with described N-shaped conductive layer and is connected;
S1.4.3, the second insulating barrier is set on described first insulating barrier, for the preparation of arranging the first n-type electrode, through the first N-shaped through hole to described n-type electrode interconnection layer on described second insulating barrier;
In described step S1.5, for the preparation of arranging p-type electrode, through described second insulating barrier and the first insulating barrier p-type through hole to described p-type electric-conducting layer on described second insulating barrier; Described first, second insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier of side;
In described step S1.6, described first n-type electrode and described p-type electrode is prepared respectively in described first N-shaped through hole and described p-type through hole, described first n-type electrode is conducted electricity with described n-type electrode interconnection layer and is connected, and described p-type electrode conducts electricity with described p-type electric-conducting layer and is connected.
The manufacture method of 21. light emitting semiconductor devices according to claim 17, is characterized in that, described p-type electrode comprises at least one first p-type electrode and at least one second p-type electrode;
Described step S1.4 comprises:
S1.4.1, on described first insulating barrier for the preparation of the second p-type through hole arranging the second p-type electrode, through described first insulating barrier of described second p-type through hole is to described p-type electric-conducting layer surface;
S1.4.2, in described second p-type through hole, prepare described second p-type electrode, prepare the p-type electrode interconnect layers be connected with described second p-type electrodes conduct on the surface of described first insulating barrier; Described second p-type electrode conducts electricity with described p-type electric-conducting layer and is connected;
S1.4.3, the second insulating barrier is set on described first insulating barrier, for the preparation of arranging the first p-type electrode, through the first p-type through hole to described p-type electrode interconnect layers on described second insulating barrier;
In described step S1.5, for the preparation of the N-shaped through hole arranging n-type electrode on described second insulating barrier, through described second insulating barrier of described N-shaped through hole and the first insulating barrier to the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or described n-type electrode groove; Described first, second insulating barrier forms the surface that is all exposed, that have conductivity of the described semiconductor luminous chip of parcel and the insulating barrier of side;
In described step S1.6, described n-type electrode and described first p-type electrode is prepared respectively in described N-shaped through hole and described first p-type through hole, described first p-type electrode conducts electricity with described p-type electrode interconnect layers and is connected, and described n-type electrode is conducted electricity with described N-shaped conductive layer and is connected.
The manufacture method of 22. light emitting semiconductor devices according to claim 17, is characterized in that, described step S1.2 also comprises: at described p-type electric-conducting layer surface coverage p-type current extending; And/or on the surface of described n-type electrode step, the bottom surface of the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove covers N-shaped current extending;
In described step S1.6, the bottom surface of described p-type electrode is all positioned on described p-type current extending or is all positioned on described p-type electric-conducting layer or is partly positioned at another part on described p-type current extending and is positioned on described p-type electric-conducting layer;
The bottom surface of described n-type electrode is all positioned on described N-shaped current extending or is all positioned on the bottom surface of the surface of described n-type electrode step and/or the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove or is partly positioned at another part on described N-shaped current extending and is positioned on the bottom surface of the surface of described n-type electrode step and/or the bottom surface of n-type electrode shrinkage pool and/or n-type electrode groove.
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| KR102357289B1 (en) * | 2014-07-01 | 2022-02-03 | 서울바이오시스 주식회사 | Light emitting device |
| CN107039569B (en) * | 2015-10-16 | 2019-04-23 | 首尔伟傲世有限公司 | Light-emitting diode chip for backlight unit |
| KR102481646B1 (en) * | 2015-11-12 | 2022-12-29 | 삼성전자주식회사 | Semiconductor light emitting device package |
| CN108011005A (en) * | 2017-11-10 | 2018-05-08 | 深圳大道半导体有限公司 | Light emitting semiconductor device and its manufacture method |
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| CN202159699U (en) * | 2011-05-27 | 2012-03-07 | 东莞市福地电子材料有限公司 | Light emitting diode with flip chip |
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