CN103618041A - ESD (electronic static discharge) protected LED (light-emitting diode) packaging structure as well as packaging method thereof - Google Patents
ESD (electronic static discharge) protected LED (light-emitting diode) packaging structure as well as packaging method thereof Download PDFInfo
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- CN103618041A CN103618041A CN201310669399.8A CN201310669399A CN103618041A CN 103618041 A CN103618041 A CN 103618041A CN 201310669399 A CN201310669399 A CN 201310669399A CN 103618041 A CN103618041 A CN 103618041A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Abstract
The invention relates to an ESD (electronic static discharge) protected LED (light-emitting diode) packaging structure as well as a packaging method thereof, and belong to the technical field of semiconductor packaging. The ESD protected LED packaging structure comprises an LED chip (200) and an ESD protective chip (300), wherein the LED chip (200) is reversely installed in a cavity (111) of a silicon base body (110); the ESD protective chip (300) is embedded into a blind hole (113) in the other surface of the silicon base body (110); the LED chip (200) and the ESD protective chip (300) are electrically communicated and are electrically communicated with the external world by multi-layer metal layers in silicon through holes (112) below the cavity (111) and in the blind hole (113) as well as metal leads (900) connected with the multi-layer metal layers. The LED chip and the ESD electrostatic protective chip are integrated into a package body by the packaging structure realized by the invention; the ESD anti-electrostatic capability of the LED packaging structure is intensified; the packaging thermal resistance is reduced greatly by the addition of a heat radiation channel; the using performance of the LED chip is improved; the service life of the LED chip is prolonged.
Description
Technical field
The LED encapsulating structure and the method for packing thereof that the present invention relates to a kind of esd protection, belong to semiconductor packaging field.
Background technology
General, light-emitting diode (Light-Emitting Diode, is called for short LED, lower with) be packaged with multiple packing forms.Early stage, adopting lead frame is that substrate encapsulates, and LED chip is mounted to lead frame by heat-conducting cream (or conducting resinl), thereby the mode by Bonding realizes current load, makes it luminous; Along with technological progress, some new, high performance baseplate material appearance have been played leading action, as ceramic substrate, AlN substrate etc. in the application of great power LED.But as the product of commercialization, also there is following defect in existing LED encapsulation: 1. thermal resistance is high.Because LED chip is luminous, be to excite by electron recombination process, thereby produce a large amount of heat when producing light.As everyone knows, the heat of generation affects the efficiency that electricity is converted into light conversely, thereby reduces the luminescent properties of LED itself.2. LED chip, in paster technique, very easily produce electrostatic breakdown, and traditional mode that adds ESD electrostatic protection device on substrate can only help LED lamp pearl after mounting, to reduce the risk of electrostatic breakdown.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of LED encapsulating structure and method for packing thereof that reduces thermal resistance and integrate the esd protection of ESD electrostatic protection chip is provided.
The object of the present invention is achieved like this:
The LED method for packing of a kind of esd protection of the present invention, comprises the steps:
Silica-based disk is provided, utilizes the mode of photoetching and etching, at the upper surface of silica-based disk, form the recessed die cavity that can hold LED chip;
Utilize chip attachment mode by LED chip upside-down mounting to die cavity;
Glass wafer is provided, glass wafer is bonded to the top of silica-based disk;
Corresponding LED chip electrode place below the die cavity of silica-based disk, utilizes photoetching and etching technics to form silicon through hole, and offers in a side of silicon through hole the blind hole that can hold esd protection chip;
At the inwall of silicon through hole and blind hole and the back side of silica-based disk, insulating barrier I is set, in silicon through hole, corresponding LED chip electrode place offers Heraeus opening, utilize successively again sputter, photoetching, electro-plating method to form to adhere to separately independently metal level I of each silicon through hole and blind hole, there is each other gap in metal level I, simultaneously in a side of metal level I, forms and connect blind hole place metal level I and the metal lead wire of a silicon through hole metal level I wherein;
Esd protection chip is mounted to the metal level I in blind hole by conducting resinl, and esd protection chip electrode is towards the outside of blind hole, then is coated with layer of cloth II in esd protection chip periphery, and offers insulating barrier II opening at esd protection chip electrode place;
On the surface of metal level I with utilize successively sputter, photoetching, electro-plating method to form the independently metal level II of corresponding each silicon through hole and blind hole in the surface of insulating barrier II and insulating barrier II opening, there is gap in metal level II each other;
At the surface-coated protective layer of metal level II, and offer the protective layer opening of distinguishing corresponding each silicon through hole and blind hole;
The surface of the metal level II below each silicon through hole, forms metal level III by printing solder or the mode of planting soldered ball;
Cut above-mentioned encapsulation disk, form the independently LED encapsulating structure of esd protection, enter subsequent handling.
Further, utilize chip attachment mode by LED chip upside-down mounting to also comprising step before in die cavity:
Mode by sputter or electron beam evaporation plating, in conjunction with mask technology, wet etching mode, forms reflector layer in inwall and the outer of die cavity, and forms and run through the reflector layer opening figure that reflector layer can hold LED chip electrode.
Further, described LED chip is connected with the bottom of die cavity by Heraeus.
Further, on the surface towards die cavity of glass wafer, by the mode spraying or print, form phosphor powder layer.
Further, before being bonded to above the die cavity of silica-based disk, glass wafer also comprises step:
In being provided with the die cavity of LED chip, fill filler, and solidify.
Further, below die cavity, offer and also comprise step before silicon through hole and blind hole:
The silica-based part at the back side of the complete silica-based disk of bonding is thinned to the thickness of setting.
Further, by printing solder or the mode of planting soldered ball, form and also comprise step after metal level III:
By mechanochemistry, grind, make the flush of the metal level II of metal level III and blind hole below.
The LED encapsulating structure of the esd protection that the LED method for packing of a kind of esd protection of the present invention forms, comprise silica-based body and with the LED chip of LED chip electrode, the one side of described silica-based body is provided with die cavity, another side is provided with several silicon through hole and blind holes, described silicon through hole is positioned at the below of die cavity, blind hole is positioned at a side of silicon through hole, described LED chip is arranged in die cavity, its LED chip electrode is towards the inner side of die cavity, the inwall of described die cavity arranges reflector layer, described die cavity top arranges glassy layer, the surface towards die cavity of described glassy layer arranges phosphor powder layer, described glassy layer is connected by adhesive and die cavity, in described die cavity, filler is set,
The inwall of described silicon through hole and blind hole all arranges insulating barrier I, described insulating barrier I outwards extends into the surface of the silica-based body at silicon through hole and/or blind hole place, in described insulating barrier I in each hole, independently multiple layer metal layer is set respectively, described multiple layer metal layer comprises metal level I, metal level II and/or metal level III, and described LED chip is realized electrical communication by the described multiple layer metal layer of filling in described LED chip electrode and silicon through hole;
Also comprise the esd protection chip with esd protection chip electrode, described esd protection chip is arranged between the described multiple layer metal layer in blind hole, and realize electrical communication, between described multiple layer metal layer, insulating barrier II is set, described esd protection chip is realized serial or parallel connection by metal lead wire and described LED chip, and described metal lead wire is arranged at a side of described multiple layer metal layer;
In the peripheral of described multiple layer metal layer and the gap each other at described multiple layer metal layer, protective layer is set, and offers protective layer opening, the outermost layer of multiple layer metal layer described in described protective layer opening exposed portions serve.
Alternatively, between described LED chip and metal level I, Heraeus is set, and offer Heraeus opening in the place, top of silicon through hole, described metal level I is arranged in the described insulating barrier I in silicon through hole, top at silicon through hole, described metal level I is connected with LED chip electrode respectively by Heraeus opening, and the surface of described metal level I arranges metal level II, on the surface of described metal level II, metal level III is set.
Alternatively; described metal level I is arranged in the described insulating barrier I in blind hole; described esd protection chip is fixed in the metal level I in blind hole by conducting resinl; described esd protection chip electrode is towards the outside of blind hole; and described metal level II is set thereon, between described metal level I and metal level II, insulating barrier II is set.
Structure of the present invention utilizes semi-conductive Wafer-Level Packaging Technology, in encapsulation, traditional LED chip and ESD electrostatic protection chip are embedded to integration, promoted the antistatic breakdown capability of LED chip in paster process and in follow-up use, and the metal level that large area ratio is used contributes to reduce the thermal resistance of encapsulating structure; Wafer level packaging from chip manufacturing, be encapsulated into the whole process that product mails to user, greatly reduced intermediate link, shortened the cycle, this will cause the reduction of cost.
Beneficial effect of the present invention is:
1, utilize Wafer-Level Packaging Technology, LED chip and ESD electrostatic protection integrated chip are incorporated in packaging body, reduced the electrostatic breakdown risk of LED chip in encapsulation process, guaranteed the antistatic impact capacity of LED lamp pearl (being LED encapsulating structure) in the uses such as attachment process, simultaneously, reduce to take the space of substrate, can significantly expand its application;
2, the copper interconnection metal layer that thermal dissipating path is used by large area ratio is main, by chip electrode and copper interconnection metal layer Direct Bonding, without additional thermal resistance, greatly reduce packaging thermal resistance, far below traditional LED lamp pearl packaging thermal resistance, contribute to promote serviceability and the life-span of LED chip;
3, the chip design of wafer level packaging and package design can be unified to consider, carry out simultaneously, contribute to improve design efficiency, reduce design cost;
4, wafer level packaging from chip manufacturing, be encapsulated into the whole process that product mails to user, greatly reduced intermediate link, shortened the cycle, contribute to the reduction of cost.
Accompanying drawing explanation
Fig. 1 is the process chart of the LED method for packing of a kind of esd protection of the present invention;
Fig. 2 is the schematic diagram of the LED encapsulating structure of a kind of esd protection of the present invention;
Fig. 3 be the LED chip of Fig. 2 and esd protection chip relative position relation and and each metal level between the schematic diagram of relative position relation;
Fig. 4 is the schematic diagram of the amplification of local I in Fig. 2;
Fig. 5 is the schematic diagram of the amplification of local I I in Fig. 2;
Fig. 6 to Figure 18 is the process flow diagram of the method for packing of embodiment in Fig. 2;
In figure: silica-based disk 100,101,102,103
Silica-based body 110
Die cavity 111
Silicon through hole 112
Reflector layer opening figure 121
Adhesive 141
Heraeus 151,151 '
Heraeus opening 152
Conducting resinl 161
LED chip electrode 210
Esd protection chip electrode 310
Glass wafer 400
Insulating barrier I 610,610 '
Insulating barrier II 620
Insulating barrier II opening 621
Metal level I 711,712,713
Metal level II 721,722,723
Metal level III 731,732
Protective layer opening I 801
Protective layer opening II 802
Protective layer opening III 803
Embodiment
LED method for packing referring to a kind of esd protection of Fig. 1 the present invention, comprises the steps:
Execution step S101: silica-based disk is provided, utilizes the mode of photoetching and etching, form the recessed die cavity that can hold LED chip at the upper surface of silica-based disk;
Execution step S102: utilize chip attachment mode by LED chip upside-down mounting to die cavity;
Execution step S103: glass wafer is provided, glass wafer is bonded to the top of silica-based disk;
Execution step S104: corresponding LED chip electrode place below the die cavity of silica-based disk, utilizes photoetching and etching technics formation silicon through hole, and offers in a side of silicon through hole the blind hole that can hold esd protection chip;
Execution step S105: insulating barrier I is set at the inwall of silicon through hole and blind hole and the back side of silica-based disk, in silicon through hole, corresponding LED chip electrode place offers Heraeus opening, utilize successively again sputter, photoetching, electro-plating method to form to adhere to separately independently metal level I of each silicon through hole and blind hole, there is each other gap in metal level I, simultaneously in a side of metal level I, forms and connect blind hole place metal level I and the metal lead wire of a silicon through hole metal level I wherein;
Execution step S106: esd protection chip is mounted to the metal level I in blind hole by conducting resinl, esd protection chip electrode is towards the outside of blind hole, in esd protection chip periphery, be coated with layer of cloth II again, and offer insulating barrier II opening at esd protection chip electrode place;
Execution step S107: on the surface of metal level I with utilize successively sputter, photoetching, electro-plating method to form the independently metal level II of corresponding each silicon through hole and blind hole in the surface of insulating barrier II and insulating barrier II opening, metal level II exists gap each other;
Execution step S108: at the surface-coated protective layer of metal level II, and offer the protective layer opening of distinguishing corresponding each silicon through hole and blind hole;
Execution step S109: the surface of the metal level II below each silicon through hole, forms metal level III by printing solder or the mode of planting soldered ball;
Execution step S110: cut above-mentioned encapsulation disk, form the independently LED encapsulating structure of esd protection, enter subsequent handling.
The embodiment of the LED encapsulating structure of the esd protection that the LED method for packing of a kind of esd protection of the present invention can form, as shown in Figures 2 to 5.LED chip 200 and esd protection chip 300 are integrated and are packaged in silica-based body 110 in the mode embedding, and realize each other and with the electrical connection of extraneous substrate.LED chip 200 and esd protection chip 300 all can one or more, multi-functional integrated to realize.
The one side of the silica-based body 110 of the LED encapsulating structure of a kind of esd protection of the present invention is provided with the recessed die cavity that can hold LED chip 200 111, another side and is provided with several silicon through holes 112 and blind hole 113, and silicon through hole 112 is positioned at the below of die cavity 111, the side that blind hole 113 is positioned at silicon through hole 112.Usually, the number of silicon through hole 112 is no less than the number of LED chip electrode 210, and blind hole 113 can one or more.The shape of cross section of silicon through hole 112 is circle, rectangle or polygon, adopts according to actual needs suitable shape.The shape of cross section of blind hole 113 also can be circle, rectangle or polygon, and its degree of depth is as the criterion can hold esd protection chip electrode 310.
LED chip 200 is arranged in die cavity 111, its LED chip electrode 210 is towards the inner side of die cavity 111, its reverse installation process by semiconductor technology is upside down in the bottom of die cavity 111, and be fixed with Heraeus 151, and offer Heraeus opening 152 at the interior corresponding LED chip electrode of silicon through hole 112 210 places.Die cavity 111 inner wall smooths, have certain reflection and the effect of refracted ray, in order to promote its effect to light, the reflector layer 120 of the materials such as silver, aluminium are generally set at die cavity 111 inwalls.Reflector layer 120 leaves reflector layer opening figure 121 in the bottom of die cavity 111, to hold LED chip electrode 210, and LED chip electrode 210 is not contacted with reflector layer 120.Die cavity 111 tops arrange the glassy layer 410 that light transmission is good, the setting of glassy layer 410 also contributes to improve the characteristic of LED chip encapsulating structure aspect weatherability, environment out of doors particularly, its ambient temperature, humidity etc. all will directly affect the life-span of LED lamp.Glassy layer 410 is connected by adhesive 141 and die cavity 111, and adhesive 141 can be general adhesive glue, can be also silica gel.Usually, in die cavity 111, also can fill filler 131, to improve the reliability of LED chip 200 in die cavity 111.The surface towards die cavity 111 of glassy layer 410 also can coating phosphor powder layer 510, to realize the outgoing of white light.Phosphor powder layer 510 uniformities that form by the mode of wafer level packaging, can promote the optical grade test yield of LED encapsulating structure effectively.Certainly, phosphor substance also can be mixed in the filler 131 in die cavity 111.
The silicon through hole 112 of another side and the inwall of blind hole 113 at silica-based body 110 all arrange insulating barrier I 610, and insulating barrier I 610 can outwards extend into the surface of the silica-based body 110 at silicon through hole 112 and/or blind hole 113 places.Independently multiple layer metal layer is set respectively in the insulating barrier I 610 in each silicon through hole 112, and multiple layer metal layer can be by metal level I 711,712,713, and metal level II 721,722,723 and metal level III 731,732 form.Wherein, metal level I 711,712 is arranged at respectively in the insulating barrier I 610 in silicon through hole 112, and in silicon through hole 112, metal level I 711,712 is connected with LED chip electrode 210 respectively by Heraeus opening 152.Metal level I 711,712 is the thin copper layer that connects up again, and its lower surface arranges respectively metal level II 721,722; Metal level II 721,722 is also the thin copper layer that connects up again, along metal level I 711,712, is attached in silicon through hole 112; The metal level III 731,732 of thick tin layer is set respectively in metal level II 721,722, makes metal level III 731,732 fill and lead up silicon through hole 112.Described LED chip 200 is realized electrical communication by described LED chip electrode 210 and the described multiple layer metal layer of silicon through hole 112 interior fillings.
In insulating barrier I 610 in blind hole 113, metal level I 713 is set; esd protection chip 300 with esd protection chip electrode 310 is arranged in blind hole 113; esd protection chip electrode 310 is towards the outside of blind hole 113; the opposite side of the esd protection chip electrode 310 of esd protection chip 300 is fixed in metal level I 713 by conducting resinl 161; the thin copper layer metal level II 723 that connects up again contacting with extraneous substrate is set on esd protection chip electrode 310, and between metal level I 713 and metal level II 723, insulating barrier II 620 is set.The multiple layer metal layer consisting of metal level I 713 and metal level II 723 is independent of one another with the multiple layer metal layer that is distributed in each silicon through hole 112 place.Wherein the metal level I 713 of esd protection chip 300, by being arranged at the metal level I 711 of one of the metal lead wire 900 of one side and LED chip electrode 210 of LED chip 200 or being connected of metal level I 712, has realized the serial or parallel connection relation of esd protection chip 300 with LED chip 200.Usually, N utmost point electrode and the P utmost point electrode of corresponding LED chip electrode 210, the metal level III 732 that the metal level III 731 of answering with the N utmost point electrode pair of LED chip electrode 210 is answered for N utmost point conductive metal layer, with the P utmost point electrode pair of LED chip electrode 210 is P utmost point conductive metal layer; The metal level II 723 being connected with the esd protection chip electrode 310 of esd protection chip 300 for P utmost point conductive metal layer, the metal level I 713 that is connected with the opposite side of esd protection chip electrode 310 be N utmost point conductive metal layer; If the metal level I of esd protection chip 300 713 is connected with the metal level I 711 of the N utmost point electrode of LED chip 200 by metal lead wire 900, realized the in parallel relation of esd protection chip 300 with LED chip 200; If the metal level I of esd protection chip 300 713 is connected with the metal level I 712 of the P utmost point electrode of LED chip 200 by metal lead wire 900, realized the series relationship of esd protection chip 300 with LED chip 200.Esd protection chip 300 is determined by actual needs with the determining of serial or parallel connection relation of LED chip 200.
The setting of multiple layer metal layer of the present invention, has increased thermal dissipating path, greatly reduces packaging thermal resistance, has promoted serviceability and the life-span of LED chip.In the peripheral of multiple layer metal layer and the gap each other at multiple layer metal layer, protective layer 800 is set; and offer protective layer opening I 801, protective layer opening II 802, protective layer opening III 803; the P utmost point conductive metal layer that exposes respectively the P utmost point conductive metal layer of LED chip 200 and N utmost point conductive metal layer, esd protection chip 300, for the surface mount process of LED encapsulating structure.
The implementation procedure of the embodiment of the LED encapsulating structure of esd protection of the present invention is:
As shown in Figure 6 and Figure 7, silica-based disk 100 is provided, utilize the mode of photoetching and etching, upper surface at silica-based disk 101 forms recessed die cavity 111, the sidewall of die cavity 111 is smooth and have certain angle of inclination, can play certain reflection function, the degree of depth of die cavity 111 is as the criterion can hold LED chip 200.
As shown in Figure 8, by the mode of sputter or electron beam evaporation plating, in conjunction with mask technology, in inwall and the outer of die cavity 111, form reflector layer 120, and forming the reflector layer opening figure 121 that runs through reflector layer 120, the material of reflector layer 120 can be the metal that silver, aluminium etc. have reverberation effect.
As shown in Figure 9 and Figure 10, utilize chip attachment mode by LED chip 200 upside-down mountings to die cavity 111, LED chip electrode 210 is aimed at reflector layer opening figure 121, adopt Heraeus 151 ' to strengthen the firmness of LED chip 200 and die cavity 111 bottoms, and at the interior filling filler 131 of die cavity 111, and solidify.
As shown in figure 11, glass wafer 400 is provided, the surface towards die cavity 111 at glass wafer 400 forms phosphor powder layer 510 by the mode spraying or print, after solidifying with silica-based disk 102 by the adhesives such as silica gel 141 bondings, phosphor powder layer 510 also can be with graphic style spraying or the printing of setting, and fluorescent material also can be filled in die cavity 111 after evenly mixing with filler 131.
As shown in figure 12; the silica-based part at the back side of the silica-based disk 102 after bonding is thinned to the thickness of setting; corresponding LED chip electrode 210 places below die cavity 111 again; utilize photoetching and etching technics to form and the silicon through hole 112 that is no less than LED chip electrode 210 numbers; silicon through hole 112 runs through the silica-based part of die cavity 111 belows; one side of silicon through hole 112 is offered blind hole 113, and its degree of depth is as the criterion can hold esd protection chip 300.
As shown in Figure 13 and Fig. 3, the back side at silicon through hole 112 and blind hole 113 inwalls and silica-based disk 103 arranges insulating barrier I 610 ', the partial insulative layer I 610 ' and the part Heraeus 151 ' that at the interior corresponding LED chip electrode of silicon through hole 112 210 places, remove LED chip electrode 210 places form Heraeus opening 152, utilize successively again sputter, photoetching, electro-plating method forms the discontinuous metal level I 711 of the thin copper material of wire laying mode again, 712, 713, make each silicon through hole 112 and blind hole 113 all have independently metal level I 711, 712, 713, metal level I 711, 712, 713 there is gap each other, simultaneously in metal level I 711, 712, a side of 713 form to connect the metal lead wire 900 of blind hole 113 place's metal level I 713 and silicon through hole 112 place's metal level I 711 wherein or 712.
As shown in figure 14; esd protection chip 300 is mounted to the metal level I 713 in blind hole 113 by conducting resinl 161; esd protection chip electrode 310 is towards the outside of blind hole 113; and Curing conductive adhesive 161; in esd protection chip 300 peripheries, be coated with layer of cloth II 620 again, and offer insulating barrier II opening 621 at esd protection chip electrode 310 places.
As shown in figure 15, on the surface of above-mentioned metal level I 711,712,713 with utilize successively sputter, photoetching, electro-plating method to form the independently metal level II 721,722,723 of corresponding each silicon through hole 112 and blind hole 113 in the surface of insulating barrier II 620 and insulating barrier II opening 621, there is gap in metal level II 721,722,723 each other.
As shown in figure 16, at the surface-coated protective layer 800 of above-mentioned metal level II 721,722,723, and offer protective layer opening I 801, protective layer opening II 802, the protective layer opening III 803 of distinguishing corresponding each silicon through hole 112 and blind hole 113.
As shown in figure 17; in the protective layer opening I 801 and protective layer opening II 802 of silicon through hole 112 correspondences; by printing or plant the mode of soldered ball; form the metal level III 731,732 of solder alloy; by mechanochemistry, grind again, make the flush of the metal level II 723 of metal level III 731,732 and blind hole 113 belows.
As shown in figure 18, cut above-mentioned encapsulation disk, form the independently packaging body of the LED encapsulating structure of esd protection, and carry out the operations such as follow-up sorting, test.
LED encapsulating structure and the method for packing thereof of esd protection of the present invention are not limited to above-described embodiment; any those skilled in the art without departing from the spirit and scope of the present invention; any modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all fall in the protection range that the claims in the present invention define.
Claims (10)
1. a LED method for packing for esd protection, comprises the steps:
Silica-based disk (100) is provided, utilizes the mode of photoetching and etching, at the upper surface of silica-based disk (100), form the recessed die cavity that can hold LED chip (200) (111);
Utilize chip attachment mode by LED chip (200) upside-down mounting to die cavity (111);
Glass wafer (400) is provided, glass wafer (400) is bonded to the top of silica-based disk;
The corresponding LED chip electrode in below (210) at the die cavity (111) of silica-based disk is located, and utilizes photoetching and etching technics formation silicon through hole (112), and in a side of silicon through hole (112), offers the blind hole (113) that can hold esd protection chip (300);
At silicon through hole (112) and the inwall of blind hole (113) and the back side of silica-based disk, insulating barrier I (610) is set, in silicon through hole (112), corresponding LED chip electrode (210) locates to offer Heraeus opening (152), utilize successively again sputter, photoetching, electro-plating method forms and to adhere to independently metal level I (711 of each silicon through hole (112) and blind hole (113) separately, 712, 713), metal level I (711, 712, 713) there is each other gap, simultaneously in metal level I (711, 712, 713) a side form to connect blind hole (113) and locates the metal lead wire (900) that metal level I (713) and a silicon through hole (112) are wherein located metal level I (711) or metal level I (712),
Esd protection chip (300) is mounted to the metal level I (713) in blind hole (113) by conducting resinl (161), esd protection chip electrode (310) is towards the outside of blind hole (113), in esd protection chip (300) periphery, be coated with layer of cloth II (620) again, and locate to offer insulating barrier II opening (621) at esd protection chip electrode (310);
On the surface of metal level I (711,712,713) with utilize successively sputter, photoetching, electro-plating method to form the independently metal level II (721,722,723) of corresponding each silicon through hole (112) and blind hole (113) in the surface of insulating barrier II (620) and insulating barrier II opening (621), there is gap in metal level II (721,722,723) each other;
At the surface-coated protective layer (800) of metal level II (721,722,723), and offer the protective layer opening of distinguishing corresponding each silicon through hole (112) and blind hole (113);
On the surface of the metal level II (721,722) of each silicon through hole (112) below, by printing solder or the mode of planting soldered ball, form metal level III (731,732);
Cut above-mentioned encapsulation disk, form the independently LED encapsulating structure of esd protection, enter subsequent handling.
2. the LED method for packing of esd protection according to claim 1, is characterized in that: utilize chip attachment mode by LED chip (200) upside-down mounting to also comprising step before in die cavity (111):
Mode by sputter or electron beam evaporation plating is in conjunction with mask technology, wet etching mode, inwall and outer at die cavity (111) form reflector layer (120), and formation runs through the reflector layer opening figure (121) that reflector layer (120) can hold LED chip electrode (210).
3. the LED method for packing of esd protection according to claim 2, is characterized in that: described LED chip (200) is connected with the bottom of die cavity (111) by Heraeus (151).
4. the LED method for packing of esd protection according to claim 3, is characterized in that:
Providing glass wafer (400) to comprise afterwards step:
The surface towards die cavity (111) at glass wafer (400) forms phosphor powder layer (510) by the mode spraying or print.
5. the LED method for packing of esd protection according to claim 4, is characterized in that: at glass wafer (400), be bonded to and also comprise step before die cavity (111) top of silica-based disk:
In being provided with the die cavity (111) of LED chip (200), fill filler (131), and solidify.
6. the LED method for packing of esd protection according to claim 5, is characterized in that: in the below of die cavity (111), offer silicon through hole (112) and blind hole (113) also comprises step before:
The silica-based part at the back side of the complete silica-based disk of bonding is thinned to the thickness of setting.
7. the LED method for packing of esd protection according to claim 6, is characterized in that: by printing solder or the mode of planting soldered ball, form metal level III (731,732) and also comprise afterwards step:
By mechanochemistry, grind, make the flush of the metal level II (723) of metal level III (731,732) and blind hole (113) below.
8. the LED encapsulating structure of the esd protection that the LED method for packing of an esd protection as claimed in claim 7 forms, it is characterized in that: comprise silica-based body (110) and with the LED chip (200) of LED chip electrode (210), the one side of described silica-based body (110) is provided with die cavity (111), another side is provided with several silicon through holes (112) and blind hole (113), described silicon through hole (112) is positioned at the below of die cavity (111), blind hole (113) is positioned at a side of silicon through hole (112), described LED chip (200) is arranged in die cavity (111), its LED chip electrode (210) is towards the inner side of die cavity (111), the inwall of described die cavity (111) arranges reflector layer (120), described die cavity (111) top arranges glassy layer (410), the surface towards die cavity (111) of described glassy layer (410) arranges phosphor powder layer (510), described glassy layer (410) is connected by adhesive (141) and die cavity (111), filler (131) is set in described die cavity (111),
The inwall of described silicon through hole (112) and blind hole (113) all arranges insulating barrier I (610), described insulating barrier I (610) outwards extends into the surface of the silica-based body (110) at silicon through hole (112) and/or blind hole (113) place, in described insulating barrier I (610) in each hole, independently multiple layer metal layer is set respectively, described multiple layer metal layer comprises metal level I (711, 712, 713), metal level II (721, 722, 723) and/or metal level III (731, 732), described LED chip (200) is realized electrical communication by the interior described multiple layer metal layer of filling of described LED chip electrode (210) and silicon through hole (112),
Also comprise the esd protection chip (300) with esd protection chip electrode (310), described esd protection chip (300) is arranged between the described multiple layer metal layer in blind hole (113), and realize electrical communication, insulating barrier II (620) is set between described multiple layer metal layer, described esd protection chip (300) is realized serial or parallel connection by metal lead wire (900) and described LED chip (200), and described metal lead wire (900) is arranged at a side of described multiple layer metal layer;
In the peripheral of described multiple layer metal layer and the gap each other at described multiple layer metal layer, protective layer (800) is set, and offers protective layer opening, the outermost layer of multiple layer metal layer described in described protective layer opening exposed portions serve.
9. the LED encapsulating structure of esd protection according to claim 8, it is characterized in that: in described LED chip (200) and metal level I (711, 712) Heraeus (151) is set between, and offer Heraeus opening (152) in the place, top of silicon through hole (112), described metal level I (711, 712) be arranged in the described insulating barrier I (610) in silicon through hole (112), top in silicon through hole (112), described metal level I (711, 712) by Heraeus opening (152), be connected with LED chip electrode (210) respectively, described metal level I (711, 712) surface arranges metal level II (721, 722), in described metal level II (721, 722) surface arranges metal level III (731, 732).
10. the LED encapsulating structure of esd protection according to claim 8; it is characterized in that: described metal level I (713) is arranged in the described insulating barrier I (610) in blind hole (113); described esd protection chip (300) is fixed in the metal level I (713) in blind hole (113) by conducting resinl (161); described esd protection chip electrode (310) is towards the outside of blind hole (113); and described metal level II (723) is set thereon, between described metal level I (713) and metal level II (723), insulating barrier II (620) is set.
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