CN102693972A

CN102693972A - Light emitting diode package and manufacture method of lead frame of the light emitting diode package

Info

Publication number: CN102693972A
Application number: CN2012101645211A
Authority: CN
Inventors: 彭胜扬
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2011-12-23
Filing date: 2012-05-24
Publication date: 2012-09-26
Also published as: TW201327948A; US20130161670A1

Abstract

The invention discloses a light emitting diode package and a manufacture method of a lead frame of the light emitting diode package. According to the invention, the LED possesses good heat dissipation. In a specific embodiment, only weld filler metal is provided at the space between the lead frame and a circuit board, good heat exchange performance is provided from the LED chip to the circuit board. In the specific embodiment, the side wall of the lead frame is inclined to provide improved light radiation.

Description

The manufacture method of LED package and lead frame thereof

Technical field

The present invention relates to a kind of semiconductor element encapsulation, and particularly relate to the encapsulation and the manufacture method of a kind of light-emitting diode (LED).

Background technology

Along with the brightness and the luminous efficiency of light-emitting diode (LED) chip are improved, LED more is widely used in illumination.Because led chip has the problem of heat radiation, often cause the brightness and the real colour degree variation of led light source.But if use ceramic base material for main packaged type comes the encapsulation LED chip, it is many then can to cause the LED packaging cost to improve.Therefore, present industry needing to look forward to the encapsulating structure of tool good heat radiating efficient and lower cost.

Summary of the invention

For addressing the above problem, the present invention provides a kind of semiconductor element encapsulation.The encapsulation of this semiconductor element comprises a lead frame, the tool metal base, is positioned at a first metal layer and one second metal level that is positioned at the lower surface of this metal base of the upper surface of this metal base.This lead frame defines a depression and has a depression bottom surface portions.This semiconductor element encapsulation more comprises at least one light-emitting diode (LED) chip, is arranged at and is electrically connected on this first metal layer of this depression bottom surface portions.The encapsulation of this semiconductor element more comprises an adhesive body, is arranged on this first metal layer, and coats this led chip and this first metal layer of part at least.This second metal level comes out fully.

This also provides a kind of semiconductor element encapsulation.This semiconductor element encapsulation comprises a lead frame, and it defines a depression and has interior surface opposing and outer surface.The encapsulation of this semiconductor element more comprises at least one light-emitting diode (LED) chip, is arranged on this inner surface of this lead frame and is electrically connected to this inner surface of this lead frame.The encapsulation of this semiconductor element more comprises an adhesive body, coat this at least one led chip and at least part cover this inner surface of this lead frame.This outer surface of this lead frame is not covered by any adhesive body.

The present invention also provides a kind of making to be used for the method for the lead frame of semiconductor element encapsulation.This method comprises punching press one planar metal substrate to produce a plurality of depression aggregated(particle) structures, and structure defines a depression each time, and is extended with a web from its periphery.This method more is included in and forms one first photoresist layer on the upper surface of this metallic substrates, and on a lower surface of this metallic substrates, forms one second photoresist layer.This method more is included in and forms one first photoresist pattern in this first photoresist layer, and in this second photoresist layer, forms one second photoresist pattern.This method more comprises uses this first and second photoresists pattern as photomask; On this upper surface of this metallic substrates, do not formed a first metal layer, and on this lower surface of this metallic substrates, do not formed one second metal level by the zone of this second photoresist pattern covers by the zone of this first photoresist pattern covers.This method more comprises and removes this first and second photoresists pattern in this first and second metal level, to form passage.

In one embodiment of this invention, the aforementioned step of this conductive wire frame strip that provides comprises the metal base that a general planar is provided and this metal base is stamped out those base unit.Form this first metal layer on this lead frame upper surface and form this second metal level on this lead frame lower surface.

For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended accompanying drawing to elaborate as follows.

Description of drawings

Figure 1A is a kind of LED encapsulating structure generalized section of one embodiment of the invention;

Figure 1B looks sketch map on the LED encapsulating structure of Figure 1A;

Fig. 2 looks sketch map on a kind of LED encapsulating structure of another embodiment of the present invention;

Fig. 3 A-Fig. 3 F is the generalized section of a kind of each step of lead frame unit manufacturing approach of one embodiment of the invention;

Fig. 3 B ' and Fig. 3 B " be the schematic perspective view of lead frame unit;

Fig. 4 A-Fig. 4 I is the generalized section of a kind of each step of lead frame unit manufacturing approach of another embodiment of the present invention;

Fig. 5 A-Fig. 5 F is the generalized section of a kind of each step of LED method for packing of one embodiment of the invention;

Look sketch map on Fig. 5 E ' Fig. 5 E;

Fig. 6 A-Fig. 6 F looks sketch map on the LED encapsulating structure of the embodiment of the invention.

The main element symbol description

10: lead frame

10A, 10B, 20A: flat conductor frame

10A', 10A ": aggregated(particle) structure

100: substrate

100a: upper surface

100b: lower surface

101A, 101A': at the bottom of the depression

101B, 101B', 101D: sloped sidewall

101C: lead bonding land

101E: web part

102,104,102', 104': photoresist layer

102a, 104a, 104'a: photoresist pattern

106,108: metal level

105,105', 107: breach

120: central pad

122: peripheral part

200: chip

202: adhesion coating

204: contact

206: fluorescence coating

210: lead

220: adhesive body

20: conductive wire frame strip

30: scolder

40: motherboard

50,50': encapsulating structure

S: opening

Embodiment

Figure 1A-Figure 1B is depicted as the semiconductor component packaging structure 50 according to one embodiment of the invention, and it comprises lead frame 10, one or more led chip 200, lead 210 and adhesive body 220.Encapsulating structure 50 is through scolder or soldered ball 30 and electrically reach physical property and be connected to a wiring board 40.Wiring board 40 for example is a printed circuit board (PCB) (PCB), is the wiring board outside the encapsulating structure 50.Led chip 200 is anchored to lead frame 10, and lead 210 electrically connects led chip 200 to lead frame 10.Adhesive body 220 is around coating led chip 200 and lead 210.Semiconductor element encapsulation 50 via scolder 30 physical property be electrically connected to circuit board 40.Circuit board 40 (it can be printed circuit board (PCB) in one embodiment) is in the outside of semiconductor device 50.

Referring to Figure 1A, lead frame 10 comprises metal base 100 and the first metal layer 106 and second metal level 108 of being located at the two sides.Lead frame 10 comprises metallic substrates or core layer 100, be arranged on first or the upper metallization layer 106 and second or lower metal layer 108 on the apparent surface of metallic substrates 100.For example plating capable of using or any other technologies make metal level 106,108 combine with metal core layer 100.Lead frame 10 also comprises depression 101, the first sloped sidewall 101B that said depression 101 has 101A at the bottom of the depression, 101A extends at the bottom of the depression, extends and the lead bonding land 101C of level, the second sloped sidewall 101D that 101C extends from the bonding land and the web part 101E that extends from the second sloped sidewall 101D substantially from the first sloped sidewall 101B.The first sloped sidewall 101B, parallel lead bonding land 101C and the second sloped sidewall 101D " sidewall " that can be referred to as lead frame 10 substantially.

Each sloped sidewall, bonding land and web around the scope (shown in Figure 1B) that limits lead frame 10, and form continuous ladder or height (shown in Figure 1A) with the mode of joining continuously.Though show three ladders, can provide still less or more ladder to be suitable for arbitrary set application.101A at the bottom of the depression upwards arranges these ladders with abducent mode.Therefore, lead frame 10 is defined as re-entrant angle taper or the recessed taper shape of upper diameter (the height place of web part 101E) greater than lower diameter (the height place of 101A at the bottom of the depression).

101A comprises a plurality of chip mats 118 and surrounds central pad 120 at the bottom of the depression.Chip mat 118 is physical properties and electrically separates with central pad 120.Chip 200 is attached to chip mat 118 and lead joins central pad 120 to, and is attached to lead bonding land 101C via lead 210.Central pad 120 is served as common-battery district (electrical common), and it can be for example power supply or ground connection.

Chip 200 can connect with physics mode and/or electrical mode via other technologies in depression 101.For instance, chip 200 can join chip mat 118 downwards to.Except that lead engaged, chip 200 possibly be to be inverted so that its active surface is downward and flip-chip bonded arrives lead frame 10.

Continuation is with reference to Figure 1A, and adhesive body 220 is filled or part is filled depression and encapsulate chip 200 and lead 210.Adhesive body 220 can be for example silica gel resin or epoxy resin or other materials.Adhesive body 220 can further comprise light converting substances particle (for example fluorescent grain) so that produce desired photochromic.In another embodiment, the fluorescence coating (not shown) can be between chip 200 and adhesive body 220.Fluorescence coating can cover the upper surface and/or the side surface of chip 200.In addition, fluorescence coating can be arranged on the bottom of the depression that is defined by the first inclined wall 101B, and adhesive body 220 is arranged on the top of the depression that is defined by the second inclined wall 101D.

Sloped sidewall

101B, 101D part at least surround installation region and chip 200.The light that sloped

sidewall

101B, 101D send from chip 200 with the advantageous manner reflection, thus the light that increases semiconductor element encapsulation 50 is exported.In one embodiment, metal level 106 for example can be served as reasons: the high reflecting metal layer that silver (Ag), platinum (Pt), tin (Sn) or other materials are processed is used for further increasing light output.Preferable, web part 101E top do not exist in order to receive the material of the light that sends from chip 200.That is to say, do not have for example adhesive material in this zone.Therefore, sending light from chip 200 has vast scale more to be tilted the high reflecting surface reflection of

sidewall

101B, 101D, increases the light emission from semiconductor element encapsulation 50.

In the embodiment shown in Fig. 1, Fig. 2, Fig. 5 G, Fig. 6 C and Fig. 6 F; Lead frame is divided into the middle body that is surrounded by other parts by open S; This provides favorable mechanical stability; Can resist because of thermal coefficient of expansion between adhesive body 220 and the lead frame 10' (coefficient of thermal expansion, the problem that CTE) does not match and cause.

For further strengthening light output, can select to adjust angle, that is angle θ 1, θ 2 (101A and the folded angle of horizontal bonding land 101C are θ 1, θ 2 at the bottom of

sloped sidewall

101B, 101D and the depression).In the embodiment shown, angle θ 1, θ 2 equate substantially.Yet in other embodiments, angle θ 1, θ 2 possibly be unequal.Utilize simulation to find, 140 ° of interior angles of-170 ° of scopes can provide the luminescent properties of enhancing.Yet in other embodiments, angle θ 1, θ 2 can be about 90 °, make that

sidewall

101B, 101D are vertical substantially.

Continuation is with reference to Figure 1A, semiconductor element encapsulation 50 via scolder 30 physical property be electrically connected to circuit board 40.Yet; Before being connected to circuit board 40; The lower surface 108A of lower metal layer 108 comes out in the All Ranges of lead frame 10 fully, and the All Ranges of lead frame 10 comprises central pad 120, chip mat 118, the first sloped sidewall 101B, lead bonding land 101C, the second sloped sidewall 101D and web part 101E.Therefore, after being connected to circuit board 40, the main heat transfer path that is used for cooled wafer 200 is to circuit board 40 via scolder 30.Scolder has good heat-conducting as metal.Polymeric material do not have for example polymeric material between chip 200 and the circuit board 40, because of can reduce the thermal conductivity between chip 200 and the circuit board 40.Therefore, embodiments of the invention provide from chip 200 to circuit board 40 fabulous heat transmission, make the operating temperature of chip 200 keep lower, thereby increase its effectiveness of performance and reduce its performance owing to overheated possibility of degenerating.Embodiments of the invention also avoid the use of ceramic bases, use ceramic bases can increase the cost of semiconductor element encapsulation with there is no need.

Fig. 2 explains another kind of semiconductor element encapsulation 50'.Encapsulation 50' comprises lead frame 10', and one or more led chip 200, is fixed to lead frame 10'.Yet with the embodiment different (they comprise the lead 210 that led chip 200 is electrically connected to lead frame 10) of Fig. 1, the led chip 200 among Fig. 2 is to use flip chip technology to install.Further, first sloped sidewall 101B that lead frame 10' comprises 101A at the bottom of the depression, 101A extends at the bottom of the depression and the web part 101E that extends from the first sloped sidewall 101B.Lead frame 10' does not comprise the lead bonding land 101C or the second sloped sidewall 101D.Breach S with depression at the bottom of 101A be separated into first and second parts 120,122, and breach S defines the scope of first 120 and the scope that second portion 122 defines breach S.With led chip 200 be arranged in that lead frame 10' goes up and each chip all across the both sides of breach.This configuration (it is also shown among some embodiment of hereinafter) provides favorable mechanical stability; Can resist because of thermal coefficient of expansion (coefficient ofthermal expansion, the problem that CTE) does not match and cause between adhesive body 220 and the lead frame 10'.

Fig. 3 A to Fig. 3 F describes the step of making according to an embodiment of the invention in the LED semiconductor element encapsulation method therefor.Fig. 3 A describes the metallic substrates 100 that is plate shaped or strip.Metallic substrates 100 can be Copper Foil tool thickness and is for example about 100-150 micron, or other suitable materials are obtained.

Referring to Fig. 3 B, stamping technology makes metallic substrates or core layer 100 form a plurality of depression aggregated(particle) structure 100A.Separate dotted line A-A and be separated out an aggregated(particle) structure 100A.Aggregated(particle) structure 100A can have circle or square plate-like or dish shape shape.Fig. 3 B' describes an illustrative aggregated(particle) structure 100A', the disc of the similar tool web of its shape.Said disc comprises 101A at the bottom of the square depression, the sloped sidewall 101B that extends at the bottom of its cave and the web part 101E that extends from sloped sidewall 101B.Fig. 3 B " describes another illustrative aggregated(particle) structure 100A ", aggregated(particle) structure 100A " shape also as the disc of tool web, but it has 101A' and a continuous sloped sidewall 101B' at the bottom of the circular depression.(please correspondingly revise Fig. 3 B, Fig. 3 B ' and Fig. 3 B "; And remove Fig. 3 C, the 10A of Fig. 3 D)

Referring to Fig. 3 C, the first photoresist layer 102 is formed on the upper surface 100a of metallic substrates 100, and the second photoresist layer 104 is formed on the lower surface 100b of metallic substrates 100.102,104 for example spraying capable of using of the first and second photoresist layers or dip-coating or other technologies form.The photoresist layer that utilizes spraying to form more likely has uniformity and consistency preferably.Yet dip-coating can be in order to form photoresist layer 102,104 at surperficial 100a, 100b on both simultaneously.The thickness of the first and second photoresist layers 102,104 can be for example 6 microns or other thickness.

Referring to Fig. 3 D, the first photoresist pattern 102a is formed on the upper surface 100a, and the second photoresist pattern 104a is formed on the lower surface 100b of metallic substrates 100.For example etching capable of using of these patterns or other technologies form.In the embodiment shown,

photoresist pattern

102a, 104a are identical, but in other embodiments, the first photoresist pattern 102a maybe be different with the second photoresist pattern 104a.

Referring to Fig. 3 E; Using under the first and second photoresist pattern 102a, the situation of 104a as photomask; The first metal layer 106 is formed at not by on the upper surface 100a of first photoresist pattern 102a covering, and second metal level 108 is formed at not by on the lower surface 100b of second photoresist pattern 104a covering.Any one among both of the first metal layer 106 and second metal level 108 all can be individual layer or many layer of metal foil (for example nickel/gold (Ni/Au) lamella).Layer 106,108 capable of using for example plating or the other technologies making.

Referring to Fig. 3 F, the first and

second photoresist layer

102a, 104a form path 10 5,107 in first and second metal levels 106,108 through removing.Though seeming all has two path 10s 5,107 in each metal level 106,108, in fact breach possibly be the different piece in the same breach shown in two in each metal level 106,108.The structure of Fig. 3 F comprises conductive wire frame strip 20, and said conductive wire frame strip 20 comprises a plurality of lead frame unit 10A.In process subsequently, conductive wire frame strip 20 and chip and other electronic installations are assembled.After the assembling, will be along separator bar A wire cutting frame bar 20 with separating conductive wires frame unit 10A.

Preferable situation, the method shown in Fig. 3 A to Fig. 3 F are a kind ofly to be used to produce lead frame but to have the simplification technology of less relatively step.Therefore provide low-cost and had enough to meet the need advantages such as quick.

Fig. 4 A to Fig. 4 I describes the step of making according to an embodiment of the invention in used another method of LED semiconductor element encapsulation.Some the step aspects of the embodiment of Fig. 4 A to Fig. 4 I and the embodiment of Fig. 3 A to Fig. 3 F are similar.Therefore, the argumentation that will omit these aspects to Fig. 4 A to Fig. 4 I.

Referring to Fig. 4 A, stamping technology makes metallic substrates or core layer 100 form a plurality of depression aggregated(particle) structure 10A.Referring to Fig. 4 B, the first photoresist layer 102 is formed on the upper surface 100a of metallic substrates 100, and the second photoresist layer 104 is formed on the lower surface 100b of metallic substrates 100.

Referring to Fig. 4 C, the first photoresist pattern 102a is formed on the upper surface 100a of metallic substrates 100.Opposite with the embodiment of Fig. 3 A to Fig. 3 F, on the lower surface 100b of metallic substrates 100, can not form the second photoresist pattern this moment.

Referring to Fig. 4 D, using under the situation of the first photoresist pattern 102a as photomask, the first metal layer 106 is formed at not by on the upper surface 100a of the metallic substrates 100 of first photoresist pattern 102a covering.Referring to Fig. 4 E, the first photoresist pattern 102a is removed and in the first metal layer 106, forms at least one breach 105, and removes the second photoresist layer 104 from the lower surface 100b of metallic substrates 100.

Referring to Fig. 4 F, the upper surface 100a that the 3rd photoresist layer 102' is formed at metallic substrates 100 goes up and is formed on the first metal layer 106.The 4th photoresist layer 104' is formed on the lower surface 100b of metallic substrates 100.Referring to Fig. 4 G, the second photoresist pattern 104'a is formed on the lower surface 100b of metallic substrates 100.

Referring to Fig. 4 H, using under the situation of the second photoresist pattern 104'a as photomask, second metal level 108 is formed at not by on the lower surface 100b of second photoresist pattern 104'a covering.Referring to Fig. 4 I, remove the 3rd photoresist layer 102' and the second photoresist pattern 104'a and in first and

second metal levels

106 and 108, form path 10 5,107.The structure of Fig. 4 I comprises the conductive wire frame strip 20 that comprises a plurality of lead frame unit 10A.In process subsequently, conductive wire frame strip 20 and chip and other electronic installations are assembled.After the assembling, will be along separator bar A wire cutting frame bar 20 with separating conductive wires frame unit 10A.

In the aforementioned embodiment, the technical step of patterning and/or formation metal level can carry out in regular turn on two apparent surfaces of lead frame.Therefore, the last formed metal level of two apparent surfaces of the method permission lead frame is material different or thickness.For instance, the first metal layer 106 can be high reflection silver layer, and second metal level 108 can be nickel and golden lamella (Ni/Au layer).Therefore, the method is that final products provide higher design flexibility.

Fig. 5 A to Fig. 5 F describes the step of making another method of LED semiconductor element encapsulation according to an embodiment of the invention.Referring to Fig. 5 A, conductive wire frame strip 20 comprises the path 10 5,107 in metallic substrates 100, the first metal layer 106, second metal level 108 and the metal level 106,108.Only show a lead frame unit 20A among Fig. 5 A, shown in dotted line A-A.Lead frame unit 20A comprises depression 101.Referring to Fig. 5 A', in another embodiment, the first metal layer 106 can be used as the etching photomask to etch partially to breach 105', so that the degree of depth of breach 105' increases.This step can strengthen lead frame and the adhesive body filled subsequently between adhesion strength.

Referring to Fig. 5 B, at least one chip 200 is arranged on the first metal layer 106 and is arranged on the middle body and (is positioned within the breach 105).Chip 200 can or use other technologies to be fixed to the first metal layer 106 via for example adhesion coating 202.For instance, chip 200 can be led chip (for example high-capacity LED chip).Referring to Fig. 5 C, a plurality of leads 210 are formed between contact 204 and the first metal layer 106 of chip 200 so that chip 200 is connected to the first metal layer 106 with electrical mode.

Referring to Fig. 5 D, fluorescence coating 206 is formed on the chip 200.Fluorescence coating 206 can only cover the upper surface of chip 200, perhaps also covers the side of chip 200.Subsequently, in depression 101, form adhesive body 220 to cover chip 200 and lead 210.Depression 101 can partly filled or fill fully to adhesive body 220.The material of adhesive body 220 can be arbitrary transparent adhesive body material (for example silica gel resin or epoxy resin).When chip 200 for example was the high-capacity LED chip, the envelope mold materials of preferable use silica gel resin caused the yellow problem to avoid high temperature.And, can use the envelope mold materials of epoxide resin material if use general led chip, have higher hardness and adhesion strength preferably is provided.

Referring to Fig. 5 E, using under the situation of second metal level 108 as the etching photomask, come out up to adhesive body 220 from breach 107 beginning etching metal substrates 100 (from following beginning etchings), so that form open S.The complete penetrating metal substrate 100 of open S, and make 101A tool central pad 120 at the bottom of the depression, all the other of said

central pad

120 and 101A at the bottom of the depression or peripheral part 122 are electrically separated.Though central pad 120 electrically is separated from each other with peripheral part 122, they interconnect via adhesive body 220 physical properties.

Referring to Fig. 5 F and Fig. 5 G, form a plurality of independent encapsulating structure 50' along separator bar A wire cutting frame bar 20 thereby carry out singulation step.Each encapsulating structure 50' all comprises single lead frame 10B.The encapsulating structure 50 of encapsulating structure 50' and Figure 1A and Figure 1B is similar, but encapsulating structure 50' only comprises single chip 200 and less ladder in sidewall 101B.In follow-up step, semiconductor element encapsulation 50' is connected to the circuit board (not shown) with physics mode and electrical mode.Yet; With reference to figure 5F; Before being connected to circuit board, the lower surface 108A of lower metal layer 108 comes out in the All Ranges of lead frame 10B fully, and the All Ranges of lead frame 10B comprises central pad 120, peripheral part 122, the first sloped sidewall 101B and web part 101E.

Fig. 6 A to Fig. 6 F describes several kinds of LED encapsulating structures that different configuration designs are arranged for open S.For clarity sake, omit adhesive body.Referring to Fig. 6 A and Fig. 6 D, open S can be linear channel.Referring to Fig. 6 B and Fig. 6 E, open S can be L shaped groove.Referring to Fig. 6 C and Fig. 6 F, open S can be the Q-RING line trenches that is positioned at 101A' at the bottom of the depression.Referring to Fig. 6 A to Fig. 6 C, chip 200 utilizes lead 210 to be electrically connected to lead frame unit.Referring to Fig. 6 D to Fig. 6 F, chip 200 possibly be electrically connected to lead frame unit via the flip chip technology that comprises solder bump.

Though described with reference to specific embodiment of the present invention and explanation the present invention, these descriptions and explanation do not limit the present invention.It will be understood by one of ordinary skill in the art that and under the prerequisite that does not break away from the true spirit of the present invention that defines by appended claims and scope, to make various changes and replacement equivalent.These explanations possibly be not necessarily drawn to scale.Because manufacturing technology and manufacturing tolerance possibly exist difference between artistic rendition among the present invention and the practical structures.Possibly exist other embodiment that the present invention does not specify.Specification and accompanying drawing are considered to illustrative rather than restrictive.Can make an amendment so that the composition of particular case, material, material, method or technology are fit to the object of the invention, spirit and scope.All said modifications are all hoped to be included in the scope of appended claims of the present invention.Though describe the method that discloses among the present invention with reference to the specific operation of carrying out by particular order, should be appreciated that these operations can be through combination, gradation or rearrangement to be to form the equivalent method that does not break away from religious doctrine of the present invention again.Therefore, only if special instructions among the present invention, the order of these operations does not limit the present invention with grouping.

Claims

1. semiconductor element encapsulation comprises:

Lead frame comprises that metal base, the first metal layer are positioned at the upper surface of this metal base and the lower surface that second metal level is positioned at this metal base, and wherein this lead frame defines a depression, has the depression bottom surface portions;

At least one light-emitting diode (LED) chip is arranged at and is electrically connected on this first metal layer of this depression bottom surface portions; And

Adhesive body is arranged on this first metal layer, and coat this led chip with at least the part this first metal layer, wherein this second metal level comes out fully.

2. semiconductor element as claimed in claim 1 encapsulation, at least one opening that runs through of this depression bottom surface portions tool wherein, this runs through opening this depression bottom surface portions is divided into two parts, and these two parts are electrically isolated each other.

3. semiconductor element as claimed in claim 2 encapsulation, wherein this run through opening with this depression bottom surface portions of this lead frame be divided into by this run through opening institute around a middle body be positioned at this and run through opening peripheral part outward.

4. semiconductor element encapsulation as claimed in claim 1 also comprises a stepped depression sidewall sections.

5. semiconductor element encapsulation as claimed in claim 1; Wherein this depression also has the first depression sidewall sections, horizontal component and the second depression sidewall sections; And this first depression sidewall sections extends upward with one first angle from this depression bottom surface portions; This horizontal component extends out from this depression sidewall sections, and this second depression sidewall sections extends upward away with one second angle from this horizontal component.

6. semiconductor element encapsulation as claimed in claim 5, wherein this first angle is in 140 ° of-170 ° of scopes.

7. semiconductor element encapsulation as claimed in claim 5, wherein this second angle is in 140 ° of-170 ° of scopes.

8. semiconductor element encapsulation as claimed in claim 5 also comprises a web part, extends out from this second depression sidewall sections.

9. a making is used for the method for the lead frame of semiconductor element encapsulation, and this method comprises:

Punching press one planar metal substrate is to produce a plurality of depression aggregated(particle) structures, and structure defines a depression each time, and is extended with a web from its periphery;

On the upper surface of this metallic substrates, form one first photoresist layer, and on the lower surface of this metallic substrates, form one second photoresist layer;

In this first photoresist layer, form one first photoresist pattern, and in this second photoresist layer, form one second photoresist pattern;

Use this first and second photoresists pattern as photomask; On this upper surface of this metallic substrates, do not formed a first metal layer, and on this lower surface of this metallic substrates, do not formed one second metal level by the zone of this second photoresist pattern covers by the zone of this first photoresist pattern covers; And

Remove this first and second photoresists pattern in this first and second metal level, to form passage.

10. making as claimed in claim 9 is used for the method for the lead frame of semiconductor element encapsulation, wherein those passages in this first metal layer on the position corresponding to those passages in this second metal level.