CN104253162A - 双向esd二极管结构及其形成方法 - Google Patents
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Abstract
本申请案涉及一种双向ESD二极管结构及其形成方法。一种双向静电放电二极管结构(200)消耗实质上较少的硅基板面且通过利用p-外延层(214)而提供超低电容,所述p-外延层(214)触及n+下部外延层(212)及n+上部外延层(216)且位于其之间。金属触点(224)触及p+层(218)且位于其上方,所述p+层(218)触及所述n+上部外延层(216)且位于其上方。
Description
技术领域
本发明涉及双向ESD二极管结构,且更特定来说,涉及一种消耗少量硅基板面的具有超低电容的双向ESD二极管结构。
背景技术
静电放电(ESD)电路是保护集成电路免遭通常在处置集成电路时发生的电压尖峰的电路。在操作中,当跨越第一及第二节点的电压差小于击穿电压时,ESD电路在第一节点与第二节点之间提供开路。
然而,当跨越第一及第二节点的电压差形成尖峰而等于或大于击穿电压时,ESD电路在第一与第二节点之间提供低电阻电流路径。不管第一节点上的电压相对于第二节点升高还是第二节点上的电压相对于第一节点升高,双向ESD电路均提供保护。
常规双向ESD电路通常包含齐纳二极管与高击穿电压雪崩二极管的组合。利用齐纳二极管与雪崩二极管的常规组合的缺点之一是,将齐纳二极管与雪崩二极管连接在一起所需的金属引线消耗大量的硅基板面。
图1展示图解说明现有技术双向ESD二极管结构100的实例的横截面图。如图1中所展示,二极管结构100包含p+衬底区域110、触及p+衬底区域110的顶部表面的n+外延区域112及触及n+外延区域112的顶部表面的p+区域114。
二极管结构100还包含横向环绕p+衬底区域110、n+外延区域112及p+区域114的一部分的沟槽隔离结构116。二极管结构100进一步包含触及p+区域114且位于其上方的不导电层120及触及且延伸穿过不导电层120以形成到p+区域114的电连接的金属触点122。另外,二极管结构100包含触及不导电层120及金属触点122且位于其上方的不导电层124。此外,不导电层124具有暴露金属触点122的开口130。
在操作中,p+区域114形成顶部齐纳二极管的阳极且n+外延区域112形成其阴极,而p+衬底区域110形成底部齐纳二极管的阳极且n+外延区域112形成其阴极,其中两个二极管的阴极连接在一起。
因此,当金属触点122上的电压相对于p+衬底区域110上的电压形成尖峰且超过底部齐纳二极管的击穿电压时,放电电流从金属触点122流动到p+衬底区域110。另一方面,当p+衬底区域110上的电压相对于金属触点122上的电压形成尖峰且超过顶部齐纳二极管的击穿电压时,放电电流从p+衬底区域110流动到金属触点122。
二极管结构100的优点之一是,二极管结构100消耗比齐纳二极管与雪崩二极管的常规组合少得多的硅基板面。然而,二极管结构100的缺点之一是,二极管结构100具有比齐纳二极管与雪崩二极管的常规组合高得多的电容。
举例来说,衬底区域110、n+外延区域112及p+区域114的掺杂剂浓度可经选择使得二极管结构100具有14.7pF的电容,顶部齐纳二极管具有-6.5V的击穿电压,且底部齐纳二极管具有+11V的击穿电压。然而,具有较高电容的二极管结构无法与高速信号应用(例如USB3.0及HDMI1.4)一起使用。因此,需要一种具有低电容的也消耗少量硅基板面的双向ESD二极管结构。
发明内容
本发明提供一种消耗少量硅基板面且提供超低电容的二极管结构。本发明的二极管结构包含第一导电性类型的衬底区域。所述衬底区域具有一掺杂剂浓度。所述二极管结构还包含第二导电性类型的第一半导体层。所述第一半导体层具有一掺杂剂浓度,并触及所述衬底区域且位于其上方。所述二极管结构另外包含所述第一导电性类型的第二半导体层。所述第二半导体层触及所述第一半导体层且位于其上方。所述第二半导体层具有实质上小于所述衬底区域的所述掺杂剂浓度的掺杂剂浓度。所述二极管结构进一步包含所述第二导电性类型的第三半导体层。所述第三半导体层触及所述第二半导体层且位于其上方。另外,所述二极管结构包含所述第一导电性类型的第四半导体层。所述第四半导体触及所述第三半导体层且位于其上方。
本发明还提供一种形成具有超低电容及小的大小的二极管结构的方法。本发明的所述方法包含在衬底区域上外延生长第一半导体层。所述衬底区域具有第一导电性类型及一掺杂剂浓度。所述第一半导体层具有第二导电性类型及一掺杂剂浓度。所述方法还包含在所述第一半导体层上外延生长第二半导体层。所述第二半导体层具有所述第一导电性类型及实质上小于所述衬底区域的所述掺杂剂浓度的掺杂剂浓度。所述方法进一步包含在所述第二半导体层上外延生长第三半导体层。所述第三半导体层具有所述第二导电性类型。
将通过参考以下详细描述及附图来获得对本发明的特征及优点的更好理解,所述附图陈述其中利用本发明的原理的说明性实施例。
附图说明
图1是图解说明现有技术双向ESD二极管结构100的实例的横截面图。
图2是图解说明根据本发明的双向ESD二极管结构200的实例的横截面图。
图3A到3L是图解说明根据本发明形成双向ESD二极管结构的方法300的实例的横截面图。
具体实施方式
图2展示图解说明根据本发明的双向ESD二极管结构200的实例的横截面图。如下文更详细地描述,通过将p-外延层形成为位于两个n+外延层中间来实质上减小二极管结构100的电容。
如图2中所展示,ESD二极管结构200包含p+单晶硅衬底区域210、触及p+衬底区域210的顶部表面的n+外延区域212及触及n+外延区域212的顶部表面的p-区域214。ESD二极管结构200还包含触及p-外延区域214的顶部表面的n+外延区域216及触及n+外延区域216的顶部表面的p+区域218。
二极管结构200还包含横向环绕p+衬底区域210、n+外延区域212、p-区域214、n+外延区域216及p+区域218的一部分的沟槽隔离结构220。二极管结构200进一步包含触及p+区域218且位于其上方的不导电层222及触及且延伸穿过不导电层222以形成到p+区域218的被沟槽隔离结构220环绕的部分的电连接的金属触点224。另外,二极管结构200包含触及不导电层222及金属触点224且位于其上方的不导电层226。此外,不导电层226具有暴露金属触点224的开口230。
二极管结构200的操作与二极管结构100相同,只不过二极管结构200具有实质上较低的电容。当p+衬底区域110及210的掺杂剂浓度实质上相同时,n+外延区域112、212及216的掺杂剂浓度实质上相同,p+区域114及218的掺杂剂浓度实质上相同,且p-外延区域214的掺杂剂浓度实质上小于p+区域218的掺杂剂浓度,与二极管结构100的14.7pF电容相比,二极管结构200具有1.3pF的电容。
另外,与二极管结构100中的顶部二极管的-6.5V击穿电压相比,二极管结构200中的顶部二极管具有-7.9V的击穿电压。此外,与二极管结构100中的顶部二极管的+11V击穿电压相比,二极管结构200中的底部二极管具有+15V的击穿电压。因此,除提供实质上较低的电容以外,二极管结构200中的二极管也具有较大的击穿电压。
图3A到3L展示图解说明根据本发明形成双向ESD二极管结构的方法300的实例的横截面图。如图3A中所展示,方法300利用以常规方式形成的p+单晶硅衬底区域310,且通过在衬底区域310的顶部表面上生长外延结构320而开始。(可在形成外延结构320之前任选地形成硬掩模,使得外延结构320可仅形成于裸片的选定区上。)
以常规方式将外延结构320生长为具有触及p+衬底区域310且位于其上方的n+下部外延层322、触及n+下部外延层322且位于其上方的p-中间外延层324及触及p-中间外延层324且位于其上方的n+上部外延层326。
此外,可在已形成n+下部外延层322之后且在形成n+上部外延层326之前植入砷、锑或磷且将其退火。植入砷、锑或磷控制n+下部外延层322的掺杂剂浓度,此又允许获得多种击穿电压。
另外,还可在已形成n+上部外延层326之后植入砷、锑或磷且将其退火。植入砷、锑或磷控制n+上部外延层326的掺杂剂浓度,此又允许获得进一步的多种击穿电压。
P-中间外延层324具有(举例来说)低于1×1016原子/cm3的掺杂剂浓度,而p+衬底区域310具有(举例来说)大于1×1018原子/cm3的掺杂剂浓度。另外,p-中间外延层324完全位于n+下部外延层322与n+上部外延层326之间。在已形成外延结构320之后,在n+上部外延层326的顶部表面上形成不导电层330(例如氧化物层)。
如图3B中所展示,在已形成不导电层330之后,穿过不导电层330以一剂量将p型掺杂剂植入到n+上部外延层326中,所述剂量足以将n+上部外延层326的顶部部分转换成触及n+上部外延层326的剩余部分且位于所述剩余部分上面的p+层332。接着使用常规方法来扩散经植入掺杂剂。此外,n+上部外延层326完全位于p-中间外延层324与p+层332之间。
如图3C中所展示,一旦已完成植入,便在p+层332上形成不导电层334。可给不导电层334植入(举例来说)原硅酸四乙酯(TEOS)。可沉积TEOS且接着在900℃下将其退火达20分钟以使膜致密。此后,在不导电层334上形成经图案化光致抗蚀剂层336。
以常规方式形成经图案化光致抗蚀剂层336,此包含:沉积光致抗蚀剂层;通过称为掩模的经图案化黑色/透明玻璃板投射光以在光致抗蚀剂层上形成经图案化图像以软化暴露于光的光致抗蚀剂区域;及移除经软化的光致抗蚀剂区域。
如图3D中所展示,在已形成经图案化光致抗蚀剂层336之后,以常规方式蚀刻不导电层334、不导电层330、p+层332、n+上部外延层326、p-中间外延层324、n+下部外延层322及p+衬底区域310的经暴露区域以形成沟槽开口340。接着以常规方式移除经图案化光致抗蚀剂层336,例如借助灰化工艺。
如图3E中所展示,一旦已移除经图案化光致抗蚀剂层336,便以常规方式在不导电层334上沉积不导电层342以给沟槽开口340加衬。可给不导电层342植入(举例来说)氧化物层,后续接着TEOS层。接下来,以常规方式在不导电层342上沉积多晶硅层344以填满沟槽开口340。(在本实例中,在晶片的前面及后面两者上形成多晶硅,且使用众所周知的材料及方法从晶片的后面移除所述多晶硅,例如借助等离子蚀刻。)
接下来,如图3F中所展示,在已沉积多晶硅层334之后,平面化多晶硅层334以及不导电层334及330以暴露p+层322的顶部表面且形成横向且完全环绕p+衬底区域310、n+下部外延层322、p-中间外延层324、n+上部外延层326及p+区域332的一部分的沟槽隔离结构360。可使用(举例来说)化学机械抛光或回蚀来平面化所述层。沟槽隔离结构360包含通过不导电结构364与p+衬底区域310隔离的多晶硅芯362。
如图3G中所展示,在形成沟槽隔离结构360之后,以常规方式在p+区域332上沉积不导电层370。可给不导电层370植入(举例来说)已沉积及致密化的硼磷硅酸盐玻璃(BPSG)。一旦已形成不导电层370,便以常规方式在不导电层370上形成经图案化光致抗蚀剂层372。
如图3H中所展示,在已形成经图案化光致抗蚀剂层372之后,以常规方式蚀刻不导电层370的经暴露部分以形成暴露p+区域332的顶部表面的开口374。在蚀刻之后,以常规方式移除经图案化光致抗蚀剂层372。
如图3I中所展示,在已移除经图案化光致抗蚀剂层372之后,形成金属层376以触及不导电层370、填充开口374且形成与p+区域332的电连接。可给金属层376植入(举例来说)硅化物层、触及所述硅化物层且上覆于其上的钛钨层及触及所述钛钨层且上覆于其上的铝层。
可给所述硅化物层植入(举例来说)硅化铂、硅化钴或硅化钛。另外,以常规方式形成硅化物层,例如通过沉积金属、烧结所述金属以在由所述金属覆盖的每一单晶硅及多晶硅区域上形成硅化物结构,且接着从晶片的不导电区域移除所述金属。在已沉积金属层376之后,以常规方式在金属层346上形成经图案化光致抗蚀剂层380。
如图3J中所展示,在已形成经图案化光致抗蚀剂层380之后,以常规方式蚀刻金属层376的经暴露部分以形成触及p+区域332的顶部表面的金属触点382。在蚀刻之后,以常规方式移除经图案化光致抗蚀剂层380。
如图3K中所展示,在已移除经图案化光致抗蚀剂层380之后,沉积不导电层384以触及不导电层370及金属触点382。在已沉积不导电层384之后,以常规方式在不导电层384上形成经图案化光致抗蚀剂层386。
如图3L中所展示,在已形成经图案化光致抗蚀剂层386之后,以常规方式蚀刻不导电层384的经暴露部分以形成暴露金属触点382的顶部表面的开口390。在蚀刻之后,以常规方式移除经图案化光致抗蚀剂层386以形成二极管结构392。此后,方法300以常规步骤继续。
因此,已描述一种双向二极管结构及一种形成所述双向二极管结构的方法。所述双向二极管结构消耗比现有技术双向二极管结构实质上少的硅基板面,且通过利用触及两个n+外延层且位于其之间的p-外延层而提供超低电容。
应理解,以上描述为本发明的实例,且可在实践本发明时采用本文中所描述的本发明的各种替代方案。因此,打算使所附权利要求书界定本发明的范围且借此涵盖此权利要求书的范围及其等效内容内的结构及方法。
Claims (20)
1.一种二极管结构,其包括:
第一导电性类型的衬底区域,所述衬底区域具有一掺杂剂浓度;
第二导电性类型的第一半导体层,所述第一半导体层具有一掺杂剂浓度,并触及所述衬底区域且位于其上方;
所述第一导电性类型的第二半导体层,所述第二半导体层触及所述第一半导体层且位于其上方,所述第二半导体层具有实质上小于所述衬底区域的所述掺杂剂浓度的掺杂剂浓度;
所述第二导电性类型的第三半导体层,所述第三半导体层触及所述第二半导体层且位于其上方;及
所述第一导电性类型的第四半导体层,所述第四半导体触及所述第三半导体层且位于其上方。
2.根据权利要求1所述的二极管结构,其中所述第三半导体层具有实质上等于所述第一半导体层的所述掺杂剂浓度的掺杂剂浓度。
3.根据权利要求2所述的二极管结构,其中所述第四半导体层具有实质上等于所述衬底区域的所述掺杂剂浓度的掺杂剂浓度。
4.根据权利要求3所述的二极管结构,且其进一步包括触及所述第四半导体层且位于其上方的金属触点。
5.根据权利要求4所述的二极管结构,其中所述第二半导体层完全位于所述第一半导体层与所述第三半导体层之间。
6.根据权利要求5所述的二极管结构,其中所述第三半导体层完全位于所述第二半导体层与所述第四半导体层之间。
7.根据权利要求6所述的二极管结构,且其进一步包括触及所述衬底区域、所述第一半导体层、所述第二半导体层、所述第三半导体层及所述第四半导体层的一部分且横向环绕所述部分的沟槽隔离结构。
8.根据权利要求7所述的二极管结构,其中所述沟槽隔离结构包含多晶硅芯及位于所述多晶硅芯与所述衬底区域之间的隔离结构。
9.根据权利要求7所述的二极管结构,且其进一步包括:
第一不导电层,其触及所述第四半导体层且位于其上方;及
第二不导电层,其触及所述第一不导电层且位于其上方。
10.根据权利要求9所述的二极管结构,其中所述金属触点触及所述第一不导电层的一部分且位于所述部分上方。
11.一种形成二极管结构的方法,其包括:
在衬底区域上外延生长第一半导体层,所述衬底区域具有第一导电性类型及一掺杂剂浓度,所述第一半导体层具有第二导电性类型及一掺杂剂浓度;
在所述第一半导体层上外延生长第二半导体层,所述第二半导体层具有所述第一导电性类型及实质上小于所述衬底区域的所述掺杂剂浓度的掺杂剂浓度;及
在所述第二半导体层上外延生长第三半导体层,所述第三半导体层具有所述第二导电性类型。
12.根据权利要求11所述的方法,且其进一步包括将所述第一导电性类型的掺杂剂植入到所述第三半导体层中以形成触及所述第三半导体层且位于其上方的第四半导体层,所述第四半导体层具有所述第一导电性类型。
13.根据权利要求12所述的方法,其中所述第三半导体层具有实质上等于所述第一半导体层的所述掺杂剂浓度的掺杂剂浓度。
14.根据权利要求13所述的方法,其中所述第四半导体层具有实质上等于所述衬底区域的所述掺杂剂浓度的掺杂剂浓度。
15.根据权利要求14所述的方法,其中所述第二半导体层完全位于所述第一半导体层与所述第三半导体层之间。
16.根据权利要求15所述的方法,其中所述第三半导体层完全位于所述第二半导体层与所述第四半导体层之间。
17.根据权利要求16所述的方法,且其进一步包括形成触及所述衬底区域、所述第一半导体层、所述第二半导体层、所述第三半导体层及所述第四半导体层的一部分且横向环绕所述部分的沟槽隔离结构。
18.根据权利要求17所述的方法,且其进一步包括:
形成触及所述第四半导体层且位于其上方的第一不导电层;及
形成延伸穿过所述第一不导电层以暴露所述第四半导体层的金属开口。
19.根据权利要求18所述的方法,且其进一步包括:
沉积触及所述第一不导电层且位于其上方并填满所述金属开口的金属层;及
蚀刻所述金属层以形成触及所述第四半导体层且位于其上方的金属触点。
20.根据权利要求19所述的方法,且其进一步包括:
形成触及所述第一不导电层及所述金属触点且位于其上方的第二不导电层;及
形成延伸穿过所述第二不导电层以暴露所述金属触点的触点开口。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107644873A (zh) * | 2016-07-20 | 2018-01-30 | 意法半导体(图尔)公司 | 一种过压保护设备 |
CN108520874A (zh) * | 2018-03-28 | 2018-09-11 | 矽力杰半导体技术(杭州)有限公司 | 半导体器件及其制造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108598078B (zh) * | 2018-07-11 | 2024-06-04 | 上海艾为电子技术股份有限公司 | 一种esd保护电路及电子装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4286279A (en) * | 1976-09-20 | 1981-08-25 | Hutson Jearld L | Multilayer semiconductor switching devices |
JPH01125873A (ja) * | 1987-11-10 | 1989-05-18 | Origin Electric Co Ltd | サージ吸収用半導体装置 |
US6555849B1 (en) * | 1998-05-12 | 2003-04-29 | Infineon Technologies Ag | Deactivatable thyristor |
CN1605127A (zh) * | 2001-07-11 | 2005-04-06 | 通用半导体公司 | 具有表面击穿保护的低压穿通双向瞬态电压抑制器件及其制造方法 |
US20120299146A1 (en) * | 2011-05-25 | 2012-11-29 | Texas Instruments Incorporated | Vertical esd protection device |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1253682B (it) * | 1991-09-12 | 1995-08-22 | Sgs Thomson Microelectronics | Struttura di protezione dalle scariche elettrostatiche |
JP3119931B2 (ja) * | 1992-03-31 | 2000-12-25 | 株式会社東芝 | サイリスタ |
US5801420A (en) * | 1994-09-08 | 1998-09-01 | Fuji Electric Co. Ltd. | Lateral semiconductor arrangement for power ICS |
WO1997012405A1 (en) * | 1995-09-25 | 1997-04-03 | Nippon Sheet Glass Co., Ltd. | Surface light-emitting element and self-scanning type light-emitting device |
US6480056B1 (en) * | 1997-06-09 | 2002-11-12 | Sgs-Thomson Microelectronics S.A. | Network of triacs with gates referenced with respect to a common opposite face electrode |
US6674129B1 (en) * | 1999-12-17 | 2004-01-06 | Koninklijke Phillips Electronics N.V. | ESD diode structure |
US6472686B1 (en) * | 2000-10-03 | 2002-10-29 | United States Of America As Represented By The Secretary Of The Army | Silicon carbide (SIC) gate turn-off (GTO) thyristor apparatus and method for high power control |
US6501099B2 (en) * | 2001-03-05 | 2002-12-31 | The United States Of America As Represented By The Secretary Of The Army | Modified-anode gate turn-off thyristor |
US6794631B2 (en) * | 2002-06-07 | 2004-09-21 | Corning Lasertron, Inc. | Three-terminal avalanche photodiode |
US6835993B2 (en) * | 2002-08-27 | 2004-12-28 | International Rectifier Corporation | Bidirectional shallow trench superjunction device with resurf region |
JP2004288680A (ja) * | 2003-03-19 | 2004-10-14 | Mitsubishi Electric Corp | 圧接型半導体装置 |
US7126166B2 (en) * | 2004-03-11 | 2006-10-24 | Semiconductor Components Industries, L.L.C. | High voltage lateral FET structure with improved on resistance performance |
JP2007305959A (ja) * | 2006-04-10 | 2007-11-22 | Seiko Epson Corp | 光素子およびその製造方法 |
US7804150B2 (en) * | 2006-06-29 | 2010-09-28 | Fairchild Semiconductor Corporation | Lateral trench gate FET with direct source-drain current path |
JP5172654B2 (ja) * | 2008-12-27 | 2013-03-27 | 株式会社東芝 | 半導体装置 |
FR2953062B1 (fr) * | 2009-11-24 | 2011-12-16 | St Microelectronics Tours Sas | Diode de protection bidirectionnelle basse tension |
TW201209993A (en) * | 2010-08-19 | 2012-03-01 | Beyond Innovation Tech Co Ltd | ESD-protection structure |
FR2968835A1 (fr) * | 2010-12-09 | 2012-06-15 | St Microelectronics Tours Sas | Triac quatre quadrants |
TWI430449B (zh) * | 2011-09-29 | 2014-03-11 | Anpec Electronics Corp | 橫向堆疊式超級接面功率半導體元件 |
-
2013
- 2013-06-30 US US13/931,936 patent/US9059324B2/en active Active
-
2014
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-
2015
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4286279A (en) * | 1976-09-20 | 1981-08-25 | Hutson Jearld L | Multilayer semiconductor switching devices |
JPH01125873A (ja) * | 1987-11-10 | 1989-05-18 | Origin Electric Co Ltd | サージ吸収用半導体装置 |
US6555849B1 (en) * | 1998-05-12 | 2003-04-29 | Infineon Technologies Ag | Deactivatable thyristor |
CN1605127A (zh) * | 2001-07-11 | 2005-04-06 | 通用半导体公司 | 具有表面击穿保护的低压穿通双向瞬态电压抑制器件及其制造方法 |
US20120299146A1 (en) * | 2011-05-25 | 2012-11-29 | Texas Instruments Incorporated | Vertical esd protection device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107644873A (zh) * | 2016-07-20 | 2018-01-30 | 意法半导体(图尔)公司 | 一种过压保护设备 |
CN107644873B (zh) * | 2016-07-20 | 2021-06-22 | 意法半导体(图尔)公司 | 一种过压保护设备 |
CN108520874A (zh) * | 2018-03-28 | 2018-09-11 | 矽力杰半导体技术(杭州)有限公司 | 半导体器件及其制造方法 |
CN108520874B (zh) * | 2018-03-28 | 2021-04-06 | 南京矽力微电子技术有限公司 | 半导体器件及其制造方法 |
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US9059324B2 (en) | 2015-06-16 |
US20150001672A1 (en) | 2015-01-01 |
US20150243757A1 (en) | 2015-08-27 |
US9337299B2 (en) | 2016-05-10 |
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