CN104143505B - 自对准环绕结构 - Google Patents

自对准环绕结构 Download PDF

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CN104143505B
CN104143505B CN201310217498.2A CN201310217498A CN104143505B CN 104143505 B CN104143505 B CN 104143505B CN 201310217498 A CN201310217498 A CN 201310217498A CN 104143505 B CN104143505 B CN 104143505B
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让-皮埃尔·科林格
江国诚
郭大鹏
卡洛斯·H.·迪亚兹
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了垂直环绕结构及其制造方法的实施例。制造自对准的垂直环绕结构器件的方法实施例包括：环绕半导体柱从结构层伸出的暴露部分形成间隔件；在结构层的被保护部分和间隔件的第一部分上方形成光刻胶；蚀刻掉结构层设置在由间隔件和光刻胶共同限定的边界的外部的未被保护部分以形成具有底脚部分和非底脚部分的结构，底脚部分和非底脚部分共同环绕半导体柱；以及去除光刻胶和间隔件。本发明还提供了自对准环绕结构。

Description

自对准环绕结构
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及半导体器件及其制造方法。
背景技术
半导体器件用于大量的电子器件中，诸如计算机、手机和其他器件。半导体器件包括通过在半导体晶圆上方沉积多种薄膜材料并且图案化薄膜材料以形成集成电路在半导体晶圆上形成的集成电路。集成电路包括诸如金属氧化物半导体（MOS）晶体管的场效应晶体管（FET）。
半导体工业的目标之一是继续缩小独立FET的尺寸并提高其运行速度。为了实现这些目标，开发了围栅FET。除了栅极材料在每条边都环绕沟道区之外，围栅FET在构思上类似于FET。
在垂直围栅（VGAA）晶体管中，栅极环绕垂直半导体柱（例如纳米线）的整个圆周或边界。由于通过沉积金属（薄栅极介电层）并且使用光刻蚀刻多余的金属来制造栅电极，所以栅极图案必定完全环绕纳米线。这将约束将强加于栅极光刻，尤其是栅极掩模平面与至纳米线平面的自对准。该种约束限制了集成密度并且对潜在成品率构成危害。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种制造自对准的垂直围栅器件的方法，包括：环绕半导体柱从栅极层伸出的暴露部分形成间隔件；在所述栅极层的被保护部分和所述间隔件的第一部分上方形成光刻胶；蚀刻掉所述栅极层设置在由所述间隔件和所述光刻胶共同限定的边界的外部的未被保护部分以形成具有底脚部分和非底脚部分的栅极，所述非底脚部分和所述底脚部分共同环绕所述半导体柱；以及去除所述光刻胶和所述间隔件。
在该方法中，所述间隔件是硬掩模间隔件。
在该方法中，所述半导体柱是垂直柱，并且所述栅极层是水平栅极层。
在该方法中，所述栅极层是金属栅极层。
在该方法中，所述间隔件具有至少部分为弧形的间隔件边界。
在该方法中，所述间隔件被形成为环形。
该方法进一步包括：在氧化物层和半导体层上方形成所述栅极层。
根据本发明的另一方面，提供了一种制造自对准的垂直围栅器件的方法，包括：在半导体柱的初始暴露部分的周围以及初始氧化物层上方沉积栅极层；在所述栅极层上方形成附加氧化物层并且平坦化所述附加氧化物层；实施回蚀工艺，以使所述附加氧化物层和栅极层环绕所述半导体柱的初始暴露部分的一部分凹进；环绕保持环绕所述半导体柱的初始暴露部分的所述栅极层以及所述半导体柱的随后暴露部分形成间隔件；在所述栅极层的被保护部分和所述间隔件的第一部分上方形成光刻胶；蚀刻掉栅极层设置在由所述间隔件和所述光刻胶共同限定的边界的外部的未被保护部分以形成具有底脚部分和非底脚部分的栅极，所述底脚部分和所述非底脚部分共同环绕所述半导体柱；以及去除所述光刻胶和所述间隔件。
该方法进一步包括：使用化学机械抛光工艺平坦化所述附加氧化物层。
该方法进一步包括：通过使用化学机械抛光工艺和回蚀工艺去除所述栅极层的上部来限定栅极长度。
在该方法中，所述半导体柱是垂直柱，并且所述栅极层是水平栅极层。
在该方法中，所述栅极层是金属栅极层。
在该方法中，所述间隔件具有至少部分为弧形的间隔件边界。
该方法进一步包括：在通过硅衬底所支撑的二氧化硅层的上方形成所述栅极层。
根据本发明的又一方面，提供了一种垂直围栅晶体管，包括：氧化物层，设置在半导体层上方；半导体柱，从所述氧化物层中伸出；以及栅极，设置在所述氧化物层上方，所述栅极具有共同环绕所述半导体柱的底脚部分和非底脚部分。
在该晶体管中，所述底脚部分的底脚边界为弧形。
在该晶体管中，所述栅极是金属栅极。
在该晶体管中，所述氧化物层是二氧化硅。
在该晶体管中，所述半导体柱是垂直柱，并且所述氧化物层是水平层。
在该晶体管中，所述栅极包括在所述底脚部分和所述非底脚部分的至少一个上所堆叠的间隔件部分，所述间隔件部分环绕所述半导体柱。
附图说明
为了更充分地理解本发明及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1示出垂直围栅晶体管的一个实施例；
图2A和图2B至图5A和图5B示出形成图1的垂直围栅晶体管的实施例的工艺的截面图和俯视图；
图6示出垂直围栅晶体管的实施例；
图7A和图7B至图12A和图12B示出形成图6的垂直围栅晶体管的实施例的工艺的透视图和俯视图；
图13和图14示出具有由于栅极未对准所导致的缺陷的传统的垂直围栅晶体管；
图15和图16示出通过使用底脚补偿未对准的垂直围栅晶体管的实施例；
图17至图19示出传统的垂直围栅晶体管和具有由于未对准所导致的缺陷的传统的垂直围栅晶体管所需的公差；
图20和图21示出使用底脚补偿未对准的垂直围栅晶体管的实施例；
图22是制造自对准的垂直围栅器件的方法的实施例；以及
图23是制造自对准的垂直围栅器件的方法的实施例。
除非另有指定，否则不同附图中相应的数字和标号通常指的是相应的部件。绘制附图是以清晰地示出多个实施例的相关方面，并且附图不必按比例绘制。
具体实施方式
以下详细论述本发明实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的创造性构思。所论述的具体实施例仅为示例性的，而不用于限制本发明的范围。
将参照具体上下文中的实施例来描述本发明，即，垂直围栅（VGAA）晶体管。尽管如此，本文中所公开的发明构思不限于自对准栅极的形成。实际上，还可以使用本文中所公开的发明构思来形成除栅极之外的其他自对准结构。此外，即使本发明涉及VGAA晶体管的实施例，本发明所公开的发明构思也可以应用于其他类型的集成电路、电子结构等。
现参照图1，示出了垂直围栅（VGAA）晶体管10的一个实施例。如图所示，VGAA晶体管10包括支撑氧化物层14的衬底12。在一个实施例中，衬底12是由硅、块状硅或者半导体材料形成。在一个实施例中，氧化物层14是诸如二氧化硅（SiO2）的氧化物。其他介电材料可以用于氧化物层14，例如，氮氧化物或者氮化物。
半导体柱（semiconductor column）16伸出到氧化物层14之外。在一个实施例中，半导体柱16是由硅所形成的纳米线。在一个实施例中，半导体柱是由其他半导体材料形成，诸如硅锗（SiGe）、碳化硅（SiC）、硅碳锗（SiCGe）、锗（Ge）、III-V族化合物或者其他半导体材料。半导体材料可以是单晶、多晶或非晶材料。如图1所示，半导体柱16相对于水平定向的氧化物层14垂直定向。然而，本文中预期包括其他配置和定向。图1示出的半导体柱的截面图是圆形，但可以使用其他截面形状（例如，正方形、六边形、矩形、椭圆形、三角形或者具有尖角或圆角的形状）。
仍参照图1，在氧化物层14上方形成栅极18。在一个实施例中，栅极18可以是除了栅极以外并由非金属材料形成的其他器件。栅极18通常包括底脚（footer）部分20（又称为间隔件限定部分）和非底脚部分22（又称为栅极掩模限定部分）。在一个实施例中，底脚部分20是具有弧形边界24的环形。在一个实施例中，非底脚部分22为具有相应的边界26的矩形、正方形、六边形、椭圆形、三角形或者具有尖角或圆角的其他形状。即使如此，也可以将栅极18形成为多种合适配置中的任何一种。
如以下更全面地描述的，即使在VGAA晶体管10的制造期间由于诸如无意地未对准栅极掩模所导致的相对于半导体柱16没有理想地设置栅极18的非底脚部分22，也能够确保栅极18的底脚部分20和非底脚部分22共同地围绕或者环绕半导体柱16。
参照图2A和图2B至图5A和图5B，共同示出了制造图1的VGAA晶体管10的工艺流程。分别地，如在图2A和2B的透视图和俯视图所示，环绕半导体柱16从栅极层30伸出的部分形成间隔件28。同样地，间隔件28覆盖和保护下面的栅极层30。在一个实施例中，间隔件28是具有弧形边界32的硬掩模间隔件。换句话说，间隔件28可以形成为环形。在一个实施例中，栅极层30是金属栅极层并且包括薄栅极介电层（未示出）。
现参照图3A和3B，光刻工艺从形成光刻胶34开始。如图所示，在栅极层30的被保护部分36和间隔件28的一部分上方形成光刻胶34。换句话说，光刻胶34覆盖并保护下面的栅极层30未被间隔件28保护的部分。
现在参照图3A和3B以及图4A和4B，蚀刻掉栅极层30的未被保护部分，该未被保护的部分位于由间隔件28和光刻胶34共同限定的边界40的外部。在一个实施例中，使用干蚀刻工艺或者其他合适的蚀刻工艺蚀刻掉未被保护部分38。通过蚀刻掉栅极层30的未被保护部分38，如图4A和图4B所示，形成具有底脚部分20和非底脚部分22的栅极18。
底脚部分20在尺寸和形状上通常与间隔件28相对应，而非底脚部分22在尺寸和形状上通常与光刻胶34相对应。如以下更详细地描述的，即使用于形成栅极18的掩模无意地未对准，栅极18的底脚部分20和非底脚部分22也共同围绕半导体柱16。
仍参照图3A和图3B以及图4A和图4B，在去除栅极层30的未被保护部分38并限定栅极18之后，去除光刻胶34。此后，如图5A和图5B所示，去除间隔件28以形成图1的VGAA晶体管10的实施例。
现参照图6，示出了垂直围栅（VGAA）晶体管42的一个实施例。图6的示例性VGAA晶体管42类似于图1的VGAA晶体管10。实际上，VGAA晶体管42包括衬底12、氧化物层14和半导体柱16。然而，图6的示例性VGAA晶体管42的栅极44与图1的示例性VGAA的栅极18略有不同并且具有与图1的示例性VGAA的栅极18不同的配置。
参照图7A和图7B至图12A和图12B，共同地示出了制造图6的VGAA晶体管42的工艺流程。如图7A和图7B所示，在氧化物层14和半导体柱16的最初的暴露部分上方同时形成栅极层30和栅极层46。在图7A中，栅极层30和栅极层46是覆盖绝缘层14和半导体柱16的沉积层。沉积层覆盖绝缘层14的部分被称为栅极层30，而沉积层覆盖半导体柱16的部分被称为栅极层46。栅极层30和栅极层46是由合适的栅极材料形成并且共同形成器件的栅极或栅叠层。
在一个实施例中，栅极层46是具有弧形边界48的金属栅极间隔件。换句话说，栅极层46可以形成为环形。在一个实施例中，栅极层30是金属栅极层。由于同时形成栅极层30和栅极层46，所以它们通常具有均匀的厚度。
现在参照图8A和图8B，在栅极层30上方以及在栅极层46周围沉积附加氧化物层50。此后，使用化学机械抛光工艺（CMP）以使附加氧化物层50的表面变平，并且使用回蚀工艺使附加氧化物层50和栅极层46凹进以提供期望高度（其等于凹进的附加氧化物层50的厚度）的栅极层46。
如图9A和9B所示，环绕半导体柱16的随后暴露部分形成间隔件52。间隔件52覆盖并保护下面的栅极层30的多部分和栅极层46。在一个实施例中，间隔件52是具有弧形边界54的硬掩模间隔件。换句话说，间隔件52可以形成为环形。
现在参照图10A和图10B，光刻工艺从形成光刻胶34开始。如图所示，在栅极层30的被保护部分36和间隔件52的一部分上方形成光刻胶34。因此，光刻胶34覆盖并保护未被间隔件52保护的下面的栅极层30。
现在参照图10A和图10B以及图11A和图11B，蚀刻掉栅极层30的未被保护部分38，未被保护部分38位于由间隔件52和光刻胶34共同限定的边界40的外部。在一个实施例中，使用干蚀刻工艺或者其他合适的蚀刻工艺蚀刻掉未被保护部分38。通过蚀刻掉栅极层30的未被保护部分38，如图11A和图11B所示，形成底脚部分20和非底脚部分22。
现在参照图12A和图12B。底脚部分20在尺寸和形状上通常与间隔件52相对应，而非底脚部分22在尺寸和形状上通常与光刻胶34相对应。如以下更详细地描述的，即使用于形成整个栅极44的掩模无意地未对准，底脚部分20和非底脚部分22也共同围绕半导体柱16。
仍参照图12A和图12B，在去除栅极层30的未被保护部分38之后，去除光刻胶34和间隔件52。通过去除光刻胶34和间隔件52，形成图6的示例性VGAA晶体管42。如图所示，由底脚部分20、非底脚部分22和栅极层46的下部共同形成示例性VGAA晶体管42的栅极44。在一个实施例中，当总栅极44是金属栅极时，图12A所示的栅极层46的下部可以用于控制栅极长度。
图13和图14示出具有由于未对准所导致的缺陷的传统的垂直围栅晶体管56。实际上，栅极60没有完全环绕垂直纳米线58。相反，图15和图16示出使用具有底脚66的栅极64补偿未对准的垂直围栅晶体管62的实施例。实际上，因为栅极64（即，栅电极）的底脚66完全围绕或环绕纳米线68。因此，在较差的对准的情况下（即，如果矩形栅极掩模没有完全环绕垂直纳米线68），仍通过栅极材料完全环绕垂直半导体纳米线68。
图17示出具有由栅极74所环绕的多条纳米线72的传统的垂直围栅晶体管70的栅极掩模所需要的公差L。图18和图19示出传统的垂直围栅晶体管70，其处于由于纳米线72相对于栅极74未对准所导致的缺陷的状态。实际上，栅极74没有完全环绕每条垂直纳米线72。相反，图20和图21示出使用具有底脚80的栅极78补偿栅极掩模未对准的垂直围栅晶体管76的一个实施例。实际上，在某种程度上由于底脚80使得栅极78（即，栅电极）完全围绕或环绕每条纳米线82。因此，现在，减小栅极掩模的宽度是可接受的。
现在参照图22，示出了制造自对准的垂直围栅器件的方法84的实施例。在框86中，环绕半导体柱从栅极层伸出的暴露部分形成间隔件。在框88中，在栅极层的被保护部分和间隔件的第一部分上方形成光刻胶。在框90中，蚀刻掉栅极层位于由间隔件和光刻胶共同限定的边界的外部的未被保护部分以形成具有底脚部分和非底脚部分的栅极。非底脚部分和底脚部分共同环绕半导体柱。在框92中，去除光刻胶和间隔件。
现在参照图23，示出了制造自对准的垂直环状结构器件的方法94的实施例。在框96中，在半导体柱的最初暴露部分的周围以及最初的氧化物层上方沉积栅极层。在框98中，在栅极层上方形成附加氧化物层，然后对该附加氧化物层进行平坦化。在框100中，实施回蚀工艺以使附加氧化物层以及栅极层环绕半导体柱的最初暴露部分的一部分凹进。在框102中，环绕保持环绕半导体柱的最初暴露部分的栅极层和半导体柱的随后暴露部分形成间隔件。
在框104中，在栅极层的被保护部分和间隔件的第一部分上方形成光刻胶。在框106中，蚀刻掉栅极层位于由间隔件28和光刻胶共同限定的边界的外部的未被保护部分以形成具有底脚部分和非底脚部分的栅极。非底脚部分和底脚部分共同环绕半导体柱以及栅极46的部分，其中，栅极46的部分围绕柱。在框108中，去除光刻胶34和间隔件28。
通过前述可知，应该认识到，可以使用本文中所公开的构思来制造自对准的垂直环绕栅极。由于栅极（例如印刷栅极）具有并使用底脚（例如，栅极底脚），所以栅极自对准并且确保例如完全围绕垂直纳米线。例如，使用本文中所公开的构思形成的栅极是由“逻辑OR”功能或者栅极掩模和间隔件的底脚的相加性组合的结果。这允许栅极自动自对准并且改善了对印刷栅极层的未对准的公差。同样地，可以放宽关于栅极对准的设计规则，从而增加或改善了封装密度。
此外，改善了栅极与有源区（纳米线）公差对准。可以使栅极层的尺寸（宽度和间距）更紧密。改善的对准公差和紧密的尺寸提高了集成密度。
制造自对准的垂直围栅器件的方法的一个实施例包括：环绕半导体柱从栅极层伸出的暴露部分形成间隔件；在栅极层的被保护部分和间隔件的第一部分上方形成光刻胶；蚀刻掉栅极层设置在由间隔件和光刻胶共同限定的边界的外部的未被保护部分以形成具有底脚部分和非底脚部分的栅极；非底脚部分和底脚部分共同环绕半导体柱；以及去除光刻胶和间隔件。
制造自对准的垂直围栅器件的方法的实施例包括：在半导体柱的最初暴露部分的周围和最初氧化物层上方沉积栅极层；在栅极层上方形成附加氧化物层并且平坦化附加氧化物层；实施回蚀工艺以使附加氧化物层以及栅极层环绕半导体柱的最初暴露部分的一部分凹进；环绕保持环绕半导体柱的最初暴露部分的栅极层以及半导体柱的随后暴露部分形成间隔件；在栅极层的被保护部分和间隔件的第一部分上方形成光刻胶；蚀刻掉栅极层设置在由间隔件和光刻胶共同限定的边界的外部的未被保护部分以形成具有底脚部分和非底脚部分的栅极，该底脚部分和非底脚部分共同环绕半导体柱；以及去除光刻胶和第二间隔件。
垂直围栅晶体管的实施例包括：设置在半导体层上方的氧化物层；从氧化物层伸出的半导体柱；设置在氧化物层上方的栅极，该栅极具有共同环绕半导体柱的底脚部分和非底脚部分。
虽然本发明提供了示例性实施例，但是本说明书并不旨在被解释为限定意义。参照说明书，示例性实施例的各种修改和组合以及其他实施例对于本领域技术人员是显而易见的。因此，所附权利要求意图涵盖任何这种的修改或实施例。

Claims (19)

1.一种制造自对准的垂直围栅器件的方法，包括：
环绕半导体柱从栅极层伸出的暴露部分形成间隔件；
在所述栅极层的被保护部分和所述间隔件的第一部分上方形成光刻胶；
蚀刻掉所述栅极层设置在由所述间隔件和所述光刻胶共同限定的边界的外部的未被保护部分以形成具有底脚部分和非底脚部分的栅极，所述非底脚部分和所述底脚部分共同环绕所述半导体柱；以及
去除所述光刻胶和所述间隔件。
2.根据权利要求1所述的制造自对准的垂直围栅器件的方法，其中，所述间隔件是硬掩模间隔件。
3.根据权利要求1所述的制造自对准的垂直围栅器件的方法，其中，所述半导体柱是垂直柱，并且所述栅极层是水平栅极层。
4.根据权利要求1所述的制造自对准的垂直围栅器件的方法，其中，所述栅极层是金属栅极层。
5.根据权利要求1所述的制造自对准的垂直围栅器件的方法，其中，所述间隔件具有至少部分为弧形的间隔件边界。
6.根据权利要求1所述的制造自对准的垂直围栅器件的方法，其中，所述间隔件被形成为环形。
7.根据权利要求1所述的制造自对准的垂直围栅器件的方法，进一步包括：在氧化物层和半导体层上方形成所述栅极层。
8.一种制造自对准的垂直围栅器件的方法，包括：
在半导体柱的初始暴露部分的周围以及初始氧化物层上方沉积栅极层；
在所述栅极层上方形成附加氧化物层并且平坦化所述附加氧化物层；
实施回蚀工艺，以使所述附加氧化物层和栅极层环绕所述半导体柱的初始暴露部分的一部分凹进；
环绕保持环绕所述半导体柱的初始暴露部分的所述栅极层以及所述半导体柱的随后暴露部分形成间隔件；
在所述栅极层的被保护部分和所述间隔件的第一部分上方形成光刻胶；
蚀刻掉栅极层设置在由所述间隔件和所述光刻胶共同限定的边界的外部的未被保护部分以形成具有底脚部分和非底脚部分的栅极，所述底脚部分和所述非底脚部分共同环绕所述半导体柱；以及
去除所述光刻胶和所述间隔件。
9.根据权利要求8所述的制造自对准的垂直围栅器件的方法，进一步包括：使用化学机械抛光工艺平坦化所述附加氧化物层。
10.根据权利要求8所述的制造自对准的垂直围栅器件的方法，进一步包括：通过使用化学机械抛光工艺和回蚀工艺去除所述栅极层的上部来限定栅极长度。
11.根据权利要求8所述的制造自对准的垂直围栅器件的方法，其中，所述半导体柱是垂直柱，并且所述栅极层是水平栅极层。
12.根据权利要求8所述的制造自对准的垂直围栅器件的方法，其中，所述栅极层是金属栅极层。
13.根据权利要求8所述的制造自对准的垂直围栅器件的方法，其中，所述间隔件具有至少部分为弧形的间隔件边界。
14.根据权利要求8所述的制造自对准的垂直围栅器件的方法，进一步包括：在通过硅衬底所支撑的二氧化硅层的上方形成所述栅极层。
15.一种垂直围栅晶体管，包括：
氧化物层，设置在半导体层上方；
半导体柱，从所述氧化物层中伸出；以及
栅极，设置在所述氧化物层上方，所述栅极具有共同环绕所述半导体柱的底脚部分和非底脚部分；
所述栅极包括在所述底脚部分和所述非底脚部分的至少一个上所堆叠的间隔件部分，所述间隔件部分环绕所述半导体柱，
其中，通过所述底脚部分在尺寸和形状上与附加氧化物间隔件相对应，以补偿未对准的垂直围栅晶体管，所述附加氧化物间隔件环绕所述半导体柱和所述间隔件部分。
16.根据权利要求15所述的垂直围栅晶体管，其中，所述底脚部分的底脚边界为弧形。
17.根据权利要求15所述的垂直围栅晶体管，其中，所述栅极是金属栅极。
18.根据权利要求15所述的垂直围栅晶体管，其中，所述氧化物层是二氧化硅。
19.根据权利要求15所述的垂直围栅晶体管，其中，所述半导体柱是垂直柱，并且所述氧化物层是水平层。
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