CN104051267A - 在sti沟槽中形成半导体材料的方法 - Google Patents

在sti沟槽中形成半导体材料的方法 Download PDF

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CN104051267A
CN104051267A CN201310381600.2A CN201310381600A CN104051267A CN 104051267 A CN104051267 A CN 104051267A CN 201310381600 A CN201310381600 A CN 201310381600A CN 104051267 A CN104051267 A CN 104051267A
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sti
annealing
district
gate dielectric
approximately
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CN104051267B (zh
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马丁·克里斯多夫·霍兰德
乔治斯·威廉提斯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种形成半导体材料的方法，包括在包含氢气（H2）和氯化氢（HCl）以作为工艺气体的环境中对硅区域进行退火。在退火步骤之后，从硅区域的表面处生长半导体区域。

Description

在STI沟槽中形成半导体材料的方法
相关申请的交叉引用
本申请要求于2013年3月13日提交的题目为“Methods for FormingSemiconductor Materials in STI Trenches”的美国临时专利申请第61/780,068号的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体领域，更具体地，涉及在STI沟槽中形成半导体材料的方法。
背景技术
金属氧化物半导体（MOS）晶体管的速度与MOS晶体管的驱动电流密切相关，而驱动电流又与电荷的迁移率密切相关。例如，当其沟道区域中的电子迁移率高时，NMOS晶体管具有高驱动电流，而当其沟道区域中的空穴迁移率高时，PMOS晶体管具有高驱动电流。
由于其具有高电子迁移率，III族和V族元素的化合物半导体材料（已知为III-V族元素化合物半导体）是形成晶体管的良好备选材料。因此，已经开发出基于III-V族元素化合物半导体而形成的晶体管。但是，由于很难获得块状III-V族元素的晶体，因此III-V族元素化合物半导体薄膜需在其他衬底上生长。由于衬底的晶格常数与热膨胀系数与III-V族元素化合物半导体不同，所以在不同的衬底上生长III-V族元素化合物半导体薄膜面临着困难。各种方法已用于形成不会出现严重缺陷的高质量的III-V族元素化合物半导体。例如，从位于浅沟槽隔离区之间的沟槽处生长III-V族元素化合物半导体以减少穿透位错（threading dislocation）的数目。
典型地从沟槽处形成III-V族元素化合物半导体的步骤包括外延生长，然后进行化学机械抛光（CMP）以去除位于浅沟槽隔离区域上方的多余的III-V族元素化合物半导体。通过形成III-V族元素化合物半导体，可以消除一些缺陷。但是，消除的缺陷是非垂直生长的缺陷。因此，随着III-V族元素化合物半导体的生长，缺陷也在生长，从而延伸至并且受到STI区的侧壁的阻挡。这些缺陷包括堆垛层错（stacking fault）及穿透位错。但是，诸如反相域缺陷（anti-phase domain defect）的其他类型的缺陷可以垂直生长，因此不受浅沟槽隔离区的阻挡。这些缺陷不能通过再生长工艺来消除。反相域缺陷是在化合物半导体生长时产生的缺陷。如果诸如硅或锗的单一元素半导体进行生长，则不会出现反相域缺陷。
发明内容
根据本发明的一个方面，提供了一种方法，包括：在包括作为工艺气体的氢气（H2）和氯化氢（HCl）的环境中对硅区域进行退火；以及在退火步骤之后，从硅区域的表面处生长半导体区域。
优选地，在温度介于约700℃和约725℃之间的条件下实施退火，并且在退火期间，将硅区域的单台阶表面转变为双台阶表面。
优选地，实施退火的时间介于约1分钟和约10分钟之间。
优选地，该方法还包括：在硅衬底中形成浅沟槽隔离（STI）区；以及使位于STI区的两部分之间的硅衬底的一部分凹进以形成凹槽，其中，将硅区域的表面暴露于凹槽，并且从凹槽处生长半导体区域。
优选地，该方法还包括：使STI区凹进，其中，半导体区域位于STI区的保留部分的顶面上方的部分形成半导体鳍；在半导体鳍的侧壁和顶面上形成栅极介电质；以及在栅极介电质上方形成栅电极，其中，栅极介电质和栅电极形成鳍式场效应晶体管（FinFET）的一部分。
优选地，在退火期间，HCl的流速介于约5sccm和约200sccm之间。
优选地，在退火期间，H2的流速介于约500sccm和约20000sccm之间。
根据本发明的另一个方面，提供了一种方法，包括：在低于约870℃的温度下对包括硅区域的晶圆进行退火，其中，在退火步骤之前，硅区域包括具有单台阶的表面，并且通过退火步骤使单台阶转变为双台阶；以及在退火步骤之后，从硅区域的表面处生长化合物半导体区域。
优选地，在包括作为工艺气体的氢气（H2）和氯化氢（HCl）的环境中实施退火。
优选地，在温度介于约700℃和约725℃之间的条件下实施退火。
优选地，实施退火的时间介于约1分钟和约10分钟之间。
优选地，该方法还包括：在退火步骤之前，在晶圆的硅衬底中形成浅沟槽隔离（STI）区；以及使硅衬底位于STI区的两部分之间的部分凹进以形成凹槽，其中，硅区域的表面暴露于凹槽，并且从凹槽处生长化合物半导体区域。
优选地，该方法还包括：使STI区域凹进，其中，化合物半导体区域位于STI区域的保留部分的顶面上方的部分形成半导体鳍；在半导体鳍的侧壁和顶面上形成栅极介电质；以及在栅极介电质上方形成栅电极，栅极介电质和栅电极形成鳍式场效应晶体管（FinFET）的一部分。
优选地，在退火期间，HCl的第一流速介于约5sccm和约200sccm之间，而H2的第二流速高于第一流速。
根据本发明的又一个方面，提供了一种方法，包括：在硅衬底中形成浅沟槽隔离（STI）区；使硅衬底位于STI区的两部分之间的部分凹进以形成凹槽；在凹进步骤之后，在包括作为工艺气体的氢气（H2）和氯化氢（HCl）的环境中对硅衬底进行退火，其中，在温度低于约870℃的条件下实施退火；在退火步骤之后，从硅衬底的表面处生长化合物半导体区域，其中，硅衬底的表面位于凹槽中；使STI区域凹进，其中，化合物半导体区域位于STI区的保留部分的顶面上方的部分形成半导体鳍；在半导体鳍的侧壁和顶面上形成栅极介电质；以及在栅极介电质上方形成栅电极，其中，栅极介电质和栅电极形成鳍式场效应晶体管（FinFET）的一部分。
优选地，在温度介于约700℃和约725℃之间的条件下，实施退火。
优选地，实施退火的时间介于约1分钟和约10分钟之间。
优选地，在退火期间，HCl的流速介于约5sccm和约200sccm之间。
优选地，在退火期间，H2的流速介于约500sccm和约20000sccm之间。
优选地，生长化合物半导体区域的步骤包括生长III-V族元素化合物半导体材料。
附图说明
为了更全面地理解实施例及其优势，现结合附图参考以下描述，其中：
图1至图5是根据一些示例性实施例的形成半导体鳍和鳍式场效应晶体管（FinFET）的中间阶段的截面图；
图6示出了在硅上生长的GaAs晶体结构，其中，由于硅表面上的单台阶所以形成了反相域缺陷；以及
图7示出了在硅上生长的GaAs的晶体结构，其中，由于硅表面上的双台阶所以未形成反相域缺陷。
具体实施方式
下面，详细讨论本发明实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
根据示例性实施例提供了从沟槽中生长半导体区域的方法。本发明根据示例性实施例示出了了半导体区域生长的中间阶段。在各种示图和用作说明的实施例中，类似的参考标号用于表示类似的元件。
图1至图5示出了根据示例性实施例的形成半导体鳍和鳍式场效应晶体管（FinFET）的中间阶段的截面图。参见图1，提供了衬底10，其是半导体晶圆100的一部分。衬底10可以是单晶硅衬底。可选地，可以由诸如SiC的其他材料来形成衬底10。在衬底10中形成诸如浅沟槽隔离（STI）区14的隔离区。因此，衬底10包括位于STI区14之间的区域10A，以及位于STI区14下方的区域10B。STI区14的形成工艺可以包括蚀刻衬底10以形成凹槽（由STI区14占据）、使用介电材料来填充凹槽，并实施平坦化以去除多余的介电材料。介电材料的保留部分形成STI区14。在一些实施例中，STI区14包括氧化硅。
然后，如图2所示，蚀刻衬底10的区域10A（位于STI区14的相对侧壁之间）以形成沟槽16。在一些实施例中，衬底10暴露于沟槽16的顶面10’基本上与STI区14的底面14A平齐。在可选实施例中，衬底部分10A的顶面10’高于或低于STI区14的底面14A。可以使用干蚀刻，同时蚀刻气体选自CF4、Cl2、NF3、SF6以及它们的组合来实施蚀刻。在可选实施例中，可以使用湿蚀刻（例如，将四甲基氢氧化铵（TMAH）、氢氧化钾（KOH）溶液等用作蚀刻剂）来实施蚀刻。在生成的结构中，沟槽16的宽度W1可以小于约150nm。宽度W1也可以介于约10nm和约100nm之间。但是，应该理解，通篇说明中所引用的数值仅为实例，并且可以改变为不同的值。
之后，也如图2所示，如箭头15所代表，实施退火工艺。在一些实施例中，在晶圆100处在低于约870℃的温度下时，实施退火。有利地，通过使用低于约870℃的退火温度，晶圆100将不会在退火后发生弯曲（带有明显的翘曲）。但是，如果使用的温度高于约870℃，则晶圆100可能在退火之后弯曲，并因此给后续的集成电路形成工艺带来极大的工艺难度。衬底10的退火温度也可以高于约400℃，并且低于约800℃或低于约750℃。在一些示例性实施例中，退火温度介于约700℃和约725℃之间。实施退火的时间可以介于约1分钟和约10分钟之间，尽管可以使用更长或更短的时间。
在一些实施例中，在工艺腔室（未示出）中实施退火，并且在退火过程中将工艺气体导入腔室内。在一些实施例中，工艺气体包括氢气（H2）和氯化氢（HCl）。在退火过程中，H2的流速可以高于HCl的流速。例如，H2的流速可以介于约500sccm和约20000sccm之间。HCl的流速可以介于约5sccm和约200sccm之间。在H2中对硅进行退火可以导致位于硅区10A顶面处的硅原子的迁移从而形成图6中详细示出的双台阶（doublestep）。此外，在退火过程中，HCl的引入进一步促进了硅原子的迁移，使得在本发明的低温条件下而非在高于870℃的较高温度条件下，实现双台阶的形成。因此，作为退火的结果，硅区10A的顶面10’从单台阶表面转变为双台阶表面，并因此可以基本消除在后续形成的外延区18（图3）中的反相域缺陷或至少减少反相域缺陷的量。
图3示出了半导体区域18的外延。可与退火一起原位实施外延，其中可在相同的工艺腔室中实施外延和退火，尽管可以使用不同的工艺腔室。半导体区域18从露出的顶面10’处外延生长。在一些实施例中，半导体区域18包括可以是二元或三元的III-V族元素化合物半导体材料。用于形成半导体区域18的示例性III-V族化合物半导体材料可以选自InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP以及它们的组合。半导体区域18可以是同质区域，其整体都可由选自以上所列的III-V族元素化合物半导体材料的同一材料形成。半导体区域18也可以是复合区域，具有包括不同材料和/或具有不同组分的多个堆叠的层。例如，半导体区域18的上部相对于衬底10，可具有大于下部的晶格失配。在一些实施例中，半导体区域18包括InAs区域18A、位于InAs区域18A上方的Al2O3区域18B、位于Al2O3区域18B上方的InP区域18C以及位于InP区域18C上方的InAs区域18D。在可选实施例中，跳过Al2O3区域18B的形成，从而相应的半导体区域18包括InAs区域18A、位于InAs区域18A上方的InP区域18C以及位于InP区域18C上方的InAs区域18D。
可以继续外延直至半导体区域18的顶面高于STI区14的顶面14B。然后实施平坦化。平坦化可以包括化学机械抛光（CMP）。继续平坦化直至没有留下覆盖STI区14的半导体区域18。但是，在平坦化之后，半导体区域18中位于STI区14之间的部分得到保留，并且在下文中将其称作半导体带18。在可选实施例中，当半导体区域18的顶面与STI区14的顶面14B平齐或比其低时，停止外延。在这些实施例中，可以跳过或实施平坦化步骤。
参见图4，例如，通过蚀刻步骤使STI区14凹进。因此，部分半导体带18高于STI区14的顶面14B。半导体带18的这部分形成半导体鳍22，如图5所示，半导体鳍22可以用于形成FinFET24。
参见图5，形成栅极介电质26和栅电极28。栅极介电质26可以由诸如氧化硅、氮化硅、氮氧化物、它们形成的多层以及它们的组合的介电材料来形成。栅极介电质26还可以包括高k介电材料。示例性的高k材料可以具有大于约4.0或大于约7.0的k值。栅电极28可以由掺杂的多晶硅、金属、金属氮化物、金属硅化物等形成。栅极介电质26的底端可以接触STI区14的顶面。在形成栅极介电质26和栅电极28之后，可以形成源极区和漏极区（未在示出的平面中）以完成FinFET24的形成。
图6示出了包括从下方的硅区域60处生长的III-V族元素化合物半导体区域62的晶体结构。示出的示例性半导体区域62包括GaAs。使用图例对镓原子、砷原子和硅原子进行标记。图6示出了硅区域60的表面包括级（level）40和级42。从级40转化至级42形成了单台阶44。所以，示出的硅表面是单台阶表面。因此，在其上形成的GaAs晶体62包括两个域A和B，并且用线46示意性的示出了域的边界。因此，在域的边界46处形成反相域缺陷。
但是，通过使用本发明的实施例，可以形成双台阶硅表面，并且将不会发生反相域缺陷。图7示出了包括从衬底部分10A（也在图5中示出）的顶面10’处生长的半导体区域18的晶体结构。示出的示例性半导体区域18也包括GaAs，并且使用图例来对镓原子、砷原子和硅原子进行标记。图7示出了硅区域10A的顶面10’包括级48和级50。从级48转化至级50包括两个台阶52和54。所以，示出的表面10’是双台阶表面。因此，完善的GaAs晶体是从双台阶表面10’处生长的，并且没有形成分隔的域和反相域缺陷。
通过采用使用工艺气体（包括氢气和HCl）的退火，沟槽中的硅表面可以形成双台阶，并且可以将硅表面处的单台阶转变为双台阶。因此，从双台阶表面处形成的化合物半导体可以基本上没有反相域缺陷。可以在例如介于约700℃和约725℃之间的低温下实施退火工艺。在这个温度范围内，借助于HCl，可将硅的单台阶表面可靠地转变为双台阶表面，而完全不会有引起晶圆100翘曲的风险。有利地，当在这个温度范围内退火时，包括其中形成的STI区域的硅晶圆将不会发生翘曲。但是，在传统认知中，为了形成双台阶表面，将单台阶表面转变为双台阶表面所需的退火温度要高于900℃。在这个高温范围内，由于在其中形成的STI区域的影响，晶圆将发生翘曲，并且相应的翘曲的晶圆在随后的半导体工艺中将面临着工艺困难。
根据一些实施例，一种方法包括在包含氢气（H2）和氯化氢（HCl）以作为工艺气体的环境中对硅区域进行退火。在退火步骤之后，从硅区域的表面处生长半导体区域。
根据其他实施例，一种方法包括在低于约870℃的温度条件下对包括硅区域的晶圆进行退火。在退火步骤之前，硅区域的表面具有单台阶。通过退火步骤将单台阶转变为双台阶。在退火步骤之后，从硅区域的表面处生长化合物半导体区域。
在又一些实施例中，一种方法包括在硅衬底中形成STI区域，并且使位于STI区域的两部分之间的一部分硅衬底凹进从而形成凹槽。在形成凹槽的步骤之后，在包括氢气和氯化氢以作为工艺气体的环境中对硅衬底进行退火，其中，在低于约870℃的温度条件下实施退火。在退火步骤之后，从硅衬底的表面处生长化合物半导体区域，其中，硅衬底的表面位于凹槽中。该方法还包括使STI区域形成凹槽，其中，位于STI区域保留部分的顶面上方的部分化合物半导体区域形成半导体鳍。在半导体鳍的侧壁和顶面上形成栅极介电质。在栅极介电质上方形成栅电极。栅极介电质和栅电极形成FinFET的部分。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做出各种不同的改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器装置、制造、材料组分、工具、方法或步骤的特定实施例。作为本领域普通技术人员应理解，根据本发明，可使用现有的或今后开发的与本发明所述的相应实施例执行基本相同的功能或实现基本相同结果的工艺、机器装置、制造、材料组分、工具、方法或步骤。因此，所附权利要求旨在将这些工艺、机器装置、制造、材料组分、工具、方法或步骤包括在它们的范围内。此外，每个权利要求都构成一个独立的实施例，并且不同权利要求及实施例的组合均在本公开的范围之内。

Claims (10)

1.一种方法，包括：
在包括作为工艺气体的氢气（H2）和氯化氢（HCl）的环境中对硅区域进行退火；以及
在所述退火步骤之后，从所述硅区域的表面处生长半导体区域。
2.根据权利要求1所述的方法，其中，在温度介于约700℃和约725℃之间的条件下实施所述退火，并且在所述退火期间，将所述硅区域的单台阶表面转变为双台阶表面。
3.根据权利要求1所述的方法，其中，实施所述退火的时间介于约1分钟和约10分钟之间。
4.根据权利要求1所述的方法，还包括：
在硅衬底中形成浅沟槽隔离（STI）区；以及
使位于所述STI区的两部分之间的所述硅衬底的一部分凹进以形成凹槽，其中，将所述硅区域的表面暴露于所述凹槽，并且从所述凹槽处生长所述半导体区域。
5.根据权利要求4所述的方法，还包括：
使所述STI区凹进，其中，所述半导体区域位于所述STI区的保留部分的顶面上方的部分形成半导体鳍；
在所述半导体鳍的侧壁和顶面上形成栅极介电质；以及
在所述栅极介电质上方形成栅电极，其中，所述栅极介电质和所述栅电极形成鳍式场效应晶体管（FinFET）的一部分。
6.一种方法，包括：
在低于约870℃的温度下对包括硅区域的晶圆进行退火，其中，在所述退火步骤之前，所述硅区域包括具有单台阶的表面，并且通过所述退火步骤使所述单台阶转变为双台阶；以及
在所述退火步骤之后，从所述硅区域的表面处生长化合物半导体区域。
7.根据权利要求6所述的方法，其中，在包括作为工艺气体的氢气（H2）和氯化氢（HCl）的环境中实施所述退火。
8.根据权利要求6所述的方法，还包括：
在所述退火步骤之前，在所述晶圆的硅衬底中形成浅沟槽隔离（STI）区；以及
使所述硅衬底位于所述STI区的两部分之间的部分凹进以形成凹槽，其中，所述硅区域的表面暴露于所述凹槽，并且从所述凹槽处生长所述化合物半导体区域。
9.根据权利要求6所述的方法，还包括：
使所述STI区域凹进，其中，所述化合物半导体区域位于所述STI区域的保留部分的顶面上方的部分形成半导体鳍；
在所述半导体鳍的侧壁和顶面上形成栅极介电质；以及
在所述栅极介电质上方形成栅电极，所述栅极介电质和栅电极形成鳍式场效应晶体管（FinFET）的一部分。
10.一种方法，包括：
在硅衬底中形成浅沟槽隔离（STI）区；
使所述硅衬底位于所述STI区的两部分之间的部分凹进以形成凹槽；
在所述凹进步骤之后，在包括作为工艺气体的氢气（H2）和氯化氢（HCl）的环境中对所述硅衬底进行退火，其中，在温度低于约870℃的条件下实施所述退火；
在所述退火步骤之后，从所述硅衬底的表面处生长化合物半导体区域，其中，所述硅衬底的表面位于所述凹槽中；
使所述STI区域凹进，其中，所述化合物半导体区域位于所述STI区的保留部分的顶面上方的部分形成半导体鳍；
在所述半导体鳍的侧壁和顶面上形成栅极介电质；以及
在所述栅极介电质上方形成栅电极，其中，所述栅极介电质和所述栅电极形成鳍式场效应晶体管（FinFET）的一部分。
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