CN102683192A - 用后期鳍片蚀刻形成于图案化sti区上的鳍式管 - Google Patents

用后期鳍片蚀刻形成于图案化sti区上的鳍式管 Download PDF

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CN102683192A
CN102683192A CN2012100422004A CN201210042200A CN102683192A CN 102683192 A CN102683192 A CN 102683192A CN 2012100422004 A CN2012100422004 A CN 2012100422004A CN 201210042200 A CN201210042200 A CN 201210042200A CN 102683192 A CN102683192 A CN 102683192A
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fins
central part
semiconductor
gate electrode
fin
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CN2012100422004A
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CN102683192B (zh
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P·巴尔斯
R·卡特
F·路德维希
A·卫
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GlobalFoundries Dresden Module One LLC and Co KG
GlobalFoundries Inc
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GlobalFoundries Dresden Module One LLC and Co KG
GlobalFoundries Inc
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

本发明涉及用后期鳍片蚀刻形成于图案化STI区上的鳍式管。在形成精密半导体装置时，通过在早期制造阶段(亦即，在形成浅沟槽隔离时)形成半导体鳍片，可基于取代栅极法及自对准接触组件来形成与平面型晶体管结合的三维晶体管，其中在装设自对准接触组件后以及在取代栅极法期间，可调整该半导体鳍片的最终电性有效高度。

Description

用后期鳍片蚀刻形成于图案化STI区上的鳍式管
技术领域
本揭示内容大体有关于高度精密的集成电路，包括有双栅极或三栅极架构(FinFET)的晶体管组件。
背景技术
先进集成电路(例如，CPU、储存装置、ASIC(特殊应用集成电路)及其类似者)的制造要求根据指定的电路布局在给定的芯片区上形成大量的电路组件，其中场效应晶体管为一种重要的电路组件，其实质决定集成电路的效能。一般而言，目前实施有多种制程技术，其中对于含有场效应晶体管的多种复杂电路，MOS技术是目前最有前途的方法之一，因为由操作速度及/或耗电量及/或成本效率看来，它具有优越的特性。在使用MOS技术制造复杂的集成电路期间，会在包含结晶半导体层的基板上形成数百万个晶体管，例如，n型溝道晶体管与p型溝道晶体管。不论是否考虑n型溝道晶体管，场效晶体管都包含所谓的pn结(pn junction)，其由被称作漏极及源极区的重度掺杂区与轻度掺杂或无掺杂区(例如，经配置成与重度掺杂区毗邻的溝道区)的接口形成。在场效应晶体管中，形成于该溝道区附近以及通过细薄绝缘层而与该溝道区隔开的栅极可用来控制溝道区的导电率，亦即，传导溝道的驱动电流能力。在因施加适当的控制电压至栅极而形成传导溝道后，除其它以外，该溝道区的导电率会取决于掺杂物浓度、电荷载子的迁移率(mobility)、以及对平面型晶体管架构而言，取决于漏极区与源极区之间的距离，此一距离也被称作溝道长度。
由于有实质无限的可用性、已熟悉硅及相关材料和制程的特性、以及50年来累积的经验，目前极大多数的集成电路皆以硅为基础。因此，硅可能仍为可供选择用来设计成可量产未来电路世代的材料。硅在制造半导体装置有主导重要性的理由之一是硅/二氧化硅接口的优越特性，它使得不同的区域彼此之间有可靠的电气绝缘。硅/二氧化硅接口在高温很稳定，从而允许后续高温制程的效能，例如像退火循环(anneal cycle)所要求的，可激活掺杂物及修复晶体损伤而不牺牲接口的电气特性。
基于以上所提出的理由，二氧化硅在场效应晶体管中最好用来作为隔开栅极(常由多晶硅或其它含金属材料构成)与硅溝道区的栅极绝缘层。在场效应晶体管的装置效能稳定地改善下，已持续减少溝道区的长度以改善切换速度及驱动电流能力。由于晶体管效能受控于施加至栅极的电压，该电压使溝道区的表面反转成有够高的电荷密度用以对于给定的供给电压可提供想要的驱动电流，所以必须维持有一定程度的电容耦合(capacitive coupling)，此电容耦合由栅极、溝道区及配置于其间之二氧化硅所形成的电容器提供。结果，减少用于平面型晶体管组态的溝道长度要求增加电容耦合以避免在晶体管操作期间有所谓的短溝道行为。该短溝道行为可能导致漏电流增加以及导致依赖溝道长度的临界电压。有相对低供给电压从而减少临界电压的积极缩小晶体管装置可能面临漏电流的指数增加的问题，同时也需要增强栅极与溝道区的电容耦合。因此，必须对应地减少二氧化硅层的厚度以在栅极与溝道区之间提供必要的电容。由电荷载子直接穿隧通过超薄二氧化硅栅极绝缘层造成的相对高的漏电流可能达相当氧化物厚度在1至2纳米之间的数值，这与效能驱动电路(performance drivencircuit)的要求不一致。
因此之故，已开发出可实作有可能与附加电极材料结合之新栅极介电材料于其中的优异栅电极结构，以便在栅极与溝道区之间提供优异的电容耦合，同时维持低水平的所得漏电流。为此目的，使用所谓的高k介电材料，可视为电介质常数在10.0以上的介电材料。例如，可使用多种金属氧化物或硅酸盐，有可能与习知极薄介电材料结合，以便得到精密高k金属栅电极结构。例如，在一些公认有效的方法中，可基于公认有效之概念来形成平面型晶体管的栅电极结构，亦即，使用习知栅极电介质与多晶硅材料，其中精密材料系统则在极后期制造阶段加入，亦即，在形成任何金属化系统之前以及在用高k介电材料及适当栅极材料取代多晶硅材料来完成基本晶体管组态之后。结果，在任何取代栅极法(replacement gate approach)中，公认有效之制程技术及材料可用来形成基本晶体管组态，同时在后期制造阶段，亦即，在执行任何高温制程后，可加入精密的栅极材料。
有鉴于进一步的装置缩放有可能基于公认有效的材料，已有人提出装设“三维”架构于其中的新型晶体管组态，企图得到想要的溝道宽度同时保持电流流经溝道区的优异可控性。为此目的，已有人提出所谓的FinFET，其中在SOI(绝缘层上覆硅)基板的薄主动层中可形成薄银或硅制鳍片，其中在两个侧壁上，以及若需要在顶面上，可提供栅极介电材料与栅极材料，藉此实现其溝道区可完全空乏化(fullydepleted)的多栅极晶体管。通常，在精密应用中，硅鳍片的宽度约有10至25纳米以及其高度约有30至40纳米。在形成FinFET的有些习知方法中，形成作为长形装置特征的鳍片，接着沉积栅极材料，有可能与任何间隔体结合，之后，通过外延成长硅材料可“融合”鳍片的端部，这可能导致复杂的制程，从而也有可能增加所得漏极/源极区的总外部电阻(overall external resistance)。
请参考图1，此时描述典型习知基于SOI的FinFET以更详细地解释上述问题。
图1的透视图示意图示包含基板101的半导体装置100，例如埋入式绝缘层102已形成于其上的硅基板，然而已将初始硅区或层图案化成多个硅鳍片110，因而可为FinFET晶体管的一部份。如上述，鳍片110有宽度110w与高度110h，以便遵循堆积密度(packing density)及晶体管特性，例如完全空乏及其类似者。此外，栅电极结构160图示成形成于半导体鳍片110上方及其间。栅电极结构160可具有任何适当组态，例如在栅极介电材料、电极材料及其类似者方面。此外，间隔体结构161通常设于栅电极结构160的侧壁上。因此，如上述，在形成栅电极结构160于经图案化之半导体鳍片110上方时，必须应用精密的图案化策略，因为它通常需要蚀刻极其笔直的轮廓同时由半导体鳍片110顶面去除多晶硅材料或大体去除电极材料。此外，也必须可靠地移除在半导体鳍片底部的电极材料，同时也必须移除因对应栅极蚀刻制程之各向异性而暂时形成的任何电极“间隔体”。此外，由于可能需要特别使此高度复杂“三维”蚀刻制程适应于FinFET，因此平面型场效应晶体管通常不可能使用相同的蚀刻制程，从而需要重新设计任何现有电路以避免任何二维晶体管。
如上述，以R表示的外部电阻可能需要适当的接触方案(contactregime)以便提供半导体鳍片的组合式漏极和源极区，这惯例上是通过执行选择性外延成长制程来实现以便融合个别半导体鳍片110的对应端部。以此方式，在融合的漏极和源极区中可形成金属硅化物区域。另一方面，不过，在融合时，对应端部导致在栅极、对应源极/漏极区之间会形成寄生电容器(用C表示)，因为在此不存在栅极-溝道电容。就此情形而言，寄生电容器的所得电容可到达显着的数值，因而会实质影响整体的晶体管特性。
基于这些理由，已做出很大努力以便基于自对准(self-aligned)制造策略来提供FinFET，其中可形成半导体鳍片以便对于栅电极结构可自对准。为此目的，下一步是用复杂微影技术图案化栅极开口以便得到另一个掩模，它则可定义随后基于复杂图案化策略来形成之半导体鳍片的横向位置及尺寸。之后，将适当的介电材料，例如二氧化硅，填入所得结构以便适当地调整先前已予蚀刻之鳍片的电性有效高度。虽然基于这些方法至少可解决与习知基于SOI之FinFET有关的一些上述问题中，然而似乎在进一步装置缩放，特别是在引进精密栅电极结构时，上述图案化顺序可能不再符合任何此类进一步的要求。
例如，在精密半导体装置中，通常用所谓高k介电材料，亦即，电介质常数在10.0以上的介电材料，至少部份取代习知的栅极电介质(例如，基于硅氧化物的材料)，以便提高栅极与溝道区之间的电容耦合，同时不过度增加整体的漏电流。在引进精密高k介电材料时，通常功函数调整(work function adjustment)可能需要加入适当的功函数金属物种，这可能通常也可结合高度导电电极金属的加入。由于对应复杂栅极堆栈的图案化极为困难，所以已开发出精密制造策略，其中形成及保留习知栅电极结构直到基本晶体管结构完成，以及在后面制造阶段，移除占位材料(place holder material)，亦即，多晶硅材料，以及用所欲精密材料系统取代。结果，基于任何此类精密栅电极结构，有可能进一步减少平面型及三维晶体管的特征尺寸。然而结果特别是横向尺寸减少之晶体管的接触变得更加困难，例如在紧密相邻隔开栅电极结构的间距到达100纳米及更小的范围时。就此情形而言，典型接触方案可能不再符合目前可利用的微影及图案化技术，亦即，在栅电极结构之间及上方形成层间介电材料、平坦化材料系统以及执行复杂接触图案化制程以便形成一面连接至漏极和源极区以及另一面连接至栅电极结构的开口。
因此，已开发出“自对准”接触策略，其中对于晶体管长度方向可以自对准的方式提供导电接触材料，例如，通过在层间介电材料中用对于栅电极结构有选择性的移除制程来形成开口。之后，可沉积及平坦化任何适当的导电材料，从而形成连接至漏极和源极区的自对准接触组件。
在精密的制造策略中，自对准接触方案可结合取代栅极法，其中占位材料的实际取代可在装设自对准接触组件后执行。虽然此一方法在进一步减少平面型晶体管之整体尺寸方面极有前途，然而结果是即使可应用精密制造策略，对应策略可能不符合FinFET的形成，如上述。
鉴于上述情形，本揭示内容是有关于数种制造技术及半导体装置，其中可提供有优异晶体管特性的三维晶体管或FinFET，特别是寄生电容，同时避免或至少减少以上所述问题中之一或更多的影响。
发明内容
本揭示内容大体提供数种制造技术及半导体装置，其中基于取代栅极法可提供三维晶体管，也被称为多栅极晶体管或FinFET，其中在早期制造阶段可提供该半导体鳍片，同时通过在取代栅极技术期间形成的栅极开口可实现其电性有效高度的调整。为此目的，可用浅沟槽隔离技术在半导体区中形成该半导体鳍片，其中如有必要，也可形成平面型晶体管的任何其它主动区。以此方式，得到实质平坦的表面形貌供该装置的进一步加工用，从而致能用以形成FinFET晶体管之“二维”制程技术的应用。
在揭示于本文的一些示范具体实施例中，在装设自对准接触组件后，在取代栅极策略期间通过栅极开口来实现半导体鳍片的高度调整，从而致能与高度精密的制造策略有高度的兼容性。以此方式，可减少整体晶体管尺寸，同时在自对准接触组件存在的情形下，漏极和源极区仍有可靠的接触。
揭示于此的一图解说明方法包括下列步骤：在半导体装置之半导体区中形成多个隔离区，其中该多个隔离区在该半导体区中横向划定多个鳍片。该方法更包括：在该半导体区上方形成占位栅电极结构以便覆盖该多个隔离区及鳍片中之每一者的中央部份。另外，该方法包括：在该占位栅电极结构存在的情形下，在该多个鳍片中之每一者中形成漏极和源极区。此外，移除该占位材料以便暴露该多个隔离区及鳍片的中央部份。该方法更包括：在该多个隔离区的该中央部份中选择性地形成凹处以便调整该鳍片之该中央部份的电性有效高度。另外，在该凹处中以及在该鳍片之该中央部份的上方形成栅极介电材料及电极材料。
揭示于此的另一图解说明方法是有关于形成半导体装置。该方法包括：在占位栅电极结构中形成栅极开口，该占位栅电极结构形成在多个鳍片之中央部份上方，该多个鳍片接着形成于半导体区中并且用隔离区横向隔开。该方法更包括：通过该栅极开口，在该隔离区中之每一者的中央部份中形成空腔，以便调整该多个鳍片的电性有效高度。另外，该方法包括：在该空腔及该栅极开口中形成栅极介电材料与电极材料。
揭示于此的另一图解说明半导体装置包括：包含用隔离区隔开之多个鳍片的半导体区，其中该隔离区中之每一者有下凹中央隔离部份。该半导体装置更包含：高k金属栅电极结构，其形成于该多个鳍片之中央部份上方及该下凹中央隔离部份上方。此外，一漏极区形成于该多个鳍片中之每一者中以便连接至该中央部份，以及源极区形成于该多个鳍片中之每一者中以便连接至该中央部份。此外，第一自对准接触组件形成于该漏极区中之每一者上方以及于该隔离区上方。另外，第二自对准接触组件形成于该源极区中之每一者上方以及于该隔离区上方。
附图说明
本揭示内容的其它具体实施例皆定义于随附权利要求中，在阅读以下详细说明时参考附图可更加明白这些具体实施例。
图1的透视图示意图示习知基于SOI的FinFET晶体管；
图2a根据示范具体实施例示意图示数个半导体区的上视图，其中有一半导体区包含用隔离区隔开的多个半导体鳍片；
图2b示意图示穿过该半导体鳍片之中央部份及隔离区的横截面图；
图2c示意图示该半导体装置处于可提供占位栅电极结构之更进一步制造阶段的上视图；
图2d根据示范具体实施例示意图示沿着晶体管宽度方向穿过占位栅电极结构的横截面图；
图2e至2i根据示范具体实施例示意图示该半导体装置在形成平面型及三维晶体管之漏极和源极区的不同制造阶段期间的横截面图；
图2j及2k根据示范具体实施例分别示意图示该半导体装置处于提供自对准接触组件之更进一步制造阶段的上视图与横截面图；
图2l及2m根据示范具体实施例示意图示该半导体装置处于更进一步制造阶段的上视图，此时调整该半导体鳍片的电性有效高度以及提供精密栅极材料；以及
图2n及2o根据示范具体实施例示意图示该FinFET或多栅极晶体管在完成取代栅极制程顺序之后的横截面图。
具体实施方式
尽管用如以下详细说明及附图所图解说明的具体实施例来描述本揭示内容，然而应了解，以下详细说明及附图并非旨在揭示于本文的专利标的受限于所揭示的特定示范具体实施例，而是所描述的具体实施例只是用来举例说明本揭示内容的各种方面，本发明的范畴系由随附的权利要求定义。
本揭示内容大体考虑数种制造技术及半导体装置，其可以自对准方式装设多栅极晶体管(亦即，对于栅电极结构自对准)，也可被称为FinFET，或大体上任何非平面型晶体管组态，此通过在早期制造阶段形成这些半导体鳍片，同时提供平面型表面形貌，然而在后期制造阶段(亦即，在形成取代栅电极结构时)实现调整这些半导体鳍片(亦即，其中央部份)的电性有效高度。结果，使用“二维”晶体管制造策略可实现基本晶体管特性，例如根据整体装置要求，例如在加入适当半导体合金、加入应变诱发机构及其类似者方面，来形成漏极和源极区，从而致能平面型晶体管的同时制造。因此，在精密半导体装置中，可有效率地再利用与基于平面型晶体管所形成之关键性较低电路部份有关的公认有效电路布局，同时可基于三维晶体管来形成任何效能关键性电路。通过基于STI技术来形成半导体鳍片，所得鳍片可被视为平面型晶体管的窄主动区，它们被对应鳍片隔离区适当地隔开，藉此可确保与二维制造技术有想要的兼容性。不过，在取代栅极制程顺序期间，通过提供适当蚀刻掩模，可不同地处理这些三维晶体管，以便考虑到这些鳍片隔离区的受控式下凹，从而调整这些半导体鳍片之中央部份的有效栅极高度。结果，直到此制造阶段达成后，可应用任何想要的制造策略，例如在执行取代栅极法之前加入自对准接触组件，藉此确保整体制程顺序的可扩展性(scalability)，因为自对准接触方案可能允许进一步减少晶体管的整体横向尺寸。
请参考图2a至2p，此时更详细地描述其它的示范具体实施例，其中也可适时参考图1。
图2a的上视图示意图示处于早期制造阶段的半导体装置200。如图示，在半导体层中可通过形成隔离结构203c(可装设成浅沟槽隔离的形式)来横向划定第一半导体区203a与第二半导体区203b。此外，接着可把半导体区203a分成可用对应隔离区203f横向隔开的多个“子区”，它们也被称作半导体鳍片210。因此，鳍片210可为长形半导体区，其横向尺寸取决于中间隔离区203f与半导体区203a的整体横向尺寸，接着用隔离区203c定义大小、形状及位置。应了解，半导体鳍片210的深度因而取决于隔离区203c、203f的深度或厚度。例如，基底半导体层可为其中结晶基板材料之上半部可用作半导体基材的块体组态。就此情形而言，半导体鳍片210可直接连接至结晶基板材料，其中形成沟槽隔离结构203c、203f。
图2b示意图示沿着图2a之直线IIb绘出的横截面图，亦即，沿着隔离区203f及半导体鳍片210的中央部份210c、203m(参考图2a)。如图示，装置200可包含基板201，它可为用以形成半导体层203于其上或上方的任何适当载体材料，若为块体组态，它可直接连接至结晶基板材料。应了解，在图示的制造阶段中，半导体层203不再是连续半导体材料而被分成数个适当的半导体区，如图2a所示。此外，在其它的示范具体实施例(未图示)中，可装设埋入式绝缘材料于半导体层203下方，如果认为适合进一步加工及整体装置特性的话。此外，如图示，半导体鳍片210延伸穿过半导体层203以及用隔离区203f、203c横向隔开。
如图2a及2b所示的半导体装置200可基于以下的制程技术来形成。半导体区203a、203b可基于公认有效之STI(浅沟槽隔离)技术来形成，亦即，利用适当的微影技术，有可能结合第二微影掩模以便具体定义区域203f的横向尺寸、位置及形状。在其它情形下，区域203f可用个别的图案化顺序来形成，如果认为适当的话。因此，可应用公认有效之蚀刻及沉积技术，接着是平坦化制程及退火技术，如有必要。因此，可得到用于主动区203a、203b及隔离区203f、203c的实质平坦表面形貌。
图2c示意图示处于更进一步制造阶段的半导体装置200，其中可装设多个栅电极结构260以便符合整体装置要求。例如，根据设计规则，在半导体区203b、203a上方可实作栅电极结构260之间的最小间距。栅电极结构260可为占位栅电极结构因而可包含占位材料262，例如多晶硅材料及其类似者，以及任何其它材料，例如间隔体结构261。
图2d示意图示沿着图2c之直线IId绘出的横截面图。如图示，栅电极结构260可包含占位材料262，有可能结合蚀刻终止材料，例如形式为二氧化硅及其类似者，如有必要。此外，可装设电介质覆盖层264或覆盖层系统，例如形式为氮化硅材料、二氧化硅及其类似者。如图2c及2d所示的装置可基于任何适当制造策略来形成，其中可形成栅电极结构260以便符合整体装置要求。亦即，基于设计准则来调整栅极长度与栅电极结构的间距。为此目的，可应用精密微影技术，例如双重曝光及双重图案化硬掩模材料，以便得到栅电极结构260的所欲横向尺寸。此外，可形成间隔体结构261以便符合装置200的进一步加工。为此目的，可沉积及图案化适当材料，例如氮化硅，二氧化硅及其类似者，以便形成间隔体结构261。此外，在该进一步加工期间，可形成漏极和源极区于半导体鳍片210中以及于区域203中，从而致能应用任何“二维”制造策略。例如，可应用与相关掩模方案结合的适当注入技术以便依照定义整体晶体管特性所要求的，加入任何掺杂物种。同样，可将应变诱发半导体合金加进晶体管组件中之至少一些，例如通过在半导体区中形成空腔，亦即，在半导体鳍片210的端部以及半导体区203a的暴露区以及用适当半导体合金(例如硅/锗、硅/锡、硅/锗/锡、硅/碳及其类似者)填充空腔。再者，漏极/源极区可基于经原位(in-situ)掺杂的外延成长半导体材料来形成，然而在其它情形下，可提供有优异导电率的半导体合金，例如形式为硅/磷合金及其类似者。再者，例如在n型溝道晶体管中，如果认为适当的话，可应用应变记忆技术(strain memorization technique)，以便增强整体晶体管效能。应了解，在任何制程技术中，可应用相同或不同的制程参数，例如通过适当地掩模二维晶体管或三维晶体管，这取决于所欲的最终晶体管特性。例如，在用选择性外延成长技术形成半导体材料时，可用适当硬掩模材料掩模某些装置区。同样，可应用适当注入掩模以便按需要引进任何适当的掺杂物种。
图2e示意图示处于更进一步制造阶段的半导体装置200。应了解，该横截面是沿着图2c的直线IIe绘出。结果，晶体管250a的形式可为包含漏极和源极区251a的单一半导体鳍片210，漏极和源极区251a因而对应至鳍片210的各个端部，同时被中央栅电极结构260覆盖的中央部份210c因而实质对应至晶体管250a的溝道区。另一方面，晶体管250b可包含漏极和源极区251b，漏极和源极区251b因而可为沿着晶体管宽度方向的连续漏极和源极区，亦即，沿着垂直于和2e之图纸平面的方向。如前述，漏极和源极区251a可基于多个制程技术来形成，例如通过加入半导体合金或通过提供外延成长半导体材料，如编号252所示，例如通过在中央部份210c中诱发应变及/或以便加入掺杂物种，例如p型掺杂物种或n型掺杂物种及其类似者。如上述，对于晶体管250a、250b，可应用不同的对应制造技术，如果认为适当的话。
图2f及2g示意图示三维晶体管的横截面图，其中可应用特别设计的制程顺序以便适当地调整漏极和源极区的特性。
图2f示意图示装置200的横截面图，其中，为求方便，只图示中央栅电极结构260。此外，图2f的左手边为n型溝道晶体管250a，它可包含漏极或源极区251n，例如基于有高n型掺杂物浓度的外延成长硅材料形成者。此外，可提供反向掺杂区或晕圈区域(halo region)，用编号252n表示，以便调整整体晶体管特性。同样，在右手边，晶体管250a的横截面可为p型溝道晶体管，例如，它可包含形式为硅/锗合金的应变诱发高度p型掺杂半导体合金以便在中央区或溝道区210c诱发压缩应变分量。例如，p型溝道晶体管250a的漏极和源极区251p基本上可用加入半导体合金的大小及形状与其原位掺杂物浓度来定义。此外，可装设对应反向掺杂区252p或晕圈区域以便符合整体要求。应了解，漏极和源极区251n、251p的组态可对应至典型二维晶体管组态因而可实作成二维晶体管，例如如图2e所示的晶体管250b。为了更适当地符合三维组态，例如相对于晕圈区域252n、252p，可应用额外的修改。
图2g示意图示对应组态，其中可执行附加的浅注入，例如通过适当地掩模二维晶体管，如上述，从而在适当地调整半导体鳍片210的有效电性高度后，得到包含对应“包覆物(wrap around)”的修改晕圈区域252n、252p。亦即，在图2g的制造阶段中，栅电极结构260已经为高k金属栅电极结构，它可基于取代栅极制程顺序来形成，在该取代栅极制程顺序期间也可调整鳍片210的有效高度，下文会有更详述的描述。
图2h及2i根据其它示范具体实施例示意图示晶体管250a的横截面图。
图2h示意图示在左手边的部份n型溝道晶体管250a以及在右手边的部份p型溝道晶体管250a。例如，可以高度掺杂埋入式半导体材料(例如，形式为硅材料、硅/碳材料)的形式提供n型溝道晶体管250a的漏极和源极区251n，藉此也可使用想要的拉伸应变及其类似者。在其它情形下，可用选择性外延成长技术来加入硅/磷半导体合金。结果，可用加入的高度掺杂半导体材料或合金实质定义漏极和源极区251n。此外，在形成用以加入原位掺杂半导体材料的空腔时，可适当地调整深度以便实质对应至半导体鳍片210的有效电性高度。
同样，通过适当地形成空腔及加入原位掺杂半导体材料，形式有可能为应变诱发硅/锗合金及其类似者，可调整p型溝道晶体管250a的漏极和源极区251p。为此目的，可应用适当蚀刻制程，其中，如有必要，可用适当硬掩模材料或阻剂材料掩模二维晶体管以及可应用常用于p型溝道晶体管及n型溝道晶体管的空腔蚀刻制程，藉此确保高度均匀的所得深度以及空腔的形状及大小。之后，可应用适当硬掩模方案以便依序形成分别用于n型溝道晶体管、p型溝道晶体管的材料251n、251p。为此目的，可应用公认有效之选择性外延成长技术。
图2i示意图示该装置处于更进一步制造阶段的横截面图，其中栅电极结构260为高k金属栅电极结构，同时也调整半导体鳍片210的电性有效高度，它因而可各自实质对应至漏极和源极区251n、251p的深度。结果，以此方式，可用基本二维制造技术来调整适当晶体管特性以及适当地改写制程参数以便符合三维晶体管组态。以此方式，可达成优异晶体管效能，藉此即使相较于极精密的二维晶体管，也可提供优异特性，不论是否需要任何新开发的制程技术。例如，可事前决定应变诱发机构的影响、漏极/源极区的优异掺质分布及其类似者，然后可选择性地应用于三维组态以便适当地调整晶体管特性。以此方式，对于基本半导体主动区的给定横向尺寸，利用三维组态可得到优异的可控性以及大体优异的晶体管效能，同时二维晶体管可用于关键性较低的电路部份。
图2j示意图示半导体装置200处于更进一步制造阶段的上视图。如图示，数个自对准接触组件225设于晶体管250a、250b中。自对准接触组件225可由任何适当导电材料构成，其符合该装置的进一步加工。亦即，在有些示范具体实施例中，相对于占位材料262及隔离区203f的材料(参考图2a)，接触225或至少其表面层可提供蚀刻终止特性，在后面制造阶段，相对于自对准接触组件225，可能必须选择性地蚀刻接触225。在有些示范具体实施例中，组件225可包含氮化钛材料，至少在其顶面，因为氮化钛对于任何氧化物蚀刻处方有高度抵抗力，从而使得隔离区在后面制造阶段能够有效地下凹。此外，氮化钛对于用以在取代栅极法期间移除多晶硅材料的多个蚀刻化学也有高度选择性。
图2k示意图示半导体装置200沿着图2c之直线IId绘出的横截面图。如图示，可提供部份的接触层(contact level)220，例如形式为蚀刻终止衬里(etch stop liner)221，例如氮化硅材料，结合另一介电材料，例如二氧化硅及其类似者。此外，自对准接触组件可横向装设于栅电极结构260之间，如以上在说明图2j时所述。因此，接触组件225横向都被间隔体结构261及其余的蚀刻终止层221约束。
此外，在有些示范具体实施例中，在漏极和源极区251a、251b可装设适当接触区254，例如形式为硅化镍，硅化镍铂及其类似者。
如图2k所示的半导体装置200可基于以下制程来形成。在完成漏极和源极区251a、251b及施加任何高温制程(如有必要)后，可沉积介电材料221、222，例如用电浆增强CVD技术与旋涂技术(spin-ontechnique)及其类似者，有可能结合附加低温退火制程。之后，例如用CMP、蚀刻及其类似者，可移除多余材料，其中最后可曝光占位材料262，亦即，可曝光其顶面262s。在此制造阶段中，可提供适当掩模以定义自对准接触组件225在垂直于图2k之图纸平面的方向的横向延伸。为此目的，可使用任何适当掩模材料，例如阻剂、硬掩模材料及其类似者。基于此一蚀刻掩模，可蚀刻材料222从而可由在栅电极结构260之间的空间去除，其中该蚀刻制程对于材料262有选择性，同时在底部空间的蚀刻终止衬里221可用来控制该蚀刻制程。之后，可开放终止衬里材料221以便暴露漏极和源极区251a、251b。在移除蚀刻掩模后，可用自对准方式形成接触区254，例如基于硅化技术，接着沉积适当导电接触材料，例如形式为钨，也与氮化钛、钛及其类似者结合。例如，可应用公认有效基于钨之沉积技术，如果认为钨适合进一步加工装置200的话。在有些示范具体实施例中，可提供形式为氮化钛材料的导电材料，它有较高的电阻，不过，可提供优异的蚀刻终止特性。此外，由于接触组件225有相对大的面积以及减少的高度，基于氮化钛所得到的整体接触电阻率符合整体装置要求。之后，例如用CMP，可移除任何多余材料，藉此提供暴露表面区域262s。
接下来，占位材料262的移除可基于选择性蚀刻处方，例如TMAH(四甲基氢氧化铵)，它对于二氧化硅、氮化硅、氮化钛及其类似者有极高选择性地可有效蚀刻硅。该蚀刻制程可终止于介电材料263上或中。
图2l的上视图示意图示处于更进一步制造阶段的半导体装置200。如图示，可提供蚀刻掩模205以覆盖着晶体管250b同时暴露部份晶体管250a从而先前在移除占位材料时形成栅极开口260o之至少一部份。因此，在栅极开口260o内，除了层263的残留物(如果在此阶段仍有的话)以外，可各自暴露半导体鳍片210及隔离区203f的中央部份210c、203m。应了解，取决于蚀刻掩模205的整体尺寸，也可用部份形成于晶体管250a上方的其它栅电极结构来暴露这些区域的端尖。蚀刻掩模205的形式可为任何适当掩模材料，例如阻剂材料，有可能结合光学平坦化材料及其类似者。之后，可执行蚀刻制程以便选择性地移除隔离区203f的材料，为此可利用公认有效之电浆辅助蚀刻处方，可实现对于硅、氮化硅及自对准接触组件225的材料(例如，氮化钛)有高度的选择性，这可藉由在蚀刻制程期间初始化一定程度的聚合(polymerization)来实现。结果，在此蚀刻制程期间，使隔离区203f的中央部份203m下凹，其中下凹的深度因而决定半导体鳍片210之邻近中央部份210c的电性有效高度。由于用于移除二氧化硅的高度可控制蚀刻制程是公认有效的，因此对于鳍片高度，可达成高度的均匀性。接下来，可移除任何蚀刻残留物，例如基于二亚胺(N2H2)，藉此避免应用常在电浆辅助蚀刻制程后用来移除任何聚合物残留物的高度反应性蚀刻化学。以此方式，可保留自对准接触组件225的完整性。此外，可应用附加清洗制程，例如基于臭氧及其类似者，而不会使任何暴露材料(例如，硅、二氧化硅、氮化硅、氮化钛及其类似者)劣化。同时，在任何暴露硅表面区域上可形成化学氧化物，藉此在沉积高k介电材料之前提供基底氧化物(base oxide)用以增强接口特性。之后，可沉积高k介电材料于各个栅极开口260o内，接着可图案化精密的任何适当功函数金属以便各自形成对应功函数金属或p型溝道晶体管与n型溝道晶体管，接着沉积高度导电电极金属，例如铝、铝合金及其类似者。为此目的，可应用公认有效之取代栅极制造策略。最后，可移除任何多余材料，例如用CMP及其类似者，藉此形成被电性隔离的高k金属栅电极结构。
图2m的上视图示意图示取代栅极制程顺序之后的晶体管250a。如图示，栅电极结构260可包含与适当功函数金属267结合的高k介电材料266和高度导电电极金属268。
图2n示意图示中央栅电极结构260的横截面图，其中横截面图系穿过其中一个隔离区203f绘出。如图示，在取代栅极制程顺序期间，在蚀刻制程期间已用蚀刻掩模205(参考图2l)使隔离区203f的中央部份203m下凹，其中以203r表示的凹陷程度因而可定义在垂直于图2n之图纸平面的方向与隔离区203f紧邻地形成的半导体鳍片之电性有效高度。因此，栅电极结构260延伸进入隔离区203f因而形成于下凹部份203m上以及包含高k介电材料266，功函数金属物种267及高度导电电极金属268。应了解，取决于所应用的制程顺序，用于n型溝道晶体管与p型溝道晶体管的组态可不同。亦即，如有必要，可形成两个或更多特定层于介电层266上。
如以上在说明图1时所述，在晶体管250a中，由于栅电极结构260连接至隔离区203f，所以大体实质完全避免寄生电容C，此寄生电容C于习知三维晶体管中通常出现于融合漏极和源极接触与在没有栅极-溝道电容之区域中的栅电极结构连接的部份。结果，相较于习知三维晶体管架构，所得寄生电容实质等于零因而可提供优异的效能特性。
图2o的剖面图示意图示图2m的剖面IIo。如图示，半导体鳍片210中之每一者的电性有效高度210h取决于隔离区203f的凹陷程度203r。
基于如图2m至2o所示的晶体管组态，按需要，通过形成适当互连结构以便连接至自对准接触组件225以及至栅电极结构260(参考图2m)，从而可继续该加工。为此目的，可施加适当介电材料(例如，二氧化硅)，有可能结合作为蚀刻终止材料的氮化硅，以及可加以图案化以便形成对应开口，因而可连接至接触225及栅电极结构260。之后，可填入与适当阻障材料结合的任何适当材料，例如高度导电的铜基材料，藉此致能对应互连结构的大幅窄化，这在进一步减少装置200的整体横向尺寸时可能会要求。应了解，可应用任何适当互连方案，例如适当硬掩模材料的双重曝光/图案化。
结果，本揭示内容在三维晶体管或多栅极晶体管中可提供数种半导体装置及制造技术以及可基于取代栅极法来形成，接着可应用它以便致能自对准接触组件的装设。为此目的，在早期制造阶段可基于STI技术来形成半导体鳍片，藉此可提供实质平坦的表面形貌，这使得能够应用任何想要的二维制程技术。结果，可与三维晶体管同时地形成任何平面型晶体管，同时另外可施加任何特定修改，例如在形成漏极和源极区时，如果认为适当的话。在取代栅极法期间以及在形成自对准接触组件之后，可有效地调整最终电性有效高度。
熟谙此艺者基于此说明可明白本揭示内容的其它修改及变体。因此，此说明应只被视为仅供图解说明用而且目的是用来教导熟谙此艺者实施本文提供之教导的一般方式。应了解，应将图示及描述于本文的专利标的之形式被视为目前为较佳的具体实施例。

Claims (20)

1.一种方法，包含下列步骤：
在半导体装置的半导体区中形成多个隔离区，该多个隔离区在该半导体区中横向划定多个鳍片；
在该半导体区上方形成占位栅电极结构，该占位栅电极结构覆盖该多个隔离区及鳍片中的每一者的中央部份；
在该占位栅电极结构存在的情形下，在该多个鳍片中的每一者中形成漏极和源极区；
移除该占位材料以便暴露该多个隔离区及鳍片的该中央部份；
在该多个隔离区的该中央部份中选择性地形成凹处以便调整该鳍片的该中央部份的电性有效高度；以及
在该凹处中以及在该鳍片的该中央部份的上方形成栅极介电材料及电极材料。
2.如权利要求1所述的方法，还包含下列步骤：在取代该占位材料之前形成横向毗邻该占位栅电极结构的接触组件以便连接至该漏极和源极区。
3.如权利要求2所述的方法，其中形成该接触组件的步骤包括：提供对于该占位材料及该多个隔离区的材料有蚀刻终止特性的导电接触材料。
4.如权利要求3所述的方法，其中该导电接触材料经装设成有包含氮化钛的暴露表面。
5.如权利要求1所述的方法，其中形成该漏极和源极区的步骤包括：在该占位材料存在的情形下，沉积掺杂半导体材料。
6.如权利要求5所述的方法，还包含下列步骤：在该多个鳍片中形成凹处以及至少在该凹处中形成该掺杂半导体材料。
7.如权利要求6所述的方法，其中形成该掺杂半导体材料的步骤包括：形成应变诱发半导体合金。
8.如权利要求1所述的方法，其中选择性地在该多个隔离区的该中央部份中形成凹处的步骤包括：执行电浆辅助蚀刻制程以及用氧化化学法移除该电浆辅助蚀刻制程的聚合物副产品，以便在该多个鳍片的该中央部份的暴露表面区域上形成氧化物层。
9.如权利要求1所述的方法，还包含下列步骤：形成第二隔离区以便横向划定具有横向尺寸大于该多个鳍片中的每一者的横向尺寸的连续半导体区，其中该方法更包含下列步骤：在该连续半导体区中及上方形成平面型晶体管。
10.如权利要求9所述的方法，还包含下列步骤：在该多个鳍片中的每一者中形成该凹处之前，掩模该连续半导体区及该第二隔离区。
11.一种形成半导体装置的方法，该方法包含下列步骤：
在占位栅电极结构中形成栅极开口，该占位栅电极结构形成在多个鳍片的中央部份上方，该多个鳍片形成于半导体区中以及用隔离区横向隔开；
通过该栅极开口，在该隔离区中的每一者的中央部份中形成空腔，以便调整该多个鳍片的电性有效高度；以及
在该空腔及该栅极开口中形成栅极介电材料与电极材料。
12.如权利要求11所述的方法，还包含下列步骤：在形成该栅极开口之前，形成横向毗邻该占位栅电极结构的导电接触材料。
13.如权利要求11所述的方法，其中形成该导电接触材料的步骤包括：至少在该导电接触材料的表面上，提供对于占位材料及该隔离区的蚀刻终止特性。
14.如权利要求13所述的方法，其中该导电接触材料至少在其表面包含氮化钛。
15.如权利要求11所述的方法，还包含下列步骤：在形成该栅极开口之前，在该多个鳍片中的每一者中形成漏极区与源极区。
16.如权利要求15所述的方法，其中形成漏极和源极区的步骤包括选择性地沉积掺杂半导体材料。
17.如权利要求16所述的方法，其中形成该漏极和源极区的步骤包括：在该多个鳍片中的每一者中形成漏极和源极空腔以及用原位掺杂半导体材料填充该漏极和源极空腔。
18.一种半导体装置，包含：
包含用隔离区隔开的多个鳍片的半导体区，该隔离区中的每一者有下凹中央隔离部份；
高k金属栅电极结构，其形成于该多个鳍片的中央部份上方及该下凹中央隔离部份上方；
漏极区，其形成于该多个鳍片中的每一者中以便连接至该中央部份；
源极区，其形成于该多个鳍片中的每一者中以便连接至该中央部份；
第一自对准接触组件，其成于该漏极区中的每一者上方以及于该隔离区上方；以及
第二自对准接触组件，其形成于该源极区中的每一者上方以及于该隔离区上方。
19.如权利要求18所述的半导体装置，还包含横向尺寸大于该多个鳍片中的每一者的横向尺寸的第二半导体区，其中该第二半导体区包含连续漏极和源极区与连接至该连续漏极和源极区的自对准接触组件。
20.如权利要求18所述的半导体装置，其中该第一及该第二自对准接触组件至少在其顶面包含含钛及氮化物的接触材料。
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