CN107611029B - 利用工程掺质分布具有超陡逆行井的方法、设备及系统 - Google Patents

利用工程掺质分布具有超陡逆行井的方法、设备及系统 Download PDF

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CN107611029B
CN107611029B CN201710564163.6A CN201710564163A CN107611029B CN 107611029 B CN107611029 B CN 107611029B CN 201710564163 A CN201710564163 A CN 201710564163A CN 107611029 B CN107611029 B CN 107611029B
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doped region
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dopant
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CN107611029A (zh
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大卫·保罗·波路柯
J·B·约翰逊
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GlobalFoundries US Inc
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Abstract

本发明涉及利用工程掺质分布具有超陡逆行井的方法、设备及系统，大体上，在一项具体实施例中，本发明针对一种用于形成晶体管的方法。本方法包括：布植衬底以形成n与p掺杂区其中至少一者；于该衬底上方沉积外延半导体层；穿过该外延层并且部分穿过n与p掺杂区其中至少一者形成沟槽；于该沟槽中形成介电隔离区；通过使该介电隔离区部分凹陷而在该外延半导体层的上部分中形成鳍片；形成与该鳍片的至少两个表面相邻的栅极介电质；以及使掺质从该n与p掺杂区其中至少一者至少部分扩散到该外延半导体层内，以形成与该鳍片的底端部分相邻的扩散掺杂移转区。

Description

利用工程掺质分布具有超陡逆行井的方法、设备及系统
技术领域
本发明大体关于尖端半导体装置的制造，并且更具体地说，关于利用工程掺质分布具有超陡逆行井的各种方法与结构。
背景技术
制造产业技术爆发已导致许多新式与创新的制造程序。现今的制造程序需要大量重要步骤，尤其是半导体制造程序。这些程序步骤通常需要大体上经过微调以维持适当制造控制的若干输入。
制造半导体装置需要若干离散程序步骤，用以从裸半导体材料开始建立已封装半导体装置。从半导体材料初始生长、半导体晶体切片成个别晶圆、制作阶段(蚀刻、掺杂、离子布植或类似者)到已完成装置封装与最终测试等各个程序，彼此间有很大的差异且各有专门用途，因此，可在含有不同控制方案的不同制造位置进行此等程序。
大体上，一组处理步骤使用诸如曝照工具或步进机的半导体制造工具，在有时称为一批的一半导体晶圆群组上进行。举一实施例来说，可在半导体晶圆上进行蚀刻程序以在半导体晶圆上塑形对象，诸如多晶硅线路，其各可作用为晶体管的栅极电极。举另一实施例来说，可形成多条金属线，例如：铝或铜，作用为将半导体晶圆上的一个区域连接至另一者的导线。
按照这种方式，可制作集成电路芯片。在一些情况下，集成电路或芯片可包含基于硬写码的程序而一起运作的各种装置。举例而言，特定应用集成电路(ASIC)芯片可将硬写码的程序用于各种操作，例如：启动与组配程序。将该程序代码以二进制数据形式硬写码到集成电路芯片内。
在设计具有集成电路(例如：CMOS逻辑架构)的各种装置的布局时，设计人员通常选择包含各种特征(例如：扩散区、晶体管、金属线、贯孔等)的预先设计功能胞元，并且策略性地置放这些功能胞元以提供集成电路的主动区。设计布局的一项挑战为容纳日益增加的胞元组件密度，并且依然维持路由安排能力以供连接该等胞元的各种组件。随着这些组件的尺寸愈来愈小，诸如10nm或更小的集成电路设计，此挑战愈来愈显著。
预先设计功能胞元通常用于设计晶体管，诸如金属氧化物场效晶体管(MOSFET或FET)。FET是一种装置，其典型包括源极区、漏级区、置于该源极区与该漏级区之间的通道区以及置于该通道区上面的栅极电极。流经FET的电流通过控制施加至栅极电极的电压来控制。若对栅极电极施加比装置的临限电压更小的电压，则没有电流流经装置(略去非所欲的漏电流，其相对较小)。然而，对栅极电极施加比装置的临限电压相等或更大的电压时，信道区变为具有导电性，并且允许电流穿过导电通道区在源极区与漏级区之间流动。
为了提升FET的运作速度，并且增加集成电路装置上FET的密度，装置设计者多年来已大幅缩减FET的实体尺寸。更具体地说，FET的通道长度已显著缩减，已使FET的切换速度获得提升。然而，缩减FET的通道长度亦缩减源极区与漏级区之间的距离。在某些情况下，源极与漏级之间的间隔如此缩减而造成难以使通道的电位有效免于遭受漏级电位负面影响。这有时称为所谓的短通道效应，其中FET作为主动开关的特性会降低。
FET实质有两种类型：平面型FET及所谓的3D装置，诸如说明性finFET装置，其是一种3维结构。更具体地说，在finFET中，形成大体上垂直而置的鳍形主动区，而且栅极电极将鳍形主动区的侧边及上表面两者都包围，用以形成三栅结构，为的是要使用具有3结构而非平面结构的信道。在一些情况下，绝缘覆盖层(例如：氮化硅)置于鳍片的顶端，并且finFET装置仅具有双栅结构。
FinFET设计使用可使用选择性蚀刻程序在半导体晶圆的表面上形成的“鳍片”。鳍片可用于在晶体管的源极与漏级之间形成通道。接着沉积栅极，使得其环绕鳍片以形成三栅结构。由于通道极薄，栅极对里面的载子一般会具有更大的控制。然而，当晶体管切换为接通时，通道的小尺寸可限制电流的流动。因此，可平行使用多个鳍片以提供更大的电流流动使驱动强度提升。
图1绘示习知finFET装置的特写图。图1所示的finFET装置100包含多个“鳍片”110。该半导体装置可顺着垂直取向安置，建立一或多个鳍片110。该finFET的源极与漏级沿着鳍片水平置放。高k金属栅极120环绕于鳍片上方，将其三个侧边包覆。栅极120界定finFET装置的长度。顺着与半导体晶圆的平面平行的方向沿着正交晶面出现电流流动。鳍片的电气有效高度(标示为H)典型为通过鳍片显露步骤中的氧化物凹陷量来测定，因此，所有鳍片110都实质类似。
鳍片的厚度(标示为Tfi)判定晶体管装置的短信道行为，并且通常比鳍片110的高度H还小。鳍片的间距(标示为P)通过微影限制条件来测定，并且指定要实施所欲装置宽度的晶圆区。若间距P值小且高度H值大，则能实现每平方面积的所欲装置堆积，导致设计更稠密，或硅晶圆区使用更有效率。对于块材finFET，信道下方的区域称为井体，并且与源极和漏级掺杂的极性相反。对于pMOS装置，井体为n型掺杂，并且称为n型井。对于nMOS装置，井体为p型掺杂，并且称为p型井。各井体类型的紧密位于通道下方的上部区通常称为冲穿终止(PTS)区，并且作用在于当finFET处于断开状态时，使不希望的电流在源极与漏级区之间的流动受限。
集成电路缩小外加对于这些电路的更高效能要求已促使提升对finFET的关注。FinFET大体上具有增大的有效通道宽度，其包括鳍片的侧壁与顶端部分上形成的通道部分。由于finFET的驱动电流与信道宽度成比例，finFET大体上显示驱动电流能力上升。
FinFET装置已知为包括通常称为超陡逆行井(Super Steep Retro grade Well；SSRW)的掺质分布。一般而言，在运用SSRW的finFET中，希望通道本身不具有掺杂或具有低掺杂，并且紧密位于通道下面的PTS区域为适度掺杂。这种结构类型中，PTS典型为通过布植通过通道的掺质所形成。通道中希望没有掺杂或有低掺杂，以使随机掺杂扰动(RandomDopant Fluctuation；RDF)及其对VT的影响降到最小。然而，与PTS掺质相关联的植入物蔓延通常导致通道中留下大量掺质，这可能会造成问题，并且可能造成finFET装置中非所欲的电气特性。不想要的布植后掺质扩散也可能使finFET装置退化。
本发明可因应及/或至少减少以上指认的其中一或多个问题。
发明内容
以下介绍本发明的简化概要，以便对本发明的一些态样有基本的了解。本概要并非本发明的详尽概述。用意不在于指认本发明的重要或关键要素，或叙述本发明的范畴。目的仅在于以简化形式介绍一些概念，作为下文更详细说明的引言。
大体上，在一项具体实施例中，本发明针对一种用于形成晶体管的方法。本方法包括：布植衬底以形成n与p掺杂区其中至少一者；于该衬底上方沉积外延半导体层；穿过该外延层并且部分穿过n与p掺杂区其中至少一者形成沟槽；于该沟槽中形成介电隔离区；通过使该介电隔离区部分凹陷而在该外延半导体层的上部分中形成鳍片；形成与该鳍片的至少两个表面相邻的栅极介电质；以及使掺质从该n与p掺杂区其中至少一者至少部分扩散到该外延半导体层内，以形成与该鳍片的底端部分相邻的扩散掺杂移转区。
大体上，在第二具体实施例中，本发明针对finFET晶体管。该晶体管由衬底、鳍片、子鳍片区以及适度掺杂区所构成。该衬底具有n掺杂区与p掺杂区其中至少一者。该鳍片具有低掺杂通道区。该子鳍片区包括居于该衬底与该鳍片的通道中间的掺质扩散抑制材料，以及该适度掺杂区位于该掺质扩散抑制材料下方。
附图说明
本发明可搭配附图参照以下说明来了解，其中相似的附图标记表示相似的组件，并且其中：
图1绘示习知finFET装置的描绘；
图2至5绘示用于产生finFET装置的第一具体实施例的一连串程序步骤的特写图；
图6就finFET装置的一具体实施例，绘示电气数据的例示性图标；以及
图7根据本文中的具体实施例，绘示用于制作包含finFET装置的半导体装置的系统的特写图。
尽管本文所揭示的主题名称易受各种修改和替代形式所影响，其特定具体实施例仍已通过附图中的实施例予以表示并且在本文中予以详述。然而，应了解的是，本文中特定具体实施例的说明用意不在于将本发明限制于所揭示的特定形式，相反地，如随附权利要求书所界定，用意在于涵盖落于本发明的精神及范畴内的所有修改、等同以及替代方案。
具体实施方式
下面说明本发明的各项说明性具体实施例。为了澄清，本说明书中并未说明实际实作态样的所有特征。当然，将会领会的是，在开发任何此实际具体实施例时，必须做出许多实作态样特定决策才能达到开发者的特定目的，例如符合系统有关及业务有关的限制条件，这些限制条件会随实作态样不同而变。此外，将了解的是，此一开发努力可能复杂且耗时，虽然如此，仍会是受益于本发明的本领域技术人员的例行工作。
本主题名称现将参照附图来说明。各种结构、系统及装置在附图中只是为了阐释而绘示，为的是不要因本领域技术人员众所周知的细节而混淆本发明。虽然如此，仍将附图包括进来以说明并阐释本发明的说明性实施例。本文中使用的字组及词组应了解并诠释为与本领域技术人员了解的字组及词组具有一致的意义。与本领域技术人员了解的通常及惯用意义不同的词汇或词组(即定义)的特殊定义，用意不在于通过本文词汇或词组的一致性用法提供暗示。就术语或词组用意在于具有特殊意义(亦即，不同于本领域技术人员所理解的术语或词组)的方面来说，此特殊定义将在说明书中以直接并且明确提供术语或词组特殊定义的明确方式予以清楚提出。
本文中的具体实施例针对具有超陡逆行井(SSRW)的半导体装置(例如：finFET晶体管)，其使用图型化n型与p型离子布植，后面跟着半导体层的外延生长，另外还针对用以建立工程掺质分布的受控制扩散程序，用来产生在通道中不具有掺杂或具有低掺杂的finFET，以使随机掺杂扰动(RDF)及其对VT的影响降到最小，同时在通道下面提供足以形成冲穿终止(PTS)的掺质。在一项具体实施例中，半导体层含有使n型与p型掺质其中一者或两者扩散受到抑制的材料。
图2至5绘示用于形成包括finFET晶体管的结构的一种结构与一种方法的一项具体实施例，该晶体管的通道不具有掺杂或具有低掺杂。程序始于图2，其中所示半导体晶圆200具有已接收n型掺质植入物202的第一区以及已接收p型掺质植入物204的第二区。本领域技术人员将会领会的是，利用零层(ZL)屏蔽在晶圆200上置放就n型与p型布植区可当作导件用于微影对准以及用于本文中所述后续程序的对准标记可有用处。n型区典型称为n型井，并且将在最后就pMOS finFET提供接面隔离。类似的是，p型区典型称为p型井，并且将在最后就nMOS finFET提供接面隔离。
可将各种方法与掺质中任一者用于形成n型与p型区202、204。请先转向用于形成n型区202的布植程序，该布植程序可包括将多种掺质用于形成PTS的多种植入物、将用于装置接面隔离的更深植入物。用于n型井布植的典型物种包括磷(P)、砷(As)及锑(Sb)。一般而言，P将会用于更深的布植，而As或Sb可用于更浅的布植。用于这些布植的尖峰掺质浓度典型为将会介于约8x1017原子/cm3与约2x1019原子/cm3之间，并且在一些具体实施例中，介于约1x1018原子/cm3与约1x1019原子/cm3之间。在一项具体实施例中，位在约前40nm深度上方的平均掺质浓度典型为将会介于约8x1017原子/cm3与约6x1018原子/cm3之间。
用于p型井的典型物种包括硼(B)、镓(Ga)及铟(In)。一般而言，B可用于更深的布植，而B、Ga或In可用于更浅的布植。用于这些布植的尖峰掺质浓度典型为将会介于约8x1017原子/cm3与约2x1019原子/cm3之间，并且在一些具体实施例中，介于约1x1018原子/cm3与约1x1019原子/cm3之间。在一项具体实施例中，位在约前40nm深度上方的平均掺质浓度典型为将会介于约8x1017原子/cm3与约6x1018原子/cm3之间。
井体布植前可先沉积任选的牺牲屏蔽介电质(未图示，例如：SiO2、SiON、SiN、其堆栈等)。该牺牲屏蔽介电质典型为可具有范围在约2nm至约15nm内的厚度，并且可用于各种用途。举例而言，屏蔽介电质可有帮助地降低对下伏Si晶圆200的损坏，其可辅助降低布植物种的通道效应，可在后续退火程序期间降低掺质物种(例如：As)的除气，并且可通过终止于屏蔽介电质中的低能量蔓延布植离子移除来提供更陡峭的最终掺质分布。本领域技术人员将了解的是，在完成布植程序与任选的退火程序之后，典型为将会使用各种习知的湿式及/或干式化学作用来移除屏蔽介电质。若使用任选的牺牲屏蔽介电质，则本领域技术人员将会领会的是，应该将其对后续布植程序的影响列入考虑，尤其是关于该(等)所植入掺质的深度者。
布植程序之后，使晶圆200经受退火程序以将表面损坏降低可有用处，用来改善当作晶种用于后续外延生长的结晶表面结构。退火程序可如在炉体中具有多个晶圆的批次程序、快速热退火(RTA)腔室或激光尖波退火(LSA)腔室中进行的单一晶圆程序般进行，或可通过以上的某组合来进行。之后，屏蔽介电质若有用到，可如以上所述遭受移除，然后可进行习知的外延预清洁及习知的外延预烘培。预烘培程序就范围在约10秒至约300秒内的时间周期，可在约650℃至约1000℃的范围内。
在图3中，Si外延层300已使用各种技巧在晶圆200上方生长。本领域技术人员将了解的是，Si外延层300的厚度可实质改变，但不脱离本发明的精神与范畴。举例而言，所设想的是，Si外延层300的厚度可在约30nm至约100nm的范围内变化，较佳范围是约40nm至约80nm，以使得可凭以形成所欲高度的鳍片。Si外延层300名义上可未经掺杂，或非常低度掺杂，并且可使用选择性或非选择性外延程序来生长。然而，非选择性外延程序典型为较佳，因为其可用更低的成本及更大的均匀性来进行。
在一替代具体实施例中，可在居于晶圆200与Si外延层300中间处沉积例如外延硅碳(SiC)302的扩散抑制层。SiC层302可用于在后续处理期间抑制一或多种掺质物种扩散。尤其是，C在抑制硼(B)与磷(P)扩散方面有用处。尽管高碳含量可提供有效扩散阻障物，这些高含量仍会具备有害效应，诸如SiC相位的沈淀或其它缺陷。有鉴于此，较佳碳量并未高到提供完美的扩散阻障物，而是应该高到足以就一或多种掺质物种提供显著的扩散抑制。在一项具体实施例中，C的浓度可确立在约0.05至约1.0％的范围内，并且厚度为约2nm至约30nm，端视C的浓度而定。在一较佳具体实施例中，C的浓度为约0.1至约0.4％，并且层302具有约5nm至约20nm的厚度。
如图4所示，习知的图型化与蚀刻程序用于形成位在Si外延层300以及下伏的n型掺杂区202与p型掺杂区204中的一连串实质类似凹口400，以及任选的SiC层302，其若有用到，用于形成多条线路402。这些线路的上“鳍片”部分404最终将会遭由栅极环绕，并且变为装置的信道。这些线路的下“子鳍片”部分406可用于提供冲穿终止及电隔离。图型化技巧举例而言，可包括自对准双图型化与四图型化方法，或使用极紫外线(UV)或电子束程序的微影技巧。为图型化而使用的附加层(例如：垫氧化物与垫氮化物)可在流程中的此制点于鳍片上面形成，但图4未加以表示。此蚀刻程序较佳将为在n型掺杂与p型掺杂区202、204两者中达到相当的蚀刻深度与宽度，用以产生较窄线路402。
在一项具体实施例中，此蚀刻程序可使用习知的干蚀刻程序来进行，诸如反应性离子蚀刻(RIE)程序。在另一具体实施例中，此蚀刻程序可包含干蚀刻程序与湿蚀刻程序的组合，诸如使用氢氟酸(HF)化学蚀刻。所设想的是，单一蚀刻程序将用于穿过Si外延、SiC(若有用到)并且进到n型/p型掺杂区202、204来完成蚀刻程序；然而，本领域技术人员将会领会的是，可将此蚀刻程序区分成一连串蚀刻程序。
如图5所示，线路402的蚀刻完成之后，实施浅隔离沟槽(STI)程序以及至少部分用STI介电质500填充凹口400可有用处。本领域技术人员将会领会的是，在STI程序期间，为了要使finFET的通道区502中非所欲掺质扩散降低而控制温度可有用处。温度的上限具有时间相依性。举例而言，退火时间超过30分钟且升温速率慢及降温速率慢的炉体程序可受限于850℃或更低温度。对于约10秒的更短退火程序，可接纳约1000℃的温度。
另外，在一些具体实施例中，n型/p型掺杂区202/204与Si层300的接口附近的至少该凹口400中包括SiN衬垫(图未示)以使对STI介电质500的掺杂损失(例如：B与In)降低可有用处。
此后，可使用众所周知的程序来进行习知的鳍片显露、栅极形成、接面形成、接触形成、金属化及类似者。举例而言，沉积STI介电质500层之后，可进行化学机械研磨(CMP)程序，后面跟着退火程序，用以改善STI介电质的质量。可进行氧化物蚀刻程序以通过将STI介电质500蚀刻至图5所示位准来使鳍片502显露。之后，可进行习知的栅极形成程序以产生栅极介电质504与栅极电极506。这些程序对于本领域技术人员属于已知，因此，本文中不再多作详细论述，以免不必要地混淆本文中的说明。
本领域技术人员将了解的是，鳍片502底座与STI介电质500的顶端表面506实质重合，因此，鳍片的高度为介于STI介电质500的顶端表面506与鳍片的顶端表面508之间的距离(图5中以H来指认)。在一些具体实施例中，鳍片502的高度H可为约40nm。
从沉积外延SiC 302(任选的)与Si 300开始，如图3所述，并且在整个程序流程各处，掺质起自n型与p型掺杂区202、204的向上扩散可经工程处理以制作最终掺质分布，其在介于衬底200中n型及p型掺质区202、204的原始位置的顶端与鳍片502的底端之间的外延子鳍片区510中置放适当含量的掺质。在一些具体实施例中，若PTS掺质中尖峰的置放不是紧密位于鳍片502下方，反而是位于鳍片502下面一距离处，则可谓令人期望。
图6就典型装置以及从n型与p型掺杂区202、204向上进到外延子鳍片区510的掺质扩散工程处理程度，展示有效导通电流与外延子鳍片区510的厚度的关图。有效导通电流是效能的度量，其中数字愈高表示效能愈高。如能从图6看出的是，所欲外延子鳍片区厚度的范围就中PTS掺杂为约20nm至约25nm，其中n型与p型区202、204均匀地受掺杂至晶圆200的最顶端。此厚度对于愈高的PTS掺杂会愈大，且对于愈低的PTS掺杂会愈低。若区域202、204中的掺质分布在更伸入晶圆的深度处达到峰值，本例为典型例子，则此值也会更小。尽管图6绘示基本趋势，实际所欲距离也会取决于布植条件、实际掺质距离、栅极长度、源极与漏级的位置等。
外延子鳍片区510在最终装置中变为PST区域某部分，在本具体实施例中，主要是使用起自所布植n型与p型区202、204的固体来源扩散来掺杂。此有别于先前技术，藉此，此子鳍片区510通过离子布植或通过起自固体来源掺质(例如：经掺杂玻璃)在该子鳍片区的侧边上直接经受掺杂。工程处理扩散到外延子鳍片区510的程度需要将n型与p型区202、204中的原始掺质分布控制到所欲程度、整体程序流程中的热预算、外延子鳍片区510的厚度以及其它程序变量。实际上，程序中多个热预算期间使扩散受限于所要求的程度会具有挑战性，这便是为什么通过任选的SiC 302来抑制(但非消除)扩散可有用处。在一项具体实施例中，外延子鳍片区510的厚度范围可在约2nm至约40nm内。在一较佳具体实施例中，外延子鳍片区厚度范围可在约5nm至约25nm内。此外延子鳍片区510中的掺质浓度在底端附近将会是最高，并且大体上朝鳍片通道降低。于某垂直位置处，掺杂含量变为有效未经掺杂及/或低度掺杂，小于约8x1017原子/cm3。尽管那会是在鳍片502的底端附近，实际上，若该转移出现于离鳍片502的底端一合理距离内，则可获得可接受行为。在一项具体实施例中，转移至未经掺杂或低度掺杂在鳍片502的底端的15nm内出现，并且在一较佳具体实施例中，于10nm内出现。另外，完成此程序之后，将会适度掺杂SiC层302下面的区域(例如，范围约8x1017cm-3至约2x1019cm-3)。在一些具体实施例中，外延子鳍片区510中与鳍片502的底端相邻处的掺质浓度将会比外延子鳍片区510中与n型及p型掺杂区202、204相邻处的掺质浓度低至少2倍。在其它具体实施例中，此掺质浓度降低因子范围将会是5至100。
现请参阅图7，根据本文中的具体实施例，所绘示的是用于制作包含finFET装置的半导体装置的系统的特写图。图7的系统700可包含半导体装置处理系统710及设计单元740。半导体装置处理系统710可基于设计单元740所提供的一或多个设计来制造集成电路装置。
半导体装置处理系统710可包含各种处理站，诸如：蚀刻程序站、离子布植站、光微影程序站、CMP程序站等。通过处理系统710所进行的处理步骤其中一或多者可通过处理控制器720来控制。处理控制器720可以是包含一或多种软件产品的工作站计算机、桌面计算机、膝上型计算机、平板计算机、或任何其它类型的运算装置，该软件产品能够控制程序、接收程序回馈、接收测试结果数据、进行学习周期调整、进行程序调整等。
半导体装置处理系统710可在诸如硅晶圆的媒体上产生集成电路。通过装置处理系统710生产集成电路可基于由集成电路设计单元740所提供的电路设计。处理系统710可在诸如输送器系统的输送机构750上提供已处理集成电路/装置715。在一些具体实施例中，此输送器系统可以是能够输送半导体晶圆的尖端无尘室输送系统。在一项具体实施例中，半导体装置处理系统710可包含多个处理步骤，例如：第1程序步骤、第2程序集合等，如以上所述。
在一些具体实施例中，标示“715”的项目可代表个别晶圆，而在其它具体实施例中，项目715可代表半导体群组，例如：一“批”半导体晶圆。集成电路或装置715可以是晶体管、电容器、电阻器、记忆胞、处理器及/或类似者。在一项具体实施例中，装置715为晶体管。
系统700的集成电路设计单元740能够提供可通过半导体处理系统710来制造的电路设计。设计单元740可接收与待利用功能胞元以及待设计集成电路的设计规格有关的数据。在一项具体实施例中，集成电路设计单元740可包含finFET，其具有本文中所述类型的布植体。
系统700可能够进行涉及各种技术的各种产品的分析及制造。举例而言，系统700可使用设计与生产数据以供制造CMOS技术、Flash技术、BiCMOS技术、功率装置、内存装置(例如，DRAM装置)、NAND内存装置及/或各种其它半导体技术的装置。
上述方法可通过指令来支配，此等指令储存于非暂存计算机可读储存媒体中，并且可由例如运算装置中的处理器来执行。本文中所述的运作各可对应于非暂存计算机内存或计算机可读储存媒体中所储存的指令。在各项具体实施例中，此非暂存计算机可读储存媒体包括磁性或光盘储存装置、诸如闪存的固态储存装置，或其它一或多个非挥发性内存装置。储存于非暂存计算机可读储存媒体上的计算机可读指令可呈原始码、汇编语言码、目标码或其它指令格式，由一或多个处理器来解译及/或执行。
以上所揭示的特定具体实施例仅属描述性，正如本发明可用本领域技术人员所明显知道的不同但等同方式予以修改并且实践而具有本文教示的效益。举例而言，以上所提出的程序步骤可按照不同顺序来进行。再者，如权利要求中所述除外，未意图限制于本文所示构造或设计的细节。因此，证实可改变或修改以上揭示的特定具体实施例，而且所有此类变例全都视为在本发明的范畴及精神内。因此，本文寻求的保护如权利要求书中所提。

Claims (20)

1.一种用于形成晶体管的方法，包含：
布植衬底以形成n掺杂区与p掺杂区的其中至少一者；
沉积居于该衬底上方且接触该衬底的掺质扩散抑制材料；
于该掺质扩散抑制材料上方沉积外延半导体层；
穿过该外延半导体层与该掺质扩散抑制材料并且部分穿过该n掺杂区与该p掺杂区的该其中至少一者形成沟槽；
于该沟槽中形成介电隔离区；
通过使该介电隔离区部分凹陷而在该外延半导体层的上部分中形成鳍片；
形成与该鳍片的至少两个表面相邻的栅极介电质；以及
使掺质从该n掺杂区与该p掺杂区的该其中至少一者至少部分扩散到该外延半导体层内，以形成扩散掺杂移转区，其中与该鳍片的底端部分相邻的该扩散掺杂移转区中的掺杂剂浓度低于与该n掺杂区与该p掺杂区的该其中至少一者相邻的该扩散掺杂移转区中的掺杂剂浓度。
2.如权利要求1所述的方法，其中沉积居于该衬底上方且接触该衬底的该掺质扩散抑制材料更包含沉积居于该衬底与该外延半导体层中间的硅碳外延层。
3.如权利要求2所述的方法，其中沉积居于该衬底与该外延半导体层中间的该硅碳外延层更包含沉积居于该衬底与该外延半导体层中间且所具碳莫耳浓度范围在0.05至1.0％内的硅碳外延层。
4.如权利要求2所述的方法，其中沉积居于该衬底与该外延半导体层中间的该硅碳外延层更包含沉积居于该衬底与该外延半导体层中间且所具厚度范围在2nm至30nm内的硅碳层。
5.如权利要求2所述的方法，其中沉积居于该衬底与该外延半导体层中间的该硅碳外延层更包含沉积居于该衬底与该外延半导体层中间且所具碳莫耳浓度范围在0.1至0.4％内及所具厚度范围在5nm至20nm内的硅碳外延层。
6.如权利要求1所述的方法，其中布植该衬底以形成该n掺杂区与该p掺杂区的该其中至少一者更包含使用范围在8x1017cm-3与2x1019cm-3内的尖峰掺质浓度，以硼(B)、镓(Ga)及铟(In)其中至少一者来布植该衬底。
7.如权利要求1所述的方法，其中布植该衬底以形成该n掺杂区与该p掺杂区的该其中至少一者更包含以硼(B)、镓(Ga)及铟(In)其中至少一者来布植该衬底，以在前40nm深度上方产生范围在8x1017cm-3与6x1018cm-3内的平均掺质浓度。
8.如权利要求1所述的方法，其中布植该衬底以形成该n掺杂区与该p掺杂区的该其中至少一者更包含使用范围在8x1017cm-3与2x1019cm-3内的尖峰掺质浓度，以磷(P)、砷(As)及锑(Sb)其中至少一者来布植该衬底。
9.如权利要求1所述的方法，其中布植该衬底以形成该n掺杂区与该p掺杂区的该其中至少一者更包含以磷(P)、砷(As)及锑(Sb)其中至少一者来布植该衬底，以在前40nm深度上方产生范围在8x1017cm-3与6x1018cm-3内的平均掺质浓度。
10.如权利要求1所述的方法，其中使掺质从该n掺杂区与该p掺杂区的该其中至少一者至少部分扩散到该外延半导体层内，以形成与该鳍片的该底端部分相邻的扩散掺杂移转区更包含：形成与该鳍片的该底端相离且具有一掺质浓度的扩散掺杂移转区，该掺质浓度至少2倍低于与经布植以形成该n掺杂区与该p掺杂区的该其中至少一者的该衬底相邻的该扩散掺杂移转区的掺质浓度。
11.如权利要求1所述的方法，其中使掺质从该n掺杂区与该p掺杂区的该其中至少一者至少部分扩散到该外延半导体层内，以形成与该鳍片的该底端部分相邻的扩散掺杂移转区更包含：形成所具厚度范围在5nm至30nm内的扩散掺杂移转区。
12.如权利要求1所述的方法，其中布植该衬底以形成该n掺杂区与该p掺杂区的该其中至少一者更包含：布植该衬底以形成至少一个n掺杂区与至少一个p掺杂区，以及从而形成至少一个pMOS晶体管与至少一个nMOS晶体管。
13.一种finFET晶体管，包含：
具有n掺杂区与p掺杂区的其中至少一者的衬底；
具有低掺杂通道区的鳍片；
包括居于该衬底上方且接触该衬底且居于该鳍片的该通道下方的掺质扩散抑制材料的子鳍片区；以及
位于该掺质扩散抑制材料下方的适度掺杂区，
其中与该鳍片的底端部分相邻的该子鳍片区中的掺杂剂浓度低于与该n掺杂区与该p掺杂区的该其中至少一者相邻的该子鳍片区中的掺杂剂浓度。
14.如权利要求13所述的finFET晶体管，其中该掺质扩散抑制材料为硅碳。
15.如权利要求14所述的finFET晶体管，其中该硅碳具有范围在0.05至1.0％内的碳莫耳浓度。
16.如权利要求14所述的finFET晶体管，其中该硅碳具有范围在2nm至30nm内的厚度。
17.如权利要求14所述的finFET晶体管，其中该硅碳具有范围在0.1至0.4％内的碳莫耳浓度以及范围在5nm至20nm内的厚度。
18.如权利要求13所述的finFET晶体管，其中该低掺杂通道区具有小于8x1017cm-3的平均活性掺质浓度。
19.如权利要求13所述的finFET晶体管，其中该适度掺杂通道区在相邻该掺质扩散抑制材料包含至少40nm的区域中，具有范围在8x1017cm-3与6x1018cm-3内的平均活性掺质浓度。
20.如权利要求13所述的finFET晶体管，其中该掺质扩散抑制材料具有范围在5nm至20nm内的厚度。
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