CN104037224B - 设计的用于n型MOSFET的源极/漏极区 - Google Patents

设计的用于n型MOSFET的源极/漏极区 Download PDF

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CN104037224B
CN104037224B CN201310231593.8A CN201310231593A CN104037224B CN 104037224 B CN104037224 B CN 104037224B CN 201310231593 A CN201310231593 A CN 201310231593A CN 104037224 B CN104037224 B CN 104037224B
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channel region
phosphorus
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CN104037224A (zh
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吕伟元
舒丽丽
黃俊鸿
李启弘
陈志辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本文公开了设计的用于n型MOSFET的源极/漏极区以及具有场效应晶体管的集成电路器件，该场效应晶体管包括具有第一层和第二层的源极区和漏极区。在沟道区的平面下方形成第一层。第一层包括掺杂硅和碳，其晶格结构小于硅的晶格结构。第二层形成在第一层上方并高出沟道区的平面。第二层由含有掺杂外延生长硅的材料形成。第二层的碳原子分数小于第一层的碳原子分数的一半。第一层在沟道区的表面下方形成至少10nm的深度。这种结构促进了形成浅结的源极/漏极延伸区的形成。这种器件提供了具有低阻抗的源极和漏极同时相对更能够抵抗短沟道效应。

Description

设计的用于n型MOSFET的源极/漏极区
技术领域
本发明涉及具有n型MOSFET的集成电路器件及其制造方法。
背景技术
随着集成电路器件的按比例缩小，设计师们面临着在短沟道效应与源极/漏极阻抗之间作出权衡。用以减小阻抗的更重的源极/漏极掺杂增大了结深和相关的短沟道效应。
发明内容
根据本发明的一个方面，提供了一种集成电路器件，包括：半导体主体，含有晶体硅；场效应晶体管，形成在半导体主体上，晶体管包括栅极、源极区、漏极区和沟道区，沟道区具有表面；第一层，包括在源极区和漏极区中且位于沟道表面所处平面的下方，第一层包括掺杂SiC并且第一层的晶格结构小于硅的晶格结构；以及第二层，位于第一层上方，第二层包括掺杂外延生长硅，第二层的一部分高出沟道表面所处的平面；其中，第二层的碳原子分数小于第一层的碳原子分数的一半；以及其中，第一层的一部分位于沟道表面所处平面的下方至少10nm。
优选地，第一层的碳原子分数在约1％至约2.5％的范围内。
优选地，第二层的磷浓度在2.5e20atom/cm3至1e22atom/cm3的范围内，以及第一层的磷浓度小于2.5e20atom/cm3。
优选地，第二层比沟道区的表面高至少10nm。
优选地，第二层延伸到沟道区的表面下方至少2nm的深度。
优选地，第二层位于沟道区的表面下方的部分的厚度为第一层的厚度的1/3到1/20。
优选地，第一层覆盖沟道区的侧壁，从而第一层的厚度将第二层与沟道区隔开至少3nm。
优选地，源极区和漏极区包括在栅极下方具有5nm以下深度的扩散掺杂延伸区。
优选地，在源极区和漏极区内紧邻沟道区的区域具有磷浓度梯度，磷浓度梯度表明这些区域通过来自第二层的磷扩散而掺杂了磷。
根据本发明的另一方面，提供了一种形成集成电路器件的方法，包括：提供半导体主体；在主体上形成栅极或伪栅极的堆叠件；图案化堆叠件以从源极区和漏极区中去除栅极的堆叠件，同时保留主体区上方将为栅极提供沟道区的图案化的堆叠件；在栅极的侧壁周围形成间隔件；在源极区和漏极区中的半导体主体中蚀刻沟槽；通过旋回沉积和蚀刻在沟槽中形成第一层，第一层包括硅、碳和磷；通过外延生长在第一层上方形成第二层，第二层包括硅和磷，第一层和第二层为晶体管提供源极区和漏极区；以及进行热退火以使磷至少从第二层扩散，扩散的磷决定源极区和漏极区与沟道区之间p-n结的位置。
优选地，磷从第二层扩散的速率快于从第一层扩散的速率。
优选地，蚀刻沟槽包括各向异性湿蚀刻。
优选地，第一层的碳原子分数为1％至2.5％；以及第二层的碳原子分数小于第一层的碳原子分数的一半。
优选地，第二层的磷浓度为2.5e20atom/cm3到1e22atom/cm3；以及第一层的磷浓度小于第二层的磷浓度。
优选地，第二层高出沟道区的表面至少10nm。
优选地，第二层延伸至沟道区的表面下方至少2nm的深度。
优选地，与沟槽至少部分共形地沉积第一层，从而第一层覆盖沟槽的侧面至少3nm的厚度。
优选地，第二层位于沟道区的表面下方的部分的厚度为第一层的厚度的1/3到1/20。
优选地，沟槽在沟道区的表面下方形成为至少10nm的深度。
优选地，热退火包括加热至950℃至1300℃范围内的温度，并且维持该温度不超过15毫秒。
附图说明
图1是根据一个实施例的示例性工艺的流程图。
图2至图8提供了根据一个实施例的处于各个制造阶段的示例性器件的截面图。
具体实施方式
本发明提供了集成电路器件。该器件包括半导体主体，其通常包含晶体硅。形成在半导体主体上的场效应晶体管包括形成在半导体主体中的沟道区。晶体管的源极区和漏极区包括第一层和第二层。第一层形成在沟道区的顶面所处平面的下方。第一层由含有掺杂SiC的材料形成，其中掺杂SiC的晶格结构小于硅的晶格结构。第二层形成在第一层上方并高出沟道区的顶面所处的平面。第二层由含有掺杂外延生长硅的材料形成。第二层的碳原子分数小于第一层的碳原子分数的一半。在一个实施例中，第一层在沟道区表面下方形成至少10nm的深度。这种结构利于形成非常浅的结的源极/漏极延伸区的形成。这种器件提供了具有低阻抗的源极和漏极，同时相对更能够抵抗短沟道效应。
本发明还提供了一种形成集成电路器件的方法。该方法包括：提供半导体主体以及在主体上形成堆叠件。该方法包括先栅极和后栅极工艺的实施例，并且堆叠件相应地为栅极堆叠件或者伪栅极堆叠件。图案化堆叠件，以从针对栅极的源极区和漏极区中去除堆叠件同时保留主体区上方的堆叠件，其将为栅极提供沟道区。在栅极位置的侧面形成间隔件。在源极区和漏极区中的半导体主体中形成沟槽。在一个实施例中，通过旋回沉积和蚀刻在沟槽中形成第一层。第一层包括硅、碳和磷。在一个实施例中，通过外延生长在第一层上方形成第二层。第二层包括硅和磷。第一层和第二层为晶体管提供源极区和漏极区。热退火使磷至少从第二层扩散。扩散的磷决定源极区和漏极区与沟道区之间p-n结的位置。
图1示出了用于制造器件200的方法100的流程图。图2至图8提供了处于各个制造阶段的器件200的截面图。应该理解，可以在所示方法100示出的操作之前、期间以及之后进行额外的处理以完成器件200的形成。
工艺100开始于操作101，在半导体主体201上提供堆叠件210。半导体主体201可以包括晶体硅(掺杂或非掺杂的)、或者绝缘体上半导体(SOI)结构。通常，SOI结构包括位于绝缘层上方的半导体材料层，诸如晶体硅。例如，绝缘层可以是隐埋氧化物(BOX)层或氧化硅层。在通常为硅或玻璃衬底的衬底上提供绝缘层。也可以使用诸如多层衬底或梯度衬底的其他半导体主体。半导体的结晶部分可以可选地为Ge、SiGe、III-V族材料等。
堆叠件210是用于栅极堆叠件或者伪栅极堆叠件的一层或多层。图2至图8提供了栅极堆叠件210包括三层的实例，包括介电层203、电极层205以及硬掩模层207。考虑到缩减的关键尺寸，器件200可以使用高k电介质和金属电极来代替更传统的栅极材料。用于栅电极的合适金属可能会受到形成源极区和漏极区的加工的不良影响。可以通过使用替代栅极(后栅极)工艺来避免这种损坏。
在一些实施例中，工艺100是替代栅极工艺。在替代栅极工艺中，由诸如多晶硅的牺牲材料代替电极金属来形成栅极堆叠件210。可选地，介电层203的位置还可以具有牺牲材料。在上述替代栅极工艺中，在操作113热退火之后，去除牺牲材料并沉积期望的栅极材料。
图1的工艺100继续进行操作103，图案化堆叠件210。图案化限定了栅极211的位置并从源极区和漏极区212中去除栅极堆叠件210。图案化通常包括：提供光刻掩模209；进行光刻来图案化掩模；以及进行蚀刻以将掩模的图案转移到下面的层。去除光刻掩模209，从而形成图3所示的结构。
工艺100继续进行操作105，如图4所示，邻近栅极位置211形成间隔件215。可以通过沉积和图案化介电层来形成间隔件215。在一些实施例中，间隔件215包括位于二氧化硅层上的氮化硅层。在可选实施例中，间隔件215包括一层或多层合适的材料。合适的材料可以包括例如二氧化硅、氮化硅、氮氧化硅(SiON)。可以使用任何合适的技术来沉积间隔件材料。例如，合适的技术可以包括等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)、次大气压化学汽相沉积(SACVD)等。可以通过例如各向异性蚀刻的任何合适的工艺来图案化间隔件215。
工艺100继续进行操作107，如图5所示，在半导体主体201中的源极区和漏极区的期望位置处形成沟槽217。在一些实施例中，操作107是各向异性湿蚀刻工艺。各向异性湿蚀刻可以是根据晶面方向选择性的湿蚀刻工艺。例如，蚀刻可以使用温度范围为15℃到50℃且体积浓度范围为1％到10％的四甲基氢氧化铵(TMAH)溶液。在一个实施例中，该溶液适合于硅晶体半导体主体201的蚀刻。各向异性蚀刻可以产生带有尖端218的沟槽。在一些实施例中，尖端218位于半导体主体201的表面214下方6nm以下的距离220处，其中表面214将成为沟道区的表面。在一些实施例中，尖端218比半导体主体201的表面214低3nm以下，例如2nm。尖端218较浅的深度利于形成浅结。
在工艺100的一些实施例中，在操作107之后，在图5所示的位置注入袋形/晕环(pocket/halo)区216。例如，可以将抑制电活性掺杂物(诸如磷)扩散的电中性掺杂物注入袋形区216。适合于此目的的掺杂物的实例包括氮和氟。可以通过任何合适的离子注入工艺形成袋形区216。换句话说，工艺100可以不需要注入216。可选地，可以通过注入相反导电性的掺杂物形成袋形区216，诸如用于n型晶体管的p型掺杂物。
图1的工艺100继续进行操作109，在沟槽217中形成第一层219，进而形成诸如图6所示的结构。第一层219提供源极区/漏极区212的导电区。在一些实施例中，第一层219对半导体主体201的沟道区213施加张力。这通过由晶体材料形成第一层219来实现，该晶体材料的晶格结构小于沟道区213的晶格结构。例如，当沟道区是硅时，含有SiC的第一层219可以提供期望的晶格结构。诸如磷的n型掺杂物的添加提供了期望的导电性。
在一些实施例中，通过旋回沉积和蚀刻(CDE)形成含有SiC：P的第一层219。CDE工艺包括穿插着回蚀步骤的沉积步骤。回蚀步骤去除了α-SiC和不良的c-Si：C膜。例如，蚀刻可以使用HCl气体。例如，沉积可以使用基于Si2H6的气体混合物。沉积温度可以例如在560℃至600℃的范围内。沉积工艺可以是共形或非共形的。由于非晶沉积具有比单晶相更高的蚀刻率，因此净效应可以是单相第一层219的生长。
在一些实施例中，第一层219是具有相对较高碳含量和相对较低磷含量的SiC：P。相对较高的碳含量是碳原子分数至少为1％。碳原子分数通常不大于2.5％。相对较高的碳含量降低了磷穿过第一层219的扩散率。相对较低的磷含量为4.5e20atom/cm3。为了提供期望的导电性，磷含量通常为至少1.5e20atom/cm3。减少磷穿过第一层219和从第一层219的扩散有助于形成浅结并且减轻了短沟道效应。
图1的工艺100继续进行操作111，如图7所示，在第一层219上方形成第二层221。与第一层219类似，第二层也包括n型掺杂物，其通常是磷。期望第二层221以比第一层219更高的扩散速率来释放掺杂物。在一些实施例中，一定程度上通过提供具有比第一层更高的掺杂物浓度的第二层221来实现更高的扩散速率。通常，第二层221包括浓度在2.5e20至1e22atom/cm3的范围内的掺杂物。在一些实施例中，第二层221的碳原子分数小于第一层219的碳原子分数的一半。通常，第二层221含有少量碳或不含碳。
可以通过任何合适的工艺形成第二层221。例如，合适的工艺可以是外延生长。当通过CDE形成第一层219时，可以以相对较高的温度实施外延生长。例如，相对较高的温度为650℃以上。相对较高的温度提高了生产率。通常以690℃以下的温度下实施第二层221的外延生长。
图1的工艺100继续到操作113，其中进行热退火。如图8所示，热退火113使得掺杂物从第二层221扩散以形成源极/漏极延伸区223。在热退火113之后，源极/漏极区212包括第一层219、第二层221以及源极/漏极延伸区223。热退火113通常是毫秒退火。在毫秒退火中，将半导体主体201加热到预焙温度。当从半导体主体201下方保持预焙温度时，顶面迅速被加热到峰值温度。
在一个提供期望的扩散程度的实施例中，峰值温度在950℃至1250℃的范围内，并且半导体主体201的顶面被维持在950℃至250℃的范围内达两毫秒以上但不超过15毫秒。在一个实施例中，可以使用600℃至780℃范围内的预焙温度。将表面从预焙温度加热到峰值温度的期望速率在700℃/s至900℃/s的范围内。
在一些实施例中，重复毫秒退火。可以在毫秒退火之前通过在较低温度下实施额外的退火来进一步改善掺杂物扩散分布。额外的退火可以包括使半导体主体201的温度升高至530℃到680℃范围内的温度的预焙，其维持5至15秒的时间。将表面加热到750℃至1000℃范围内的峰值温度并维持该温度持续达1至5秒。
第一层219和第二层221的几何形状和组成与退火113结合提供了浅的源极/漏极延伸区223。从第二层221扩散的掺杂物邻近沟道区213形成扇形(pie-wedge shaped)扩散掺杂区224。在一些实施例中，掺杂物从第二层221沿沟道区213的方向扩散4nm到10nm。扇形区224的窄端(其是邻近层221的端部)的深度(垂直长度)处在0至15nm的范围内。在一些实施例中，窄端的深度小于5nm。在一些实施例中，窄端的深度小于2nm。扇形区224的窄端较浅的深度利于形成浅的源极/漏极延伸区223。在一些实施例中，延伸区223位于栅极211下面的区域内的深度是15nm以下。在一些实施例中，延伸区223位于栅极211下面的区域内的深度是5nm以下。
通过布置第二层221使其下端位于沟道213的表面214下方来促进浅延伸区223的形成。在一些实施例中，第二层221延伸至沟道213的表面214所处平面下方2nm至10nm的深度。在一些实施例中，第二层221延伸至沟道213的表面214所处平面下方的深度等于第一层219的厚度的1/3至1/20。
图5的沟槽217被形成具有足够的深度，从而除整个第一层219之外，还容纳第二层221位于沟道213的表面214下方的部分221B。通常，沟槽217形成的深度在15nm至50nm的范围内，例如25nm。
通过布置第二层使其上端位于沟道213的表面214所处平面的上方来进一步促进浅源极/漏极延伸区223的形成。通常，第二层221的大部分221A位于沟道213的表面214上方。在一些实施例中，第二层在沟道表面214所处平面的上方延伸10nm至30nm。第二层221提供了用于在热退火113期间形成源极/漏极延伸区223的掺杂物源。从第二层221扩散到源极/漏极延伸区223的掺杂物通常必须穿过由间隔件215和第一层219形成的障碍物(bottleneck)。第二层221位于沟道213的表面214上方和下方的厚度有助于在退火工艺113期间维持该障碍物邻近的掺杂物浓度。
通过以覆盖沟槽217的侧壁的方式形成第一层来缩小障碍物的尺寸并促进浅源极/漏极延伸区223的形成。可以调整旋回沉积和蚀刻的条件以提供对形成第一层219的表面具有至少部分选择性的沉积工艺。在目前的环境下，选择性沉积是指沉积速率与独立于表面定向的特定类型的表面积成比例的沉积。在一些实施例中，沟槽217的侧壁的沉积速率比沟槽217的底部的沉积速率更显著，在这种意义上沉积是至少部分选择性的。第一层219的厚度通常为20nm，可以通过只有3nm厚的侧壁涂层将障碍物的尺寸缩减到期望的程度。第一层219通常覆盖沟槽217的侧壁的厚度为3nm至10nm。
在工艺100的操作113之后，通常实施额外的前端制程(FOL)，然后实施后端制程(BOL)处理。额外的处理可以提供具有各种部件的器件200，诸如接触件/通孔、互连金属层、介电层、钝化层等。源极/漏极区212可以被硅化，然而，在一种实施例中并不被硅化。本文所提供的结构可以具有足够低的源极/漏极阻抗从而使得硅化没有必要。
在操作101之前，可以在主体201上形成隔离区(未示出)。隔离区可以利用隔离技术(诸如硅局部氧化(LOCOS)或浅沟槽隔离(STI))以限定和电隔离器件200的各种有源区。
介电层203可以利用任何合适的电介质。可以使用SiO2或任何其他合适的电介质。不管使用先栅极还是后栅极工艺，介电层203都可以是高k介电层。高k电介质的导电性是二氧化硅的导电性的至少5倍。高k电介质的实例包括铪基材料，诸如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO以及HfO2-Al2O3合金。高k电介质的其他实例包括但不限于ZrO2、Ta2O5、Al2O3、Y2O3、La2O3以及SrTiO3。
导电层205也可以由各种材料的一层或多层形成。在一些实施例中，尤其是使用高k电介质的实施例中，导电层205为一层或多层金属层。金属层205通常包括Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、MoN和MoON的至少一层。用于导电金属层材料的其他实例包括钌、钯、铂、钴、镍、铪、锆、钛、钽、铝以及这些金属的导电碳化物、氧化物和合金。
本发明提供了一种集成电路器件，其包括含有晶体硅的半导体主体。在半导体主体上形成场效应晶体管。晶体管包括源极区、漏极区以及沟道区。源极区和漏极区包括形成在位于沟道区的顶面所处平面下方的半导体主体上的第一层。第一层由含有掺杂SiC且晶格结构小于硅的晶格结构的材料形成，并且源极区和漏极区进一步包括：形成在第一层上方并高出沟道区的顶面所处平面的第二层。第二层由含有掺杂的外延生长硅的材料形成。第二层的碳原子分数小于第一层的碳原子分数的一半。第一层在沟道区表面的平面下方形成至少10nm的深度。
本发明提供了一种形成集成电路器件的方法。该方法包括：提供半导体主体；在主体上形成栅极或伪栅极堆叠件；以及图案化堆叠件以从源极区和漏极区中去除栅极的堆叠件同时保留主体区上方的堆叠件，其将为栅极提供沟道区。该方法进一步包括：在栅极的侧壁上形成栅极间隔件；在源极区和漏极区中的半导体主体中蚀刻沟槽；以及通过旋回沉积和蚀刻在沟槽中形成第一层，第一层包括硅、碳和磷。该方法进一步包括：通过外延生长在第一层上方形成第二层，其中第二层包括硅和磷，第一层和第二层为晶体管提供了源极区和漏极区。该方法还包括进行热退火以使磷从至少第二层扩散，扩散的磷决定源极区和漏极区与沟道区之间p-n结的位置。
根据某些构思、部件和特征示出和/或描述了如以下权利要求所述的发明。虽然已经就数个构思或实例中的其中一个或者以广义和狭义的术语公开了特定的部件或特征，但是以广义或狭义描述的这些部件或特征可以与以广义或狭义描述的一个或多个其他部件或特征结合，其中本领域技术人员可以合理地认识到这些结合。而且，本说明书可以描述一个以上的发明并且以下权利要求不一定涵盖本文所描述的每一个构思、方面、实施例或实例。

Claims (11)

1.一种形成集成电路器件的方法，包括：
提供半导体主体；
在所述半导体主体上形成栅极或伪栅极的堆叠件；
图案化所述堆叠件以从源极区和漏极区中去除所述栅极的所述堆叠件，同时保留主体区上方将为所述栅极提供沟道区的图案化的堆叠件；
在所述栅极的侧壁周围形成间隔件；
在所述源极区和所述漏极区中的半导体主体中蚀刻沟槽；
通过旋回沉积和蚀刻在所述沟槽中形成第一层，所述第一层包括硅、碳和磷；
通过外延生长在所述第一层上方形成第二层，所述第二层包括硅和磷，所述第一层和所述第二层为晶体管提供源极区和漏极区；以及
进行热退火以使磷至少从所述第二层扩散穿过由所述间隔件和所述第一层形成的障碍物并且形成源极/漏极延伸区，其中，所述第一层覆盖所述沟槽的侧壁，所述源极/漏极延伸区沿着所述第一层的底面和外侧壁设置，扩散的磷决定所述源极区和所述漏极区与所述沟道区之间p-n结的位置。
2.根据权利要求1所述的方法，其中，磷从所述第二层扩散的速率快于从所述第一层扩散的速率。
3.根据权利要求1所述的方法，其中，蚀刻所述沟槽包括各向异性湿蚀刻。
4.根据权利要求1所述的方法，其中：
所述第一层的碳原子分数为1％至2.5％；以及
所述第二层的碳原子分数小于所述第一层的碳原子分数的一半。
5.根据权利要求1所述的方法，其中：
所述第二层的磷浓度为2.5e20atom/cm3到1e22atom/cm3；以及
所述第一层的磷浓度小于所述第二层的磷浓度。
6.根据权利要求1所述的方法，其中，所述第二层高出所述沟道区的表面至少10nm。
7.根据权利要求1所述的方法，其中，所述第二层延伸至所述沟道区的表面下方至少2nm的深度。
8.根据权利要求7所述的方法，其中，与所述沟槽至少部分共形地沉积所述第一层，从而所述第一层覆盖所述沟槽的侧面至少3nm的厚度。
9.根据权利要求1所述的方法，其中，所述第二层位于所述沟道区的表面下方的部分的厚度为所述第一层的厚度的1/3到1/20。
10.根据权利要求1所述的方法，其中，所述沟槽在所述沟道区的表面下方形成为至少10nm的深度。
11.根据权利要求1所述的方法，其中，所述热退火包括加热至950℃至1300℃范围内的温度，并且维持该温度不超过15毫秒。
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