CN103972193A - 功率晶体管装置和用于制造功率晶体管装置的方法 - Google Patents

功率晶体管装置和用于制造功率晶体管装置的方法 Download PDF

Info

Publication number
CN103972193A
CN103972193A CN201410045302.0A CN201410045302A CN103972193A CN 103972193 A CN103972193 A CN 103972193A CN 201410045302 A CN201410045302 A CN 201410045302A CN 103972193 A CN103972193 A CN 103972193A
Authority
CN
China
Prior art keywords
power transistor
power
electrode
transistor
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410045302.0A
Other languages
English (en)
Other versions
CN103972193B (zh
Inventor
R·奥特雷姆巴
J·赫格劳尔
J·施雷德尔
X·施勒格尔
K·希斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Austria AG
Original Assignee
Infineon Technologies Austria AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria AG filed Critical Infineon Technologies Austria AG
Publication of CN103972193A publication Critical patent/CN103972193A/zh
Application granted granted Critical
Publication of CN103972193B publication Critical patent/CN103972193B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/77—Apparatus for connecting with strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04034—Bonding areas specifically adapted for strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/27318—Manufacturing methods by local deposition of the material of the layer connector in liquid form by dispensing droplets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/29078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73255—Bump and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8434—Bonding interfaces of the connector
    • H01L2224/84345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92246—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Inverter Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

各种实施例提供一种功率晶体管装置。功率晶体管装置可以包括载体；第一功率晶体管，具有控制电极和第一功率电极和第二功率电极；以及第二功率晶体管，具有控制电极和第一功率电极和第二功率电极。第一功率晶体管和第二功率晶体管可以彼此紧邻地布置在载体上，使得第一功率晶体管的控制电极和第二功率晶体管的控制电极面向载体。

Description

功率晶体管装置和用于制造功率晶体管装置的方法
技术领域
各种实施例总体上涉及功率晶体管装置和用于制造功率晶体管装置的方法。
背景技术
可以将功率半导体芯片集成到用于各种电路装置的电子封装中。例如，级联电路或半桥电路可以由分立元件或封装、或者利用芯片上芯片（chip-on-chip）的结构来实施，其中可能使用扩散焊接。
分立元件或封装可以导致显著封装感应性，并且因此导致开关损耗。而芯片上芯片结构可能会导致相对于顶部的芯片（例如，硅场效应晶体管芯片）的热限制。
发明内容
各种实施例提供一种功率晶体管装置。功率晶体管装置可以包括载体；第一功率晶体管，具有控制电极和第一功率电极和第二功率电极；以及第二功率晶体管，具有控制电极和第一功率电极和第二功率电极。第一功率晶体管和第二功率晶体管可以彼此紧邻地布置在载体上，使得第一功率晶体管的控制电极和第二功率晶体管的控制电极面向载体。
附图说明
在附图中，同样的参考符号贯穿不同的示图通常指代相同的部分。此外，附图不一定按比例，而是通常将重点置于图示本发明的原理。在下面的描述中，参考以下附图描述了本发明的各种实施例，附图中：
图1示出了根据各种实施例的功率晶体管装置；
图2示出了根据各种实施例的功率晶体管装置；
图3示出了根据各种实施例的功率晶体管装置；
图4示出了根据各种实施例的级联电路；
图5A-5H示出了根据各种实施例制造功率晶体管装置的过程；以及
图6示出了图示用于根据各种实施例制造功率晶体管装置的方法的流程图。
具体实施方式
以下详细描述参考通过图示示出本发明可以在其中实施的具体细节和实施例的附图涉及以说明方式示出可以实施本发明的具体细节和实施例的附图。
词语“示例性的”在本文中用于意指“用作示例、实例或图示”。本文中描述为“示例性的”任何实施例或设计并不一定要被解释为优于或有利于其它实施例或设计。
关于“在”侧面或表面“之上”形成的沉积的材料所使用的词语“在……之上”在本文中可以被用于意指沉积的材料可以“直接”形成“在”隐含的侧面或表面“上”（例如，直接与之接触）。关于“在”侧面或表面“之上”形成的沉积的材料所使用的词语“在……之上”在本文中可以被用于意指沉积的材料可以通过被布置在隐含的侧面或表面与沉积的材料之间的一个或多个附加层来“间接”形成“在”隐含的侧面或表面“上”。
各种实施例提供用于功率应用的低电感性封装。
图1至图3示出了根据各种实施例的功率晶体管装置100。
图1示出了功率晶体管装置100的顶视图，并且图2示出了功率晶体管装置100的背面。
功率晶体管装置100可以包括载体102、第一功率晶体管104和第二功率晶体管106。如在图1和图2中所示，第一功率晶体管104可以包括控制电极112、第一功率电极114和第二功率电极116；并且第二功率晶体管106可以包括控制电极122、第一功率电极124和第二功率电极126。第一功率晶体管104和第二功率晶体管106可以被彼此紧邻地布置在载体102上，使得第一功率晶体管104的控制电极112和第二功率晶体管106的控制电极122面向载体102。
在各种实施例中，第一功率晶体管104的第一功率电极114和第二功率晶体管106的第一功率电极124可以背对载体102。第一功率晶体管104的第一功率电极114和第二功率晶体管106的第一功率电极124可以彼此电耦合。
载体102可以包括引线框架，其可以由金属或金属合金制成，例如，从由以下各项组成的组中选择的材料：铜（Cu）、铁镍（FeNi）、钢等。
在各种实施例中，第一功率晶体管104的第一功率电极114和第二功率晶体管106的第一功率电极124可以利用如图3所示的导电耦合结构132彼此电耦合。导电耦合结构132可以被布置在如图1所示的结构上面，即被布置在第一功率晶体管104的第一功率电极114和第二功率晶体管106的第一功率电极124上面，其在图3中被隐藏在导电耦合结构132的下面。
在各种实施例中，耦合结构132可以包括金属和金属合金中的至少一个。在各种实施例中，耦合结构132可以包括选自由以下各项组成的结构的组中的至少一个结构：线夹、条带、导线、板、以及导体轨道。在各种实施例中，耦合结构132可以具有1K/W或更小的热电阻。
导电耦合结构132可以与任何功率晶体管装置外部端子电隔离。功率晶体管装置外部端子可以例如包括耦合到载体102的引线或引脚。
根据各种实施例，第一功率晶体管104和第二功率晶体管106中的一个或二者可以包括MOSFET、JFET、IGBT或双极型晶体管。
在各种实施例中，第一功率晶体管104和第二功率晶体管106可以是相同晶体管类型的晶体管。在各种实施例中，第一功率晶体管104和第二功率晶体管106可以是FET（场效应晶体管）或IGBT，例如具有约20V至20kV的额定电压。
根据各种实施例，第一功率晶体管104和第二功率晶体管106可以是相同的电压等级，例如，第一功率晶体管104和第二功率晶体管106可以具有相同的额定电压，即可以由第一功率晶体管104和第二功率晶体管106维持的相同的最大电压。第一功率晶体管104和第二功率晶体管106可以具有不同的电流承载能力。
根据各种实施例，第一功率晶体管104的控制电极112和第二功率晶体管106的控制电极122可以是MOSFET、JFET或IGBT晶体管的栅极电极、和双极型晶体管的基极电极之一。
根据各种实施例，第一功率晶体管104的第一功率电极114可以是MOSFET或JFET晶体管的源极电极、和IGBT或双极型晶体管的发射极电极之一。第二功率晶体管106的第一功率电极124可以是MOSFET或JFET晶体管的源极电极、和IGBT或双极型晶体管的发射极电极之一。在各种实施例中，第一功率晶体管104和第二功率晶体管106，是PMOS晶体管并且它们各自的源极电极114、124彼此电耦合，可以形成两侧阻塞PMOS晶体管电路。
根据各种实施例，第一功率晶体管104的第一功率电极114可以是MOSFET或JFET晶体管的漏极电极、和IGBT或双极型晶体管的集电极电极之一；并且第二功率晶体管的第一功率电极可以是MOSFET或JFET晶体管的漏极电极、和IGBT或双极型的晶体管的集电极电极之一。在各种实施例中，第一功率晶体管104和第二功率晶体管106，是NMOS晶体管并且它们各自的漏极电极114、124彼此电耦合，可以形成两侧阻塞NMOS晶体管电路。
由各种实施例中的功率晶体管装置100形成的两侧阻塞PMOS晶体管电路或两侧阻塞NMOS晶体管电路可以是两侧阻塞开关电路，其可以被用于两个方向上阻塞电压。
根据各种实施例，第一功率晶体管104的第一功率电极114可以是MOSFET或JFET晶体管的源极电极、和IGBT或双极型晶体管的发射极电极之一。第二功率晶体管106的第一功率电极124可以是MOSFET或JFET晶体管的漏极电极、和IGBT或双极型晶体管的集电极电极之一。具有彼此电耦合的相应的第一功率电极的第一功率晶体管104和第二功率晶体管106可以形成共源共栅电路或半桥电路。作为示例，在图4中示出了对应于功率装置100的级联电路400，如将在下面更详细地描述。
根据各种实施例，第一功率晶体管104可以是HEMT，诸如GaNHEMT、或SiC HEMT、或高压Si HEMT。根据各种实施例，第二功率晶体管106可以是低压（例如小于200V）MOSFET（p沟道或n沟道），诸如SFET。
在图1、图2和图4所图示的实施例中，第一功率晶体管104为GaN HEMT并且第二功率晶体管106是SFET。然而，应当理解，第一功率晶体管104和第二功率晶体管106可以是上述的各种类型的功率晶体管。
如在图1和图2中所示的，功率晶体管装置100形成倒装芯片级联（FCC）装置，其中第一GaN HEMT104和SFET106的栅极电极112、122倒装到载体102上的相应引脚，并且因此被连接，而没有由安装引起的感应性。因此，栅极电极112、122可以被重新分配或重新布线，而无需要接合导线或芯片。
FCC装置100由倒装的芯片形成，其中GaN芯片104被布置成其栅极电极112和漏极电极116面朝下（即面朝向载体102）并且SFET芯片106被布置成其栅极电极122和源极电极126面朝下（即面朝向载体102）。GaN芯片104的源极电极114和SFET106的漏极电极124面朝上，即背对载体102。
GaN芯片104的源极电极114和SFET106的漏极电极124可以例如通过图3的导电耦合结构132被内部连接（例如导线连接），以在图4的级联电路400的GaN芯片104和SFET106之间形成结点。GaN芯片104的源极电极114和SFET106的漏极电极124之间的连接不需要外部连接或引脚或引线，这使得有可能独立于封装接触面积（例如，封装覆盖区）地，相对于其热性能（例如，热容量和热扩散），优化导电耦合结构132（例如，触头线夹）。
通过以上的其中功率晶体管的控制电极面朝下朝向载体的各种实施例中的功率晶体管装置100的布置，重新分配元件（即载体102，例如引线框架）不受任何导线接合的约束。
各种实施例中的功率晶体管装置100能够简单地以小的开关损耗冷却，并且可以实现类似于芯片上芯片结构的性能，但没有热限制。
功率晶体管装置100可以具有范围从约1mm2到10cm2的尺寸。
可以提供一种封装，包括以上各种实施例的功率晶体管装置100和被配置用于接收来自封装外部的电信号的封装端子（例如引脚或引线）。功率晶体管装置100的导电耦合结构132可以与封装端子电隔离。
在各种实施例中，封装可以由QFN（四面扁平无引线）封装、DSO（双小外形封装）封装、TO220、TO247、TO263、TO252等之一形成。在各种实施例中，封装可以形成为嵌入式封装。
在一个示例中，具有倒装的GaN和SFET芯片的功率晶体管装置100可以封装成8×8ThinPAK，其中GaN芯片104可以是高压（例如，大于200V）HEMT开关并且SFET芯片106可以是低压（例如，小于200V）功率MOSFET。GaN HEMT104是常通器件，并且通过引入低压SFET106而被转换为常断晶体管。这样的GaN-SFET装置100可以对应于图4的级联电路400。
共源共栅电路400可以包括在公共源极中的低压SFET106和在公共栅极中的高压GaN–HEMT配置。得到的3端口电路可以用作开关。GaN HEMT104的漏极电极限定级联电路400的600V行为。
图5A到图5H示出了根据各种实施例的制造功率晶体管装置的过程。
在图5A中，提供载体502。载体502可以包括用于安装一个或多个芯片的相应的裸片焊盘，。
在图5B中，将焊膏504沉积到载体502的相应区域上，例如，沉积到载体502的用于与芯片的连接的相应引脚上。
在图5C中，将第一功率晶体管芯片506和第二功率晶体管芯片508安装在相应的焊膏504上。在各种实施例中，第一功率晶体管芯片506和第二功率晶体管芯片508彼此紧邻地布置，并且它们的控制电极面朝下，即面朝向载体502。在各种实施例中，第一功率晶体管芯片506和第二功率晶体管芯片508的控制电极可经由软焊接、粘附、扩散焊接、烧结等连接到载体502。
在图5D中，可以将焊膏510沉积到第一功率晶体管芯片506和第二功率晶体管芯片508上。例如，可以将焊膏510沉积到的第一功率晶体管芯片506和第二功率晶体管芯片508的相应的功率电极上。
在图5E中，可以通过焊膏510形成导电耦合结构512，以连接第一功率晶体管芯片506和第二功率晶体管芯片508。
在图5E中，执行加热处理以熔化焊膏504、510。
在图5F中，执行冷却处理以硬化焊膏504、510。
在图5H中，执行另一个加热过程，从而形成具有第一功率晶体管芯片506和第二功率晶体管芯片508的功率晶体管装置。由此形成的功率晶体管装置具有通过器件纵向流动的电流的纵向结构。
图6示出了图示用于根据各种实施例的制造功率晶体管装置的方法的流程图600。
在602，可以将第一功率晶体管和第二功率晶体管布置在导电结构上，第一功率晶体管具有控制电极和第一功率电极和第二功率电极，并且第二功率晶体管具有控制电极和第一功率电极和第二功率电极可以被布置到一个导电结构，使得第一功率晶体管和第二功率晶体管被彼此紧邻地布置，并且使得第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极被固定到导电结构，并且从而彼此电耦合
在604中，可以使用导电结构作为中间载体将第一功率晶体管和第二功率晶体管安装在载体上，使得第一功率晶体管的控制电极和第二功率晶体管的控制电极面向载体
根据各种实施例，第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极可以被焊接到导电结构。在各种实施例中，第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极可以利用扩散焊接被焊接到导电结构。
在各种实施例中，第一功率晶体管的控制电极和第二功率晶体管的控制电极可以利用软焊接、粘附、扩散焊接、烧结等被连接到载体，例如连接到载体的对应的引脚或接触焊盘。
各种实施例针对功率晶体管装置。功率晶体管装置可包括载体；第一功率晶体管，具有控制电极和第一功率电极和第二功率电极，以及第二功率晶体管，具有控制电极和第一功率电极和第二功率电极。第一功率晶体管和第二功率晶体管可以被彼此紧邻地布置在载体上，使得第一功率晶体管的控制电极和第二功率晶体管的控制电极面向所述载体。
在各种实施例中，第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极可以背对载体。第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极可以彼此电耦合。
第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极可以利用导电耦合结构彼此电耦合。在各种实施例中，耦合结构可以包括金属和金属合金中的至少一个。耦合结构可以包括选自由以下各项组成的结构的组中的至少一个结构：线夹、条带、导线、板、以及导体轨道。耦合结构可以具有1K/W或更小的热电阻。
根据各种实施例，第一功率晶体管和第二功率晶体管中的一个或二者可以包括MOSFET（金属氧化物半导体场效应晶体管）、JFET（结栅场效应晶体管）、IGBT（绝缘栅双极晶体管）或双极型晶体管等。
根据各种实施例，第一功率晶体管的控制电极和第二功率晶体管的控制电极可以是第一功率晶体管和第二功率晶体管的栅极电极和基极电极之一。
根据各种实施例，第一功率晶体管的第一功率电极可以是第一功率晶体管的源极电极和发射极电极之一，并且第二功率晶体管的第一功率电极可以是第二功率晶体管的漏极电极和集电极电极之一。第一功率晶体管和第二功率晶体管的各自的第一功率电极彼此电耦合，可以形成共源共栅电路或半桥电路。
根据各种实施例，第一功率晶体管的第一功率电极可以是第一功率晶体管的源极电极和发射极电极之一；并且第二功率晶体管的第一功率电极可以是第二功率晶体管的源极电极和发射极电极之一。在各种实施例中，第一功率晶体管和第二功率晶体管是PMOS（p沟道金属氧化物半导体）晶体管并且它们各自的源极电极彼此电耦合，可以形成两侧阻塞PMOS晶体管电路。
第一功率晶体管的第一功率电极可以是第一功率晶体管的漏极电极和集电极电极之一；并且第二功率晶体管的第一功率电极可以是第二功率晶体管的漏极电极和集电极电极之一。在各种实施例中，第一功率晶体管及第二功率晶体管是NMOS（n沟道金属氧化物半导体）晶体管并且它们各自的漏极电极彼此电耦合，可以形成两侧阻塞的NMOS晶体管电路。
根据各种实施例，第一功率晶体管可以是高电子迁移率晶体管（HEMT）。HEMT的示例可以包括但不限于GaN（氮化镓）高电子迁移率晶体管、或SiC（碳化硅）高电子迁移率晶体管、或高压Si（硅）高电子迁移率晶体管。根据各种实施例，第二功率晶体管可以是低压（例如小于200V）MOSFET（p沟道或n沟道）。低压MOSFET的示例可以包括但不限于SFET（硅场效应晶体管）。
在各种实施例中，第一功率晶体管和第二功率晶体管可以是相同晶体管类型的晶体管。在各种实施例中，第一功率晶体管和第二功率晶体管可以是FET（场效应晶体管）或IGBT，例如具有约20V至20kV的额定电压。
根据各种实施例，第一功率晶体管和第二功率晶体管可以是相同的电压等级。例如，第一功率晶体管和第二功率晶体管可以具有相同的额定电压，即可以由第一功率晶体管和第二功率晶体管维持相同的最大电压。在一个实施例中，第一功率晶体管和第二功率晶体管可以具有不同的电流承载能力。
用于电耦合第一功率晶体管和第二功率晶体管的导电耦合结构可以与任何功率晶体管装置外部端子电隔离。功率晶体管装置外部端子可以例如包括耦合到载体的引线或引脚。
载体可以包括引线框架，其可以由以下的金属或金属合金制成，例如，选自由以下各项组成的组中的材料：铜（Cu）、铁镍（FeNi）、钢等。
各种实施例还针对一种封装，其可以包括功率晶体管装置。功率晶体管装置可以包括载体；第一功率晶体管，具有控制电极和第一功率电极和第二功率电极；以及第二功率晶体管，具有控制电极和第一功率电极和第二功率电极。第一功率晶体管和第二功率晶体管可以被彼此紧邻地布置在载体上，使得第一功率晶体管的控制电极和第二功率晶体管的控制电极面向载体；并且第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极背对载体。第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极可以利用导电耦合结构彼此电耦合。封装可以进一步包括封装端子，被配置用于接收来自封装外部的电信号。导电耦合结构可以与封装端子电隔离。
关于上文的功率晶体管装置描述的各种实施例对于包括功率晶体管装置的封装类似地有效。
在各种实施例中，封装可以由QFN（四面扁平无引线）封装、DSO（双小外形封装）封装、TO220、TO247、TO263、TO252等中的一个所形成。在各种实施例中，封装可以形成为嵌入式封装。
进一步的实施例针对一种用于制造功率晶体管装置的方法。该方法可以包括在导电结构上布置第一功率晶体管和第二功率晶体管，第一功率晶体管具有控制电极和第一功率电极和第二功率电极，并且第二功率晶体管具有控制电极和第一功率电极和第二功率电极，使得第一功率晶体管和第二功率晶体管彼此紧邻地布置，并且使得第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极被固定到导电结构，并且从而彼此电耦合；并且使用导电结构作为中间载体将第一功率晶体管和第二功率晶体管安装在载体上，使得第一功率晶体管的控制电极和第二功率晶体管的控制电极面向载体。
根据各种实施例，第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极被焊接到导电结构。在各种实施例中，第一功率晶体管的第一功率电极和第二功率晶体管的第一功率电极可以利用扩散焊接被焊接到导电结构。
在各种实施例中，第一功率晶体管的控制电极和第二功率晶体管的控制电极可以利用软焊接、粘附、扩散焊接、烧结等被连接到载体，例如连接到载体的对应的引脚或接触焊盘。
虽然已经参考特定实施例具体地示出和描述了本发明，但是本领域技术人员将理解可以在不脱离所附权利要求所限定的精神和范围的前提下在其中作出形式和细节方面的各种改变。本发明的范围因此由所附权利要求所指示，并且因此意图包含落入权利要求的等效形式的意义和范围内的各种改变。

Claims (20)

1.一种功率晶体管装置，包括：
载体；
第一功率晶体管，具有控制电极和第一功率电极和第二功率电极；
第二功率晶体管，具有控制电极和第一功率电极和第二功率电极；
其中所述第一功率晶体管和所述第二功率晶体管彼此紧邻地布置在所述载体上，使得所述第一功率晶体管的所述控制电极和所述第二功率晶体管的所述控制电极面向所述载体。
2.根据权利要求1所述的功率晶体管装置，
其中所述第一功率晶体管的所述第一功率电极和所述第二功率晶体管的所述第一功率电极背对所述载体；并且
其中所述第一功率晶体管的所述第一功率电极和所述第二功率晶体管的所述第一功率电极彼此电耦合。
3.根据权利要求2所述的功率晶体管装置，
其中所述第一功率晶体管的所述第一功率电极和所述第二功率晶体管的所述第一功率电极利用导电耦合结构彼此电耦合。
4.根据权利要求3所述的功率晶体管装置，
其中所述耦合结构包括金属和金属合金中的至少一个。
5.根据权利要求3所述的功率晶体管装置，
其中所述耦合结构包括选自由以下各项组成的结构的组中的至少一个结构：
线夹；
条带；
导线；
板；以及
导体轨道。
6.根据权利要求3所述的功率晶体管装置，
其中所述耦合结构具有1K/W或更小的热电阻。
7.根据权利要求2所述的功率晶体管装置，
其中所述第一功率晶体管的所述第一功率电极是所述第一功率晶体管的源极电极和发射极电极之一；
其中所述第二功率晶体管的所述第一功率电极是所述第二功率晶体管的漏极电极和集电极电极之一。
8.根据权利要求2所述的功率晶体管装置，
其中所述第一功率晶体管的所述第一功率电极是所述第一功率晶体管的源极电极和发射极电极之一；
其中所述第二功率晶体管的所述第一功率电极是所述第二功率晶体管的源极电极和发射极电极之一。
9.根据权利要求2所述的功率晶体管装置，
其中所述第一功率晶体管的所述第一功率电极是所述第一功率晶体管的漏极电极和集电极电极之一；
其中所述第二功率晶体管的所述第一功率电极是所述第二功率晶体管的漏极电极和集电极电极之一。
10.根据权利要求1所述的功率晶体管装置，
其中所述第一功率晶体管是高电子迁移率晶体管。
11.根据权利要求10所述的功率晶体管装置，
其中所述高电子迁移率晶体管是氮化镓高电子迁移率晶体管、碳化硅高电子迁移率晶体管、以及高压硅高电子迁移率晶体管之一。
12.根据权利要求1所述的功率晶体管装置，
其中所述第二功率晶体管是低压金属氧化物半导体场效应晶体管。
13.根据权利要求1所述的功率晶体管装置，
其中所述第一功率晶体管和所述第二功率晶体管是相同晶体管类型的晶体管。
14.根据权利要求13所述的功率晶体管装置，
其中所述第一功率晶体管和所述第二功率晶体管是场效应晶体管和绝缘栅双极晶体管之一。
15.根据权利要求1所述的功率晶体管装置，
其中所述第一功率晶体管和所述第二功率晶体管是相同的电压等级。
16.根据权利要求3所述的功率晶体管装置，
其中所述导电耦合结构与任何功率晶体管装置外部端子电隔离。
17.一种封装，包括：
功率晶体管装置，包括：
载体；
第一功率晶体管，具有控制电极和第一功率电极和第二功率电极；
第二功率晶体管，具有控制电极和第一功率电极和第二功率电极；
其中所述第一功率晶体管和所述第二功率晶体管彼此紧邻地布置在所述载体上，使得所述第一功率晶体管的所述控制电极和所述第二功率晶体管的所述控制电极面向所述载体；
其中所述第一功率晶体管的所述第一功率电极和所述第二功率晶体管的所述第一功率电极背对所述载体；并且
其中所述第一功率晶体管的所述第一功率电极和所述第二功率晶体管的所述第一功率电极利用导电耦合结构彼此电耦合；
封装端子，被配置用于接收来自所述封装外部的电信号；
其中所述导电耦合结构与所述封装端子电隔离。
18.一种用于制造功率晶体管装置的方法，所述方法包括：
在导电结构上布置第一功率晶体管和第二功率晶体管，所述第一功率晶体管具有控制电极和第一功率电极和第二功率电极，所述第二功率晶体管具有控制电极和第一功率电极和第二功率电极，使得所述第一功率晶体管和所述第二功率晶体管彼此紧邻地布置，并且使得所述第一功率晶体管的所述第一功率电极和所述第二功率晶体管的所述第一功率电极被固定到所述导电结构，并且从而彼此电耦合；并且
使用所述导电结构作为中间载体将所述第一功率晶体管和所述第二功率晶体管安装在载体上，使得所述第一功率晶体管的所述控制电极和所述第二功率晶体管的所述控制电极面向所述载体。
19.根据权利要求18所述的方法，
其中所述第一功率晶体管的所述第一功率电极和所述第二功率晶体管的所述第一功率电极被焊接到所述导电结构。
20.根据权利要求19所述的方法，
其中所述第一功率晶体管的所述第一功率电极和所述第二功率晶体管的所述第一功率电极利用扩散焊接被焊接到所述导电结构。
CN201410045302.0A 2013-02-05 2014-02-07 功率晶体管装置和用于制造功率晶体管装置的方法 Active CN103972193B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/759,161 US9099441B2 (en) 2013-02-05 2013-02-05 Power transistor arrangement and method for manufacturing the same
US13/759,161 2013-02-05

Publications (2)

Publication Number Publication Date
CN103972193A true CN103972193A (zh) 2014-08-06
CN103972193B CN103972193B (zh) 2017-04-12

Family

ID=51206213

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410045302.0A Active CN103972193B (zh) 2013-02-05 2014-02-07 功率晶体管装置和用于制造功率晶体管装置的方法

Country Status (3)

Country Link
US (1) US9099441B2 (zh)
CN (1) CN103972193B (zh)
DE (1) DE102014101261B4 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448746A (zh) * 2014-08-07 2016-03-30 北大方正集团有限公司 一种氮化镓器件及封装方法
CN107925404A (zh) * 2015-09-10 2018-04-17 古河电气工业株式会社 功率器件
CN108726467A (zh) * 2017-04-21 2018-11-02 英飞凌科技股份有限公司 具有高热容量的装置和用于制造该装置的方法
CN109935561A (zh) * 2017-12-18 2019-06-25 镓能半导体（佛山）有限公司 一种氮化镓器件及氮化镓器件的封装方法
WO2020098590A1 (zh) * 2018-11-16 2020-05-22 苏州东微半导体有限公司 半导体功率器件

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9960234B2 (en) * 2014-10-07 2018-05-01 Semiconductor Components Industries, Llc Method of forming a semiconductor device and structure therefor
US9496207B1 (en) 2015-06-19 2016-11-15 Semiconductor Components Industries, Llc Cascode semiconductor package and related methods
EP3385981A1 (en) * 2017-04-04 2018-10-10 Nexperia B.V. Power apparatus
JP7124474B2 (ja) 2018-06-13 2022-08-24 株式会社デンソー 半導体装置
EP4044225A1 (en) * 2021-02-16 2022-08-17 Nexperia B.V. A semiconductor device and a method of manufacturing a semiconductor device
FR3121277B1 (fr) * 2021-03-26 2024-02-16 Safran Electronics & Defense Procédé pour assembler un composant électronique à un substrat

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101238562A (zh) * 2005-03-04 2008-08-06 国际整流器公司 半导体封装的制造
US20100078783A1 (en) * 2008-09-30 2010-04-01 Infineon Technologies Ag Device including two mounting surfaces
US20100297810A1 (en) * 2006-05-10 2010-11-25 Infineon Technologies Ag Power Semiconductor Device and Method for Its Production

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19610135C1 (de) 1996-03-14 1997-06-19 Siemens Ag Elektronische Einrichtung, insbesondere zum Schalten elektrischer Ströme, für hohe Sperrspannungen und mit geringen Durchlaßverlusten
TWI365516B (en) * 2005-04-22 2012-06-01 Int Rectifier Corp Chip-scale package
DE102005034012A1 (de) 2005-07-18 2006-11-09 Infineon Technologies Ag Leistungshalbleiterbauteil, insbesondere für das Treiben induktionsarmer Lasten, und Verfahren zur Herstellung eines Leistungshalbleiterbauteils
US7271470B1 (en) 2006-05-31 2007-09-18 Infineon Technologies Ag Electronic component having at least two semiconductor power devices
US7880280B2 (en) 2007-02-16 2011-02-01 Infineon Technologies Ag Electronic component and method for manufacturing an electronic component
US8786072B2 (en) * 2007-02-27 2014-07-22 International Rectifier Corporation Semiconductor package
US8253241B2 (en) 2008-05-20 2012-08-28 Infineon Technologies Ag Electronic module
US8227908B2 (en) 2008-07-07 2012-07-24 Infineon Technologies Ag Electronic device having contact elements with a specified cross section and manufacturing thereof
US8519545B2 (en) 2010-09-17 2013-08-27 Infineon Technologies Ag Electronic device comprising a chip disposed on a pin

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101238562A (zh) * 2005-03-04 2008-08-06 国际整流器公司 半导体封装的制造
US20100297810A1 (en) * 2006-05-10 2010-11-25 Infineon Technologies Ag Power Semiconductor Device and Method for Its Production
US20100078783A1 (en) * 2008-09-30 2010-04-01 Infineon Technologies Ag Device including two mounting surfaces

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448746A (zh) * 2014-08-07 2016-03-30 北大方正集团有限公司 一种氮化镓器件及封装方法
CN105448746B (zh) * 2014-08-07 2018-03-23 北大方正集团有限公司 一种氮化镓器件及封装方法
CN107925404A (zh) * 2015-09-10 2018-04-17 古河电气工业株式会社 功率器件
CN108726467A (zh) * 2017-04-21 2018-11-02 英飞凌科技股份有限公司 具有高热容量的装置和用于制造该装置的方法
CN108726467B (zh) * 2017-04-21 2023-11-07 英飞凌科技股份有限公司 具有高热容量的装置和用于制造该装置的方法
CN109935561A (zh) * 2017-12-18 2019-06-25 镓能半导体（佛山）有限公司 一种氮化镓器件及氮化镓器件的封装方法
WO2020098590A1 (zh) * 2018-11-16 2020-05-22 苏州东微半导体有限公司 半导体功率器件

Also Published As

Publication number Publication date
DE102014101261A1 (de) 2014-08-07
DE102014101261B4 (de) 2020-01-23
CN103972193B (zh) 2017-04-12
US20140217596A1 (en) 2014-08-07
US9099441B2 (en) 2015-08-04

Similar Documents

Publication Publication Date Title
CN103972193B (zh) 功率晶体管装置和用于制造功率晶体管装置的方法
CN105981274B (zh) 电力用半导体模块
US9263440B2 (en) Power transistor arrangement and package having the same
CN104347618B (zh) 电子部件及方法
US10763246B2 (en) Device including a semiconductor chip monolithically integrated with a driver circuit in a semiconductor material
US20080017998A1 (en) Semiconductor component and method of manufacture
CN102005441A (zh) 混合封装栅极可控的半导体开关器件及制备方法
Zhao et al. Flexible epoxy-resin substrate based 1.2 kV SiC half bridge module with ultra-low parasitics and high functionality
TW201842639A (zh) 用於使串擾減至最小之積體電路連接配置
CN109698178A (zh) 半导体装置设备及其形成方法
CN104253118B (zh) 半导体封装件
CN109698180A (zh) 半导体器件和制造方法
CN114899170A (zh) 一种用于功率氮化镓hemt器件的4引脚to-247封装结构
CN104037152A (zh) 芯片载体结构、芯片封装及其制造方法
US10083942B2 (en) Electronic power device with vertical 3D switching cell
CN116230714A (zh) 氮化镓集成功率芯片及其制造方法
CN102361035A (zh) 一种无外延层的rf-ldmos器件结构
CN114864528A (zh) 半导体器件和半导体器件的制造方法
CN113410217A (zh) 一种双管芯合封的共源共栅SiC功率器件
TW202205570A (zh) 晶片封裝結構及其製造方法
Lee et al. A new package of high-voltage cascode gallium nitride device for high-frequency applications
US10199347B2 (en) Semiconductor device
CN111490030A (zh) 共源共栅半导体器件和制造方法
CN218160367U (zh) Cascode封装结构
US20240079297A1 (en) Semiconductor Package with Balanced Impedance

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant