CN103928513A - 一种沟槽dmos器件及其制作方法 - Google Patents

一种沟槽dmos器件及其制作方法 Download PDF

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CN103928513A
CN103928513A CN201310014452.0A CN201310014452A CN103928513A CN 103928513 A CN103928513 A CN 103928513A CN 201310014452 A CN201310014452 A CN 201310014452A CN 103928513 A CN103928513 A CN 103928513A
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CN103928513B (zh
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卞铮
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CSMC Technologies Fab2 Co Ltd
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Wuxi CSMC Semiconductor Co Ltd
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Priority to EP13871700.4A priority patent/EP2903028B1/en
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Abstract

一种沟槽型DMOS器件及其制作方法，该DMOS器件中将栅极沟槽从位于衬底上方的介质层中开始往衬底延伸，使得栅极多晶硅的有效截面积增加，从而减少了栅极电阻Rg。同时在本发明的制作方法中，由于在沟槽刻蚀之前就已经覆盖了介质层，因而取消了原先的源极注入工艺，转而将该源注入工艺和导电通孔在一次光刻中进行，减少了一步光刻，从而使得整个工艺更加简单。

Description

一种沟槽DMOS器件及其制作方法
技术领域
本发明涉及一种MOSFET晶体管，具体地说，是一种沟槽性DMOS器件及其制作方法。
背景技术
DMOS(双扩散型MOS)晶体管是MOSFET(金属氧化物半导体场效应晶体管)型的晶体管，其使用在相同边缘上对准的两个序列扩散步骤来形成晶体管的沟道区域。DMOS晶体管通常是高电压高电流的器件，在功率集成电路中用作分立的晶体管或元件。DMOS晶体管对于每个具有低前向压降的单元面积可以提供高电流。
典型的分立的DMOS晶体管结构包括两个或多个并行制造的单DMOS晶体管单元。单DMOS晶体管单元共享一个公共漏极触点(衬底)，而其源极共同与金属短接且其栅极公共被多晶硅短接。因此，即使分立的DMOS电路由较小的晶体管阵列构成，它运行起来也如单个大晶体管一样。对于分立的DMOS电路，当晶体管矩阵通过栅极接通时，希望能够使每个单元面积上的导电性达到最大。
DMOS晶体管的-个具体型是所谓的沟槽DMOS晶体管，其中沟道出现在从源极向漏极延伸的沟槽的内壁上，且栅极形成在沟槽内。与薄氧化物层形成一条直线且填充有多晶硅的沟槽比垂直DMOS晶体管结构允许有较少的受限电流流动，从而提供了较低的特定导通电阻值。沟槽DMOS晶体管的例子在美国专利5,072,266、5,541,425和5,866,931中公开。
图1示出了半六边形形状的现有技术的沟槽DMOS结构21。该结构包括n+衬底23，其上生长一具有预定深度depi的轻微掺杂n外延层25。在外延层25内，提供p主体区域27(p,p+)。如图中所示，p主体区域27是充分平坦的〈除了中央区域内)，位于距离外延层27顶部表面之下dmin处。覆盖大部分p主体区域27的另一层28（n+）作为源极。在外延层中设置一系列六边形的沟槽29，开口朝向顶部，具有一预定的深度dtr。沟槽29里典型地衬着氧化物，由有导电性的多晶硅填充，形成DMOS器件的栅极。沟槽29限定了元件区域31，该元件区域31在水平横截面内也呈六边形。在元件区域31内，p主体区域27上升至外延层的顶部表面，并在元件区域31的顶部表面上的水平横截面内形成一暴露图案33。在示出的具体设计中，p主体区域27的p+中心部分向外延层的表面之下延伸深度dmax，其远大于晶体管元件的沟槽深度dtr，以使击穿电压远离沟槽表面，而进入到半导体材料体中。
对于DMOS器件来说，栅极电阻决定了器件所能输出能力，通常为了得到大的输出电流，需要尽可能的减少栅极电阻Rg。现有的方法中，一种是通过增加沟槽的数量来减少Rg，然而这种方法对Rg的优化有限，而且随着沟槽的增加，不仅器件的尺寸会增加，其制作工艺也会变得更加复杂。
因此如何减少栅极电阻Rg，已经成为业界一个普遍关注的问题。
发明内容
有鉴于此，本发明的目的在于提出一种沟槽DMOS器件的结构以及制造这种DMOS器件的方法，该DMOS器件具有更低的栅极电阻Rg，该制作方法提供了制作上述沟槽DMOS器件的方案，并且相比较现有工艺，该制作方法采用更少的光刻工艺，节约成本。
根据本发明的目的提出的一种沟槽型DMOS器件，包括：
第一导电类型的衬底，该衬底作为所述器件的公共漏极区；
形成于所述衬底中的具有第二导电类型的有源区；
在所述衬底上的第一介质层；
以所述第一介质层表面延伸到所述衬底的多个沟槽，该多个沟槽包括相互连通的分布在所述有源区的至少一个第一沟槽和位于有源区外的第二沟槽；
填充于该多个沟槽中的导电材料；
设于多数导电材料和沟槽槽壁之间的氧化层；
位于有源区内邻近所述第一沟槽的源极区；
覆盖所述第一介质层和多个沟槽的第二介质层；
覆盖所述第二介质层上的金属层，该金属层包括彼此绝缘的第一电极区和第二电极区，所述第一电极区通过贯穿第一介质层和第二介质层的第一导电柱与所述源极区进行电连接，形成源极；所述第二电极区通过贯穿第二介质层的第二导电柱与所述第二沟槽中的导电材料进行电连接，形成栅极。
优选的，所述沟槽的深度大于所述有源区的深度。
优选的，所述衬底为N型衬底，所述有源区为P型有源区，所述源极区为重掺杂的N型区。
优选的，所述有源区底部正对于所述源极区下方，还设有重掺杂的P型区。
优选的，所述沟槽中的导电材料为多晶硅，所述氧化层为氧化硅。
优选的，所述第一导电柱和第二导电柱为钨。
优选的，所述衬底进一步包括多个P型分压环，设置于所述有源区的周围。
优选的，所述沟槽中的导电材料顶部，进一步包括氧化层，将所述导电材料与第二介质层隔绝。
优选的，所述第一介质层包括硼磷硅玻璃层和采用硅酸乙酯形成的氧化硅层。
根据本发明的另一目的提出的一种制作如上所述的沟槽型DMOS器件的方法，包括步骤：
有源区工艺：在第一导电型衬底上进行第二导电型掺杂，形成有源区；
沟槽刻蚀工艺：在上述衬底上制作第一介质层，并在第一介质层中刻蚀出多个沟槽，该多个沟槽从第一介质层表面延伸至衬底内部，并分为分布在有源区的至少一个第一沟槽和分布在非有源区的第二沟槽；
栅氧及栅多晶硅工艺：在所述沟槽的沟槽壁上形成氧化层，并在沟槽中填充多晶硅；
导电通孔工艺：在所述第一介质层及沟槽表面沉积第二介质层，并对第二介质层进行刻蚀，制作出贯穿第二介质层、第一介质层直至衬底的第一导电通孔，和贯穿第二介质层直至第二沟槽中的第二导电通孔，该第一导电通孔与第一沟槽的位置相邻；
源极区及导电柱工艺：通过所述第一导电通孔对有源区进行第一导电型重掺杂，形成源极区，在所有导电通孔中填充钨，形成第一导电柱和第二导电柱；
金属层工艺：在所述第二介质层上沉积金属层，并刻蚀分为第一电极区和第二电极区，所述第一电极区通过第一导电柱与所述源极区进行电连接，形成源极；所述第二电极区通过第二导电柱与所述第二沟槽中的导电材料进行电连接，形成栅极。
优选的，所述有源区工艺中，还包括在衬底有源区周围制作多个分压环的工艺。
优选的，所述源极区及导电柱工艺中，还包括在填充钨之前，通过第一导电通孔在有源区底部进行第二导电型重掺杂，该第二导电型重掺杂区形成在所述源极区的下方。
本发明提出的沟槽DMOS器件中，作为栅极区主体的沟槽是从第一介质层表面延伸至衬底，相比较现有的只在衬底中制作得到的沟槽，本发明的沟槽使得栅极多晶硅具有更大的截面积，从而有效减少了栅极电子Rg。并且在制作该器件时，将源极区的注入直接利用导电通孔进行，省略一步源注入的光刻，从而节省了生产工艺。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种现有的沟槽型DMOS器件的结构示意图；
图2是本发明的沟槽型DMOS器件结构示意图；
图3本发明制作沟槽型DMOS器件的流程示意图；
图4A-4F是上述方法中对应的器件剖面图。
具体实施方式
介于现有技术中，对于沟槽型DMOS器件很难有效减小栅极电阻Rg的难题，本发明提出了一种沟槽型DMOS器件及其制作方法。
在本发明中，将栅极沟槽从位于衬底上方的介质层中开始往衬底延伸，使得栅极多晶硅的有效截面积增加，从而减少了栅极电阻Rg。另外在制作上述器件时，由于在沟槽刻蚀之前就已经覆盖了介质层，因而取消了原先的源极注入工艺，转而将该源注入工艺和导电通孔在一次光刻中进行，减少了一步光刻，从而使得整个工艺更加简单。
下面将通过具体实施方式对本发明做详细说明。
请参见图2，图2是本发明的沟槽型DMOS器件的结构示意图。如图所示，该DMOS器件包括衬底100，该衬底100为第一导电类型，第一导电类型可以是N型，也可以是P型，视不同的器件作用而定。下文中以第一导电类型为N型为例。同其他沟槽型DMOS器件一样，衬底100作为器件的公共漏极区。形成于衬底100中的具有第二导电类型的有源区102，该有源区102是通过离子注入工艺，将第二导电类型的杂质掺杂到衬底100中，该第二导电类型比如是P型。进一步地，为了提高器件的击穿电压，在制作该有源区102时，往往会在一步离子注入工艺中同时在衬底100上制作出多个分压环103，这些分压环103分布在有源区102的周围，起到表面击穿保护的作用。
在衬底100上的第一介质层110，该第一介质层110通常包括采用化学气相淀积形成的硼磷硅玻璃层(BPSG)111和采用基于硅酸乙酯的化学气相沉积方法形成的二氧化硅（TEOS）层112。BPSG111制作在衬底100上，因其材质韧性高，且具可吸附杂质的特性，通常用作介质与硅表面接触的缓冲层，TEOS112制作在BPSG111上，其材质硬度高，绝缘性好，工艺适合批量生长，作为介质层的主体材料。
多个沟槽，这些沟槽从第一介质层110的表面延伸到衬底100中，该多个沟槽包括相互连通的分布在有源区102的至少一个第一沟槽141(图示中为3个)和位于有源区102外的第二沟槽142。第一沟槽141构成了DMOS器件的栅极主体，第二沟槽142则起到将栅极引出的作用，因此将该第二沟槽142做的比较大，并且为了便于制作栅极引出线，需要将该第二沟槽142制作在有源区102的外部，避免了与源极引出线的互相干扰。进一步的，沟槽往往需要做的比较深，比如达到1.1um，这样的深度一般大于有源区102的深度(0.8um左右)，这样有利于栅极电压对器件的控制。
在沟槽中，需要填充导电材料143形成栅极，该导电材料143一般为多晶硅，当然在一些特殊的应用场合，这些导电材料143也可以是铝、铜等金属。在该导电材料143和沟槽的沟槽壁之间，设有一层氧化层144，该氧化层144通常为氧化硅，起到栅氧的作用。进一步地，在沟槽中的导电材料143顶部，还包括一层氧化层145，将所述导电材料143与后续制作上去的第二介质层120隔绝。
在有源区102内通过离子注入工艺形成源极区104，源极区104一般为重掺杂的N型区，形成在第一沟槽的邻近位置。进一步地，还可以在有源区120底部对应源极区104的下方，通过离子注入工艺形成一个P型重掺杂区105，用以改善器件在开关瞬态的抗电涌冲击能力。
覆盖所述第一介质层110和多个沟槽的第二介质层120。
覆盖所述第二介质层120上的金属层130，该金属层130包括彼此绝缘的第一电极区131和第二电极区132，所述第一电极区131通过贯穿第一介质层110和第二介质层120的第一导电柱151与所述源极区104进行电连接，形成源极；所述第二电极区132通过贯穿第二介质层120的第二导电柱152与所述第二沟槽142中的导电材料143进行电连接，形成栅极。其中导电柱均通过金属层间连接线工艺制作而成，其导电材料为钨。
下面，再对上述沟槽型DMOS器件的制作方法进行说明。
请配合图4A-4F参见图3，图3是本发明沟槽型DMOS器件制作方法的流程示意图，图4A-4F是上述方法中对应的器件剖面图。如图所示，本发明的制作方法包括如下步骤：
S1：有源区工艺：在第一导电型衬底上进行第二导电型掺杂，形成有源区。该工艺具体包括步骤：
S11：提供一个N型衬底100，该衬底100比如是硅衬底。对该N型衬底100进行氧化，在表面生成氧化层，该氧化层起到后续离子注入时的缓冲保护作用。
S12：利用光刻工艺制作出用于离子注入的窗口：在上述衬底上涂布一层光刻胶101，以有源区掩模对光刻胶进行曝光显影，使光刻胶图形化，露出需要制作有源区的部分衬底。在该步骤中，所述有源区掩模上还可以包括分压环图形，这些分压环分布在有源区的周围，这样就可以在衬底上同步制作出分压环。
S13：以图形化后的光刻胶为掩模，对衬底进行P型离子注入。
S14：去除剩余光刻胶。
S15：对离子注入区进行推阱，使注入的离子扩散，形成有源区102。该步骤中同时可以形成分压环103，参见图4A。
S2：沟槽刻蚀工艺：在上述衬底上制作第一介质层110，并在第一介质层中110刻蚀出多个沟槽，该多个沟槽从第一介质层110表面延伸至衬底100内部，并分为分布在有源区102的至少一个第一沟槽141和分布在非有源区的第二沟槽142。该工艺的具体步骤包括：
S21：将步骤S11中形成的注入缓冲用的氧化层剥离；
S22：在剥离后的衬底上沉积第一介质层110，该第一介质层110可分为BPSG111层和TEOS112层。当然在其他一些场合下，该第一介质层也可以为一层或2层以上。
S23：利用光刻工艺在该第一介质层110上制作出用于沟槽刻蚀的窗口，具体的光刻工艺可以参见S12，这里不再赘述。
S24：利用步骤S23形成的窗口，对第一介质层110进行腐蚀，在该第一介质层110中先腐蚀出沟槽图形。
S25：去除步骤S24后剩余光刻胶，并利用第一介质层110上的沟槽图形为掩模，对衬底硅进行腐蚀，在衬底上制作出沟槽，从而完成整个沟槽的刻蚀，参见图4B。
S3：栅氧及栅多晶硅工艺：在所述沟槽的沟槽壁上形成氧化层144，并在沟槽中填充多晶硅143。该沟槽中的多晶硅143以及氧化层144构成了器件的栅极。参见图4C，从图中可以看出，在本发明中，整个栅极沟槽由于突出于衬底直至第一介质层110中，相比较普通的只在衬底中制作栅极沟槽的结构，本发明的栅极导电材料具有更大的截面积，因此其栅极电阻Rg可以被有效的减小。该工艺具体包括步骤：
S31：在步骤S25之后的衬底上制作一层牺牲氧化层；
S32：利用湿法腐蚀工艺将上述牺牲氧化层全剥；
S33：栅氧氧化工艺：在沟槽中制作出氧化层，该氧化层144一般为二氧化硅。
S34：利用多晶硅沉积工艺，在上述结构上沉积多晶硅，直至其覆盖整个表面，以使沟槽结构中充满多晶硅143。
S35：实施多晶硅/二氧化硅的高选择比干法腐蚀，将裸露在沟槽结构外部的多晶硅全部去除，直到腐蚀到达在沟槽表面的二氧化硅材质时停止。形成图4C的截面结构。
S4：导电通孔工艺：在所述第一介质层110及沟槽表面沉积第二介质层120，并对第二介质层120进行刻蚀，制作出贯穿第二介质层120、第一介质层110直至衬底100的第一导电通孔153，和贯穿第二介质层120直至第二沟槽142中的第二导电通孔154，该第一导电通孔153与第一沟槽141的位置相邻，参见图4D。
该工艺的具体步骤包括；
S41:多晶硅氧化，在沟槽开口的多晶硅顶面产生一层氧化层145。
S42：第二介质层沉积，在所述第一介质层110及沟槽表面沉积第二介质层120。
S43：利用光刻工艺在第二介质层表面制作出用于导电通孔刻蚀的窗口，具体的光刻工艺同样参见步骤S12。
S44：以步骤S43形成的窗口为掩模，对第二介质层120和第一介质层110进行二氧化硅/硅高选择比腐蚀，制作出导电通孔，该步骤中，在第二沟槽处的导电通孔，将上面的第二介质层120腐蚀之后，由于底部暴露多晶硅，腐蚀到此处即近乎终止。
S45：去除步骤S43中多余的光刻胶。
S5：源极区及导电柱工艺：通过所述第一导电通孔153对有源区102进行第一导电型重掺杂，形成源极区104，在所有导电通孔中填充钨，形成第一导电柱151和第二导电柱152，参见图4E。
该工艺具体包括步骤：
S51：通过上述第一导电通孔153对硅衬底100进行N型离子注入及快速热退火工艺，形成N型的重掺杂区，即源极区104。
S52：以第二介质层120为掩膜对第一导电通孔对应的硅衬底100表面进行硅腐蚀，使第一导电通孔153延伸到硅衬底100中，使第二导电通孔154延伸至第二沟槽142中。进一步地，还可以通过第一导电通孔153在有源区102底部进行第二导电型重掺杂，该第二导电型重掺杂区105形成在所述源极区104的下方，起到改善器件抗开关态的浪涌冲击能力的作用。
S53：在步骤S52之后的衬底上沉积钛、氮化钛层，作为导电柱缓冲层。
S54：对所有的导电通孔进行钨填充，形成导电柱。然后进行化学机械研磨，去除孔外的钨。
S6：金属层工艺：在所述第二介质层120上沉积金属层130，并刻蚀分为第一电极区131和第二电极区132，所述第一电极区131通过第一导电柱151与所述源极区104进行电连接，形成源极；所述第二电极区132通过第二导电柱152与所述第二沟槽中的导电材料进行电连接，形成栅极。
该工艺具体包括步骤：
S61：在步骤S54之后的衬底表面进行金属沉积，该金属比如是Al。
S62：利用光刻工艺上述金属表面形成用以制作第一电极区和第二电极区的窗口。该具体地光刻工艺参考步骤S12.
S63：通过步骤S62形成的窗口对金属进行腐蚀，形成第一电极区和第二电极区，然后去除多余的光刻胶。
S64：最后进行合金工艺。
需要说明的是，在本发明制作方法中采用的各个半导体工艺，比如离子注入工艺或者各层沉积工艺，都是目前的常规手段，所以本发明未做详细说明。然而本领域技术人员可以根据本发明提到的方法进行实施，且作为常规手段，上述方法中提及的各个工艺可以采用相同目的不同手段的其它工艺进行替代。
对于本发明而言，其进步之处主要在于：
第一：作为栅极区主体的沟槽是从第一介质层表面延伸至衬底，相比较现有的只在衬底中制作得到的沟槽，本发明的沟槽使得栅极多晶硅具有更大的截面积，从而有效减少了栅极电子Rg。
第二：在制作该器件时，本发明总共采用了4步光刻工艺，相比较现有技术，本发明将源极区的注入直接利用导电通孔进行，省略一步源注入的光刻，从而节省了生产工艺。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (12)

1.一种沟槽型DMOS器件，其特征在于，包括：
第一导电类型的衬底，该衬底作为所述器件的公共漏极区；
形成于所述衬底中的具有第二导电类型的有源区；
在所述衬底上的第一介质层；
以所述第一介质层表面延伸到所述衬底的多个沟槽，该多个沟槽包括相互连通的分布在所述有源区的至少一个第一沟槽和位于有源区外的第二沟槽；
填充于该多个沟槽中的导电材料；
设于多数导电材料和沟槽槽壁之间的氧化层；
位于有源区内邻近所述第一沟槽的源极区；
覆盖所述第一介质层和多个沟槽的第二介质层；
覆盖所述第二介质层上的金属层，该金属层包括彼此绝缘的第一电极区和第二电极区，所述第一电极区通过贯穿第一介质层和第二介质层的第一导电柱与所述源极区进行电连接，形成源极；所述第二电极区通过贯穿第二介质层的第二导电柱与所述第二沟槽中的导电材料进行电连接，形成栅极。
2.如权利要求1所述的沟槽型DMOS器件，其特征在于：所述沟槽的深度大于所述有源区的深度。
3.如权利要求1所述的沟槽型DMOS器件，其特征在于：所述衬底为N型衬底，所述有源区为P型有源区，所述源极区为重掺杂的N型区。
4.如权利要求3所述的沟槽型DMOS器件，其特征在于：所述有源区底部正对于所述源极区下方，还设有重掺杂的P型区。
5.如权利要求1所述的沟槽型DMOS器件，其特征在于：所述沟槽中的导电材料为多晶硅，所述氧化层为氧化硅。
6.如权利要求1所述的沟槽型DMOS器件，其特征在于：所述第一导电柱和第二导电柱为钨。
7.如权利要求1所述的沟槽型DMOS器件，其特征在于：所述衬底进一步包括多个P型分压环，设置于所述有源区的周围。
8.如权利要求1所述的沟槽型DMOS器件，其特征在于：所述沟槽中的导电材料顶部，进一步包括氧化层，将所述导电材料与第二介质层隔绝。
9.如权利要求1所述的沟槽型DMOS器件，其特征在于：所述第一介质层包括硼磷硅玻璃层和采用硅酸乙酯形成的氧化硅层。
10.一种制作权利要求1所述的沟槽型DMOS器件的方法，其特征在于，包括步骤：
有源区工艺：在第一导电型衬底上进行第二导电型掺杂，形成有源区；
沟槽刻蚀工艺：在上述衬底上制作第一介质层，并在第一介质层中刻蚀出多个沟槽，该多个沟槽从第一介质层表面延伸至衬底内部，并分为分布在有源区的至少一个第一沟槽和分布在非有源区的第二沟槽；
栅氧及栅多晶硅工艺：在所述沟槽的沟槽壁上形成氧化层，并在沟槽中填充多晶硅；
导电通孔工艺：在所述第一介质层及沟槽表面沉积第二介质层，并对第二介质层进行刻蚀，制作出贯穿第二介质层、第一介质层直至衬底的第一导电通孔，和贯穿第二介质层直至第二沟槽中的第二导电通孔，该第一导电通孔与第一沟槽的位置相邻；
源极区及导电柱工艺：通过所述第一导电通孔对有源区进行第一导电型重掺杂，形成源极区，在所有导电通孔中填充钨，形成第一导电柱和第二导电柱；
金属层工艺：在所述第二介质层上沉积金属层，并刻蚀分为第一电极区和第二电极区，所述第一电极区通过第一导电柱与所述源极区进行电连接，形成源极；所述第二电极区通过第二导电柱与所述第二沟槽中的导电材料进行电连接，形成栅极。
11.如权利要求10所述的制作方法，其特征在于：所述有源区工艺中，还包括在衬底有源区周围制作多个分压环的工艺。
12.如权利要求10所述的制作方法，其特征在于：所述源极区及导电柱工艺中，还包括在填充钨之前，通过第一导电通孔在有源区底部进行第二导电型重掺杂，该第二导电型重掺杂区形成在所述源极区的下方。
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