CN103918076A - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN103918076A
CN103918076A CN201380003722.6A CN201380003722A CN103918076A CN 103918076 A CN103918076 A CN 103918076A CN 201380003722 A CN201380003722 A CN 201380003722A CN 103918076 A CN103918076 A CN 103918076A
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CN
China
Prior art keywords
electrode
copper connector
substrate
gate electrode
engagement portion
Prior art date
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Granted
Application number
CN201380003722.6A
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English (en)
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CN103918076B (zh
Inventor
须永崇
金子昇
三好修
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NSK Ltd
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NSK Ltd
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Publication of CN103918076A publication Critical patent/CN103918076A/zh
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Publication of CN103918076B publication Critical patent/CN103918076B/zh
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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Abstract

半导体模块(30)具有通过焊锡(34b、34c)使形成于晶体管裸芯片(35)的上表面的电极(S、G)和多个布线图案(33a～33d)中的布线图案(33b、33c)接合的铜连接器(36a、36b)。铜连接器(36bb)具有与晶体管裸芯片(35)的电极(G)接合的电极接合部(36bb)和与电极接合部(36bb)以相对置的方式而配置的、与布线图案(33c)接合的基板接合部(36bc)。电极接合部(36bb)的与单向正交的方向上的宽度W1比基板接合部(36bb)的与单向正交的方向上的宽度W2窄。

Description

半导体模块
技术领域
本发明涉及一种组装于汽车用电气设备的功率模块等半导体模块。
背景技术
近来，在汽车等车辆中的各种电气设备的控制中逐渐引入了电子装置。作为组装有电子装置的电气设备的一例，在电动助力转向装置中，在容纳与汽车的转向相关的电动马达的壳体内设置有马达驱动部，将电子装置搭载于该马达驱动部。该电子装置作为功率模块组装于马达驱动部。
功率模块由作为适于电动助力转向装置那样的以比较大的电流驱动的电气设备的控制、例如搭载了FET(Field Effect Transistor)、IGBT(Insulated Gate BipolarTransistor)等功率元件的所谓的半导体模块而构成。这种功率模块由于搭载于车辆而也被称作车载模块(In-vehicle Module)。
以往，作为这种半导体模块，例如，已知有图17所示的半导体模块(参照专利文献1)。图17是表示以往的半导体模块的一个例子的截面示意图。
图17所示的半导体模块100具有：金属制的基板101；在基板101的凹部的底部平整面上设置的树脂102；以及形成于树脂102上的多个铜箔(布线图案)103a、103b、103c、103d。在铜箔103a及铜箔103c与铜箔103d之间形成有槽109。而且，在多个铜箔103a、103b、103c、103d中的铜箔103a、103b之上，分别形成有热缓冲板104a、104b，在热缓冲板104a，104b上，分别形成有IGBT105a、105b。各IGBT105a、105b是IGBT裸芯片(晶体管裸芯片)。
而且，利用由金属线构成的布线106a将IGBT105a的发射极和铜箔103b接合，另外，利用同样由金属线构成的布线106b将IGBT105b的发射极和铜箔103c接合。
另外，利用凝胶107将树脂102、铜箔103a、103b、103c、热缓冲板104a、104b、IGBT105a、105b、及布线106a、106b装入。另外，将覆盖基板101凹部的蓋108固定于基板101的上部。
另外，作为以往的半导体模块的另一例，如图18所示的半导体模块(参照专利文献2)也为大家所知。图18是表示以往的半导体模块的另一例的截面图。
图18所示的半导体模块200中，在由铝等构成的散热用基底板201上焊接有绝缘基板202。而且，在形成于绝缘基板202上的金属薄板上焊接有IGBT203的集电极电极205。
一方面，在半导体模块200中，布线部件206是由铜等高导电性金属材料构成的平板部件，包括：与IGBT203的发射极电极204相对置的电极相对部206A；从电极相对部206A向上方弯折而竖起的竖起部206B；以及从该竖起部206B延伸的导出部206C。该导出部206C与未图示的外部连接端子连接。而且，在导出部206C中设置有波状的弯折部206D。该弯折部206D吸收该布线部件206与散热用基底板201之间的热膨胀差，作为缓和热应力的应力缓和部而发挥作用。
而且，构成为，利用导电性树脂207将布线部件206的电极相对部206A和IGBT203的发射极电极204接合。与焊锡等接合用导电材料相比，该导电性树脂207的弹性系数低，因此，能够有效地缓和热应力。
并且，作为以往的半导体模块的其他例子，例如，已知有图19所示的半导体模块(参照专利文献3)。图19是表示以往的半导体模块的其他例子的俯视示意图。
在图19所示的半导体模块300中，基板(未图示)上形成有多个导电焊盘301、302。而且，多个导电焊盘301、302中的一个导电焊盘301上焊接有MOS芯片303。另外，在MOS芯片303的上表面形成有多个源电极305及单一的栅电极304，在MOS芯片203的下表面形成有未图示的漏电极。
而且，利用引线310将MOS芯片303的源电极305和形成于基板上的多个导电焊盘301、302中的另一个导电焊盘302相互接合。通过对金属板进行冲压及弯曲加工、即压制成形来形成引线310。引线310包括：沿图19所示的X方向及Y方向(水平方向)延伸的矩形平板状的源电极接合部311；沿X方向及Y方向延伸的平板状的电极接合部312；以及将源电极接合部311和电极接合部312连接的向Z方向(垂直方向)倾斜的连结部313。在此，源电极接合部311与MOS芯片303的源电极305焊接，另外，电极接合部312与基板上的多个导电焊盘301、302中的其他导电焊盘302焊接。设置有一对其他导电焊盘302，电极接合部312具有一对的支脚部形状，以与这些一对的导电焊盘302接合。
而且，源电极接合部311的X方向的宽度a为在多个源电极305的X方向的宽度b以上。由此，可以防止源电极305中不均匀的焊锡润湿和该焊锡的回流引起的相对于该源电极305的位移。
现有技术文献
专利文献
专利文献1：JP2004-335725A
专利文献2：JP2000-124398A
专利文献3：JP2007-95984A
发明内容
发明要解决的问题
但是，图17所示的这些以往的半导体模块100、图18所示的半导体模块200、及图19所示的半导体模块300存在以下的问题。
即，在图17所示的半导体模块100的情况下，对于IGBT105a的发射极和铜箔103b之间的接合及IGBT105b的发射极和铜箔103c之间的接合，是使用由金属线构成的布线106a、106b进行接合。由于使用引线接合装置(未图示)来进行该使用了金属线的接合，所以在封装布线106a、106b的作业中，需要通过与将IGBT105a、105b或其他基板封装部件封装于基板上的布线图案时进行的焊锡封装作业不同的制造工序，进行引线接合。因此，存在制造节拍变长，并且需要引线接合的专用设备，制造成本变高之类的问题。
另外，对于图18所示的半导体模块200，在将布线部件206的电极相对部206A与IGBT203的发射极电极204接合时，未触及其布线部件203的站立性。因此，当在回流炉等中将布线部件206的电极相对部206A与IGBT203的发射极电极204接合时，布线部件206有可能倾倒。特别是，布线部件206中，在其导出部206C设置有作为应力缓和部的波状的弯折部206D，在IGBT203上，布线部件206的平衡较差，而成为易倾倒的形状。另外，对于半导体模块，近年来，有小型化的要求，为了其小型化，也要求IGBT203及布线部件206的小型化。随着IGBT203及布线部件206的小型化发展，则需要提高组装性，但是，若布线部件206的站立性存在问题，则组装性不会提高。
一方面，在图19所示的半导体模块300的情况下，引线310的源电极接合部311的X方向的宽度a在多个源电极305的X方向的宽度b以上，而成为宽的形状。其另一方面，与导电焊盘302焊接的引线310的电极接合部312具有一对支脚部形状。因此，引线310形成平衡比较好的形状，所以，在通过回流进行将引线310与MOS芯片303及基板上焊接时，发生引线310倾倒的可能性小。
但是，由于引线310的源电极接合部311的X方向的宽度a在多个源电极305的X方向的宽度b以上而成为宽的形状，所以，若通过压制成形而扭歪了，则源电极接合部311不在适当的位置与源电极305接触，焊接中的位置精度变得非常差。因此，存在以下的问题：被焊接的源电极接合部311与源电极305的接合可靠性也变得极低。
因此，本发明是为了解决这些问题而完成的，其目的在于，提供通过使用铜连接器的焊锡封装作业进行晶体管裸芯片的电极和基板上的布线图案之间的接合，从而能够通过与将晶体管裸芯片或其他基板封装部件封装于基板上的布线图案时进行的焊锡封装作业相同的工序同时进行，并且，能够在可靠地确保铜连接器的焊锡封装作业中的站立性的基础上使软钎焊接中的铜连接器的配置位置精度良好的半导体模块。
用于解决课题的方案
为了解决上述问题，本发明的某个方式的半导体模块中，具有：金属制的基板；形成于该基板之上的绝缘层；形成于该绝缘层上的多个布线图案；通过焊锡封装于该多个布线图案中的一个布线图案的晶体管裸芯片；以及用于通过焊锡使形成于该晶体管裸芯片的上表面的电极和所述多个布线图案中的其他布线图案接合的、由铜板构成的铜连接器。所述铜连接器具有：与所述晶体管裸芯片的电极接合的电极接合部；以及与该电极接合部在单向上以相对置的方式配置的、与所述多个布线图案中的其他布线图案接合的基板接合部。而且，所述电极接合部的与所述单向正交的方向上的宽度比所述基板接合部的与所述单向正交的方向上的宽度窄。
根据该半导体模块，通过使用由铜板构成的铜连接器，从而能够通过焊锡封装作业进行晶体管裸芯片的电极和基板上的布线图案之间的接合。因此，能够通过与将晶体管裸芯片或其他基板封装部件封装于基板上的布线图案时进行的焊锡封装作业相同的工序同时进行晶体管裸芯片的电极和基板上的布线图案之间的接合。因此，能够缩短半导体模块的制造节拍，并且，不需要引线接合的专用设备，可以降低半导体模块的制造成本。
而且，铜连接器中的电极接合部的与单向正交的方向上的宽度比基板接合部的与单向正交的方向上的宽度窄，所以，能够利用窄幅的电极接合部侧的1点、和宽幅的基板接合部侧的2点共计3点，使铜连接器在晶体管裸芯片及基板的上表面站立。因此，在通过回流将铜连接器焊接在晶体管裸芯片及基板上时，能够减少铜连接器倾倒的可能性。进而，由于能够利用窄幅的电极接合部侧的1点、和宽幅的基板接合部侧的2点共计3点，使铜连接器在晶体管裸芯片及基板上站立，所以即使由于压制成形而扭歪，电极接合部也在适当的位置与晶体管裸芯片的电极接触，焊接中的位置精度良好。因此，能够较高地维持被焊接的电极接合部和晶体管裸芯片的电极的接合可靠性。此外，为了晶体管裸芯片的小型化，优选，使在其上表面形成的电极小。即使使电极接合部的宽度比基板接合部的宽度窄，在晶体管裸芯片所形成的电极小的情况下，接合的可靠性也没有问题。
另外，在该半导体模块中，所述电极接合部也可以位于所述基板接合部的与所述单向正交的宽度方向的大致中央部。
根据该半导体模块，由于电极接合部位于基板接合部的与单向正交的宽度方向的大致中央部，所以宽度窄的电极接合部相对于基板接合部的宽度方向位于平衡好的位置。因此，当铜连接器利用宽度窄的电极接合部端的1点、和宽度宽的基板接合部端的2点共计3点，在晶体管裸芯片及基板上站立时，电极接合部的位置的平衡良好，所以能够提高铜连接器的站立性。
进而，在该半导体模块中，在所述电极接合部和所述基板接合部之间也可以设置应力缓和部。
根据该半导体模块，通过应力缓和部，能够吸收晶体管裸芯片和铜连接器之间的线膨胀系数之差、基板和铜连接器之间的线膨胀系数之差、以及晶体管裸芯片和基板之间的线膨胀系数之差。因此，能够缓和针对晶体管裸芯片和铜连接器之间的焊接部及铜连接器和基板之间的焊接部的热应力，能够确保铜连接器相对于晶体管裸芯片及基板的接合可靠性。而且，若在电极接合部和基板接合部之间设置应力缓和部，则应力缓和部一般由波形等构成，所以，铜连接器成为难以站立的形状。但是，通过使铜连接器的电极接合部的与单向正交的方向上的宽度比基板接合部的与单向正交的方向上的宽度窄，能够利用宽度窄的电极接合部端的1点、和宽度宽的基板接合部端的2点共计3点使铜连接器在晶体管裸芯片及基板上站立，所以保证了铜连接器的站立性。
另外，在该半导体模块中，所述应力缓和部也可以形成为，具备平板部、以从该平板部的一端朝向下方延伸的方式弯折的第一连结部、以及以从所述平板部的另一端朝向下方延伸的方式弯折的第二连结部，而形成桥形，所述电极接合部从所述第一连结部弯折而向外侧延伸，所述基板接合部从所述第二连结部弯折而向外侧延伸。
根据该半导体模块，应力缓和部构成朝向上方的帽子形状的桥，所以能够充分地发挥作为应力缓和部的作用。
进而，在该半导体模块中，所述第一连结部也可以形成为从所述平板部到所述电极接合部为止宽度逐渐变细的锥状，将所述电极接合部的弯曲基点设为所述第一连结部的最细的部位。
根据该半导体模块，电极接合部的弯曲基点为锥状的第一连结部的最细的部位，所以容易变形。因此，对于焊接等，在由于晶体管裸芯片和铜连接器之间的线膨胀系数之差、基板和铜连接器之间的线膨胀系数之差、晶体管裸芯片和基板之间的线膨胀系数之差而使铜连接器发生变形时，电极接合部的弯曲基点能够容易地变形。由此，能够确保电极接合部相对于晶体管裸芯片的电极的接合可靠性。
进而，在该半导体模块中，也可以在所述平板部的与所述单向正交的方向的两端分别形成有平衡肋部，该平衡肋部以从该两端朝向下方延伸的方式弯折而成。
由于平衡肋部，铜连接器的重心下降而改善了站立性，在铜连接器利用宽度窄的电极接合部侧的1点、和宽度宽的基板接合部侧的2点共计3点，在晶体管裸芯片及基板的上表面站立时，其站立性向稳定的方向改善。因此，在利用回流将铜连接器焊接在晶体管裸芯片及基板上时，能够可靠地避免铜连接器的倾倒，能够稳定地进行焊接。
进而，在该半导体模块中，也可以是，所述铜连接器的所述电极接合部及所述基板接合部的厚度比所述铜连接器的其他部分的厚度大。
由于上述电极接合部及上述基板接合部的厚度厚，从而铜连接器的重心位置变低，站立性得到改善。因此，在铜连接器利用宽度窄的电极接合部侧的1点、和宽度宽的基板接合部侧的2点共计3点，在晶体管裸芯片及基板的上表面站立时，其站立性向稳定的方向改善。因此，在利用回流将铜连接器焊接在晶体管裸芯片及基板上时，能够可靠地避免铜连接器的倾倒，能够稳定地进行焊接。
另外，在该半导体模块中，所述晶体管裸芯片是在上表面形成有源电极及接合面积比该源电极小的栅电极的FET裸芯片，所述铜连接器也可以是将该铜连接器的电极接合部与所述栅电极接合的栅电极用铜连接器。
根据该半导体模块，将宽度窄的电极接合部与面积小的栅电极接合，所以，将铜连接器设为栅电极用铜连接器是有效的。
另外，本发明的其他方式涉及的半导体模块的特征在于，铜连接器利用宽度窄的电极接合部端的1点、和宽度宽的基板接合部端的2点共计3点，在晶体管裸芯片及基板的上表面站立，当在晶体管裸芯片及基板上利用回流进行焊接时，能够避免铜连接器的倾倒。
发明效果
根据本发明的半导体模块，通过使用由铜板构成的铜连接器，从而能够通过焊锡封装作业进行晶体管裸芯片的电极和基板上的布线图案之间的接合，因此，能够通过与将晶体管裸芯片或其他基板封装部件封装于基板上的布线图案时进行的焊锡封装作业相同的工序同时进行晶体管裸芯片的电极和基板上的布线图案之间的接合。因此，能够缩短半导体模块的制造节拍，并且，不需要引线接合的专用设备，可以降低半导体模块的制造成本。
另外，铜连接器的电极接合部的与单向正交的方向上的宽度比基板接合部的与单向正交的方向上的宽度窄，所以，能够利用宽度窄的电极接合部端的1点、和宽度宽的基板接合部端的2点共计3点，使铜连接器在晶体管裸芯片及基板的上表面站立，因此，在通过回流将铜连接器焊接在晶体管裸芯片及基板上时，能够减少铜连接器倾倒的可能性。
进而，由于能够利用宽度窄的电极接合部端的1点、和宽度宽的基板接合部端的2点共计3点，使铜连接器在晶体管裸芯片和基板之间站立，所以即使由于压制成形而扭歪，电极接合部也在适当的位置与晶体管裸芯片的电极接触，焊接中的位置精度良好。因此，能够较高地维持被焊接的电极接合部和晶体管裸芯片的电极的接合可靠性。
另外，由于以从所述平板部的与所述单向正交的方向的两端朝向下方延伸的方式弯折的平衡肋部，使得铜连接器的重心进一步下降而改善了站立性。因此，晶体管裸芯片及基板的上表面上的铜连接器的站立性向稳定的方向改善，在利用回流将铜连接器焊接在晶体管裸芯片及基板上时，能够可靠地避免铜连接器的倾倒，能够稳定地进行焊接。
附图简要说明
图1是表示使用本发明的半导体模块的电动助力转向装置的基本结构的图。
图2是表示图1所示的电动助力转向装置的控制器的控制系统的方框图。
图3是图1所示的电动助力转向装置的包含半导体模块的控制器的分解立体图。
图4是图3所示的半导体模块的俯视图。
图5是用于说明在图3及图4所示的半导体模块中构成晶体管裸芯片的FET裸芯片的电极和基板上的布线图案之间的接合状态的示意图。
图6是FET裸芯片的概略俯视图。
图7表示栅电极用铜连接器，(A)是从左侧面斜上方观察到的栅电极用铜连接器的状态的立体图，(B)是从右侧面斜上方观察到的栅电极用铜连接器的状态的立体图。另外，(C)是从左侧面斜上方观察到的具有平衡肋部的栅电极用铜连接器的状态的立体图，(D)是从右侧面斜上方观察到的具有平衡肋部的栅电极用铜连接器的状态的立体图。进而，(E)是从左侧面斜上方观察到的电极接合部及基板接合部的厚度较大的栅电极用铜连接器的状态的立体图，(F)是从右侧面斜上方观察到的电极接合部及基板接合部的厚度较大的栅电极用铜连接器的状态的立体图。
图8表示栅电极用铜连接器，(A)是俯视图，(B)是主视图，(C)是右侧视图，(D)是左侧视图。
图9是用于说明半导体模块的制造工序的图。
图10表示栅电极用铜连接器的第一变形例，(A)是左侧视图，(B)是俯视图。
图11表示栅电极用铜连接器的第二变形例，(A)是左侧视图，(B)是俯视图。
图12表示栅电极用铜连接器的第三变形例，(A)是左侧视图，(B)是俯视图。
图13是表示图8所示的栅电极用铜连接器以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例中应用的应力缓和部的第一变形例的图。
图14是表示图8所示的栅电极用铜连接器以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例中应用的应力缓和部的第二变形例的图。
图15是表示图8所示的栅电极用铜连接器以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例中应用的应力缓和部的第三变形例的图。
图16是表示图8所示的栅电极用铜连接器以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例中应用的应力缓和部的第四变形例的图。
图17是以往的半导体模块的一例的截面示意图。
图18是表示以往的半导体模块的其他例的截面图。
图19是表示以往的半导体模块的另外其他例的俯视示意图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。图1是表示使用本发明的半导体模块的电动助力转向装置的基本结构的图。图2是表示图1所示的电动助力转向装置的控制器的控制系统的方框图。图3是图1所示的电动助力转向装置的包含半导体模块的控制器的分解立体图。图4是图3所示的半导体模块的俯视图。图5是用于说明在图3及图4所示的半导体模块中构成晶体管裸芯片的FET裸芯片的电极和基板上的布线图案之间的接合状态的示意图。图6是FET裸芯片的概略俯视图。
图1中，表示使用本发明的半导体模块的电动助力转向装置的基本结构，电动助力转向装置中，方向盘1的柱轴2经由减速齿轮3、万向接头4A及4B、齿轮齿条机构5与转向轮的拉杆6连结。在柱轴2上设置有对方向盘1的转向转矩进行检测的转矩传感器7，辅助方向盘1的转向力的电动马达8通过减速齿轮3而与柱轴2连结。对控制电动助力转向装置的控制器10，从电池(未图示)供电的同时，经由点火钥匙(未图示)输入点火钥匙信号IGN(参照图2)。控制器10根据由转矩传感器7检测到的转向转矩Ts和由车速传感器9检测到的车速V，进行助推(转向辅助)指令的转向辅助指令值的运算，根据运算出的转向辅助指令值控制向电动马达8供给的电流。
控制器10主要由微型计算机构成，但是，若表示其控制装置的机构及构成，则如图2所示。
由转矩传感器7检测到的转向转矩Ts及由车速传感器9检测到的车速V输入到作为控制运算部的控制运算装置11，将由控制运算装置11算出的电流指令值输入到门极驱动电路12。将在门极驱动电路12中，根据电流指令值等形成的门极驱动信号输入到FET的桥结构所构成的马达驱动部13，马达驱动部13经由用于紧急停止的切断装置14驱动由三相无刷马达构成的电动马达8。由电流检测电路15来检测三相无刷马达的各相电流，将检测出的三相的马达电流ia～ic作为反馈电流输入到控制运算装置11。另外，三相无刷马达中安装有霍尔传感器等旋转传感器16，将来自旋转传感器16的旋转信号RT输入到转子位置检测电路17，将检测到的旋转位置θ输入到控制运算装置11。
另外，将来自点火钥匙的点火信号IGN输入到点火电压监视部18及电源电路部19，从电源电路部19输入电源电压Vdd到控制运算装置11的同时，向控制运算装置11输入用于装置停止的复位信号Rs。而且，切断装置14由对2相进行切断的继电器触点141及142构成。
另外，若对马达驱动部13的电路构成进行说明，则串联连接的FETTr1及Tr2、FETTr3及Tr4、以及FETTr5及Tr6相对于电源线81串联连接。而且，相对于电源线81并联连接的FETTr1及Tr3、FETTr5及Tr2、以及FETTr4及Tr6与接地线82连接。由此，构成逆变器。在此，FETTr1及Tr2中，FETTr1的源电极S和FETTr2的漏电极D串联连接而构成三相马达的c相臂，在c相输出线91c输出电流。另外，FETTr3及Tr4，与FETTr3的源电极S和FETTr4的漏电极D串联连接而构成三相马达的a相臂，在a相输出线91a输出电流。进而，FETTr5及Tr6，与FETTr5的源电极S和FETTr6的漏电极D串联连接而构成三相马达的b相臂，在b相输出线91b输出电流。
接着，图3是图1所示的电动助力转向装置的包含半导体模块的控制器10的分解立体图，控制器10具有外壳20、作为包含马达驱动部13的功率模块的半导体模块30、散热用薄板39、包含控制运算装置11及门极驱动电路12的控制电路基板40、电力及信号用连接器50、三相输出用连接器60、和盖70。
在此，外壳20具有：形成为大致矩形状并用于放置半导体模块30的平板状的半导体模块载置部21；设置于半导体模块载置部21的长度方向端部并用于封装电力及信号用连接器50的电力及信号用连接器封装部22；以及设置于半导体模块载置部21的宽度方向端部并用于封装三相输出用连接器60的三相输出用连接器封装部23。
而且，在半导体模块载置部21形成有旋进用于安装半导体模块30的安装螺钉38的多个螺钉孔21a。另外，在半导体模块载置部21以及电力及信号用连接器封装部22垂直安装有用于安装控制电路基板40的多个安装柱子24，在各安装柱子24形成有旋进用于安装控制电路基板40的安装螺钉41的螺钉孔24a。进而，在三相输出用连接器封装部23形成有旋进用于安装三相输出用连接器60的安装螺钉61的多个螺钉孔23a。
另外，半导体模块30具有上述马达驱动部13的电路构成，如图4所示，在基板31上封装有6个FETTr1～Tr6、与电源线81连接的正极端子81a、及与接地线82连接的负极端子82a。另外，在基板31上封装有三相输出部90，该三相输出部90包括与a相输出线91a连接的a相输出端子92a、与b相输出线91b连接的b相输出端子92b以及与c相输出线91c连接的c相输出端子92c。另外，在基板31上封装有包括电容的其他基板封装部件37。并且，在半导体模块30的基板31上设置有用于安装半导体模块30的安装螺钉38进行插入的多个通孔31a。
在此，对在该半导体模块30中向基板31上封装6个FETTr1～Tr6进行说明。各FETTr1～Tr6由FET裸芯片(晶体管裸芯片)35构成，如图6所示，在FET裸芯片35上具备源电极S和栅电极G，另外，在FET裸芯片35的下表面具有未图示的漏电极。
如图6所示，形成于该FET裸芯片35的上表面的栅电极G和源电极S沿图6中的上下方向被串联直线配置。栅电极G形成为具有沿图6中的垂直方向延伸的短边及与该短边正交的长边的长方形。另外，源电极S形成为具有沿图6中的垂直方向延伸的短边及与该短边正交的长边的长方形。源电极S的短边及长边比栅电极G的短边及长边大，源电极S的面积比栅电极G的面积大。
如图5所示，半导体模块30具有金属制的基板31，在基板31之上形成有绝缘层32。基板31是由铝等金属制成。另外，在该绝缘层32上形成有多个布线图案33a～33d。各布线图案33a～33d由铜或铝等金属或包含该金属的合金构成。而且，在多个布线图案33a～33d中的一个布线图案33a上，通过焊锡34a，封装有构成各FETTr1～Tr6的FET裸芯片35。在FET裸芯片35的下表面所形成的漏电极，通过焊锡34a与布线图案33a接合。而且，利用源电极用铜连接器36a分别通过焊锡34e、34b使FET裸芯片35的源电极S上和多个布线图案33a～33d中的其他布线图案33b上接合。利用栅电极用铜连接器36b分别通过焊锡34f、34c使FET裸芯片35的源电极G上和多个布线图案33a～33d中的还有其他布线图案33c上接合。
在此，源电极用铜连接器36a是通过对铜板进行冲压及弯曲加工、即压制成形而形成的。而且，如图5所示，源电极用铜连接器36a包括平板部36aa、从平板部36aa一端延伸并通过焊锡34e与FET裸芯片35的源电极S接合的电极接合部36ab、以及从平板部36aa的另一端延伸并通过焊锡34b与布线图案33b接合的基板接合部36ac。基板接合部36ac与电极接合部36ab在单(图5中的左右方向)上以相对置的方式而配置。
一方面，栅电极用铜连接器36b是通过对铜板进行冲压及弯曲加工、即压制成形而形成的，如图5所示，包括通过焊锡34f与FET裸芯片35的栅电极G接合的电极接合部36bb、以及通过焊锡34c与布线图案33c接合的基板接合部36bc。基板接合部36bc与电极接合部36bb在单向(图5中的左右方向)上以相对置的方式而配置。
在此，如图8(A)所示，电极接合部36bb的与所述一个方向正交的方向上的宽度W1比基板接合部36bc的与所述单向正交的方向上的宽度W2窄。
这样，通过使栅电极用铜连接器36b的电极接合部36bb的与单向正交的方向上的宽度W1比基板接合部36bc的与单向正交的方向上的宽度W2窄，能够利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点(基板接合部36bc的宽度方向两端附近的2点)共计3点，使栅电极用铜连接器36b在FET裸芯片35及基板31的上表面站立。因此，如后述那样，在利用回流将栅电极用铜连接器36b焊接在FET裸芯片35及基板31上时，能够减少栅电极用铜连接器36b发生倾倒的可能性。由此，即使将FET裸芯片35及栅电极用铜连接器36b小型化，也能够使其组装性良好。
另外，能够使栅电极用铜连接器36b利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点共计3点，在FET裸芯片35及基板31上站立。因此，即使由于压制成形而扭歪，电极接合部36bb也在适当的位置与FET裸芯片的栅电极G接触，焊点的配置位置精度良好。因此，能够较高地维持被焊接的电极接合部36bb与FET裸芯片35的栅电极G的接合可靠性。此外，为了FET裸芯片35的小型化，优选使在其上表面形成的栅电极G小。即使使电极接合部36bb的宽度比基板接合部36bc的宽度窄，在FET裸芯片35所形成的栅电极G小的情况下，接合的可靠性没有问题。
此外，对于栅电极用铜连接器36b，使电极接合部36bb及基板接合部36bc的两者为窄幅，利用宽度窄的电极接合部36bb端的1点、和宽度窄的基板接合部36bc端的1点共计2点，使其在FET裸芯片35及基板31上站立的情况下，栅电极用铜连接器36b非常容易倾倒。
另外，栅电极用铜连接器36b的电极接合部36bb位于基板接合部36bc的与所述单向正交的宽度方向的大致中央部。由此，宽度窄的电极接合部36bb相对于基板接合部36bc的宽度方向位于平衡好的位置。因此，在栅电极用铜连接器36b利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点共计3点，在FET裸芯片35和基板31上站立时，由于电极接合部36bb的位置的平衡良好，因此，能够提高栅电极用铜连接器36b的站立性。
另外，对于栅电极用铜连接器36b，如图7(A)、图7(B)及图8(A)、图8(B)、图8(C)、图8(D)所示，在电极接合部36bb和基板接合部36bc之间设置有应力缓和部36bj。
该应力缓和部36bj包括平板部36ba、以从平板部36ba的一端借助于第一弯曲部36bf朝向下方延伸的方式弯折的第一连结部36bd、以及以从平板部36ba的另一端借助于第三弯曲部36bh朝向下方延伸的方式弯折的第二连结部36be，而形成为桥形(构成为朝向上方的帽子形状的桥)。而且，形成为，电极接合部36bb从第一连结部36bd借助于第二弯曲部36bg弯折而向外侧延伸，基板接合部36bc从第二连结部36be借助于第四弯曲部36bi弯折而向外侧延伸。
这样，通过在电极接合部36bb与基板接合部36bc之间设置应力缓和部36bj，从而能够吸收FET裸芯片35和栅电极用铜连接器36b之间的线膨胀系数之差、基板31和栅电极用铜连接器36b之间的线膨胀系数之差、FET裸芯片35和基板31之间的线膨胀系数之差。因此，能够缓和针对FET裸芯片35与栅电极用铜连接器36b之间的焊接部及栅电极用铜连接器36b与基板31、即布线图案33c之间的焊接部的热应力，能够确保栅电极用铜连接器36b相对于FET裸芯片35及基板31的接合可靠性。顺便说明一下，基板31是铝材，其线膨胀系数为23.6×10-6/℃左右、栅电极用铜连接器36b的线膨胀系数为16.8×10-6/℃左右、FET裸芯片是硅，其线膨胀系数为2.5×10-6/℃左右。
一方面，若在电极接合部36bb和基板接合部36bc之间设置应力缓和部36bj，则一般应力缓和部由波形等构成(本实施方式中为桥形)，栅电极用铜连接器36b为难以站立的形状。但是，通过使栅电极用铜连接器36b的电极接合部36bb的与单向正交的方向上的宽度W1比基板接合部36bc的与单向正交的方向上的宽度W2窄，能够使栅电极用铜连接器36b利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点共计3点在FET裸芯片35及基板31上站立，因此，保证了栅电极用铜连接器36b的站立性。
另外，由于以朝向上方的帽子形状的桥来构成应力缓和部36bj，所以，能够充分地发挥作为应力缓和部的作用。
进而，如图7(A)及图8(D)表示的那样，栅电极用铜连接器36b的第一连结部36bd形成为从平板部36ba到电极接合部36bb为止宽度逐渐变细的锥状，将电极接合部36bb的弯曲基点、即第二弯曲部36bg的基点设为第一连结部36bd的最细部位。
这样，由于电极接合部36bb的弯曲基点是锥状的第一连结部36bd的最细部位，所以容易变形。因此，对于焊接等，由于FET裸芯片35和栅电极用铜连接器36b之间的线膨胀系数之差、基板31和栅电极用铜连接器36b之间的线膨胀系数之差、FET裸芯片35和基板31之间的线膨胀系数之差而使栅电极用铜连接器36b发生变形时，电极接合部36bb的弯曲基点能够容易地变形。由此，能够确保电极接合部36bb相对于栅电极G的接合可靠性。
进而，对于栅电极用铜连接器36b，如图7(C)及图7(D)所示，也可以在电极接合部36bb和基板接合部36bc之间设置的平板部36ba的与上述一个方向正交的方向的两端，分别形成有以从该两端朝向下方延伸的方式弯折的平衡肋部36bk。
由于该平衡肋部36bk，栅电极用铜连接器36b的重心位置下降，栅电极用铜连接器36b的站立性得以改善。因此，在栅电极用铜连接器36b利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点共计3点，在晶体管裸芯片及基板的上表面站立时，其站立性向稳定的方向改善。因此，在利用回流将栅电极用铜连接器36b焊接在晶体管裸芯片及基板上时，能够可靠地避免栅电极用铜连接器36b的倾倒，能够提高软钎焊接的可靠性。
进而，对于栅电极用铜连接器36b，如图7(E)及图7(F)所示，栅电极用铜连接器36b的电极接合部36bb及基板接合部36bc的板厚也可以比栅电极用铜连接器36b的其他部分(即，平板部36ba、第一连结部36bd、第二连结部36be)的板厚大。电极接合部36bb及基板接合部36bc的板厚的大小不被特别限定，但是，例如，也可以是栅电极用铜连接器36b的其他部分(即，平板部36ba、第一连结部36bd、第二连结部36be)的板厚的大约3倍。
通过使电极接合部36bb及基板接合部36bc的板厚变大，从而栅电极用铜连接器36b的重心位置变低，站立性得到改善。因此，在栅电极用铜连接器36b利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点共计3点，在晶体管裸芯片及基板的上表面站立时，其站立性被向稳定的方向改善。因此，在利用回流将栅电极用铜连接器36b焊接在晶体管裸芯片及基板上时，能够可靠地避免栅电极用铜连接器36b的倾倒，能够提高软钎焊接的可靠性。
此外，图5所示的半导体模块30中，在形成于绝缘层32上的多个布线图案33a～33d中的其他布线图案33d上，通过焊锡34d封装有电容等其他基板封装部件37。
这样构成的半导体模块30如图3所示，通过多个安装螺钉38安装于外壳20的半导体模块载置部21上。在半导体模块30的基板31上形成有安装螺钉38进行插入的多个通孔31a。
此外，在将半导体模块30安装于半导体模块载置部21上时，将散热用薄板39安装于半导体模块载置部21上，从该散热用薄板39之上安装半导体模块30。利用该散热用薄板39，将半导体模块30产生的热量通过散热用薄板39向外壳20散热。
另外，控制电路基板40用于将多个电子器件封装于基板上而构成包含控制运算装置11及栅极驱动电路12的控制电路。在将半导体模块30安装于半导体模块载置部21上后，利用多个安装螺钉41在从半导体模块30的上方垂直安装于半导体模块载置部21以及电力及信号用连接器封装部22的多个安装柱子24上安装控制电路基板40。在控制电路基板40上形成有安装螺钉41进行插入的多个通孔40a。
另外，电力及信号用连接器50用于将来自电池(未图示)的直流电源输入到半导体模块30，将包含来自转矩传感器12和车速传感器9的信号的各种信号输入到控制电路基板40。利用多个安装螺钉51在设置于半导体模块载置部21的电力及信号用连接器封装部22安装电力及信号用连接器50。
而且，三相输出用连接器60用于输出来自a相输出端子92a、b相输出端子92b及c相输出端子92c的电流。利用多个安装螺钉61在设置于半导体模块载置部21的宽度方向端部的三相输出用连接器封装部23安装三相输出用连接器60。在三相输出连接器60形成有安装螺钉61进行插入的多个通孔60a。
并且，相对于安装有半导体模块30、控制电路基板40、电力及信号用连接器50及三相输出用连接器60的外壳20，以从控制电路基板40的上方覆盖该控制电路基板40的方式安装盖70。
接着，参照图9对半导体模块30的制造工序进行说明。
在制造半导体模块30时，如图9(A)所示，首先，在金属制的基板31的一方的主面上形成绝缘层32(绝缘层形成工序)。
接着，如图9(A)所示，在绝缘层32上形成多个布线图案33a～33d(布线图案形成工序)。
之后，如图9(B)所示，在多个布线图案33a～33d上分别涂抹焊膏(焊锡34a～34d)(焊膏涂抹工序)。
而且，如图9(C)所示，在多个布线图案33a～33d中的一个布线图案33a上所涂抹的焊膏(焊锡34a)上搭载一个FET裸芯片35(FET裸芯片搭载工序)，并且在其他布线图案33d上所涂抹的焊膏(焊锡34d)上搭载其他基板封装部件37。即使对于其他FET裸芯片35，也将其搭载于与布线图案33a相同的或者另外的布线图案。
接着，如图9(D)所示，在形成于FET裸芯片35的上表面的源电极S及栅电极G上涂抹焊膏(焊锡34e，34f)(焊膏涂抹工序)。
之后，如图9(E)所示，在涂抹于FET裸芯片35的源电极S上的焊膏(焊锡34e)上、以及涂抹于多个布线图案33a～33d中的搭载了FET裸芯片35的布线图案33a以外的其他布线图案33b上的焊膏(焊锡34b)上，搭载源电极用铜连接器36a(源电极用铜连接器搭载工序)。
另外，如图9(E)所示，在涂抹于FET裸芯片35的栅电极G上的焊膏(焊锡34f)上、以及涂抹于多个布线图案33a～33d中的搭载了FET裸芯片35的布线图案33a及搭载了源电极用铜连接器36a的布线图案33b以外的另外其他布线图案33c上的焊膏(焊锡34c)上，搭载栅电极用铜连接器36b(栅电极用铜连接器搭载工序)。由此，构成半导体模块中间组装体。
而且，将通过以上工序构成的半导体模块中间组装体放入回流炉(未图示)，集中进行如下的接合(接合工序)，即，通过焊锡34a将多个布线图案33a～33d中的一个布线图案33a和FET裸芯片35接合、通过焊锡34d将布线图案33d和其他基板封装部件37接合、通过焊锡34e将FET裸芯片35的上表面所形成的源电极S和源电极用铜连接器36a接合、将多个布线图案33a～33d中的其他布线图案33b和源电极用铜连接器36a接合、通过焊锡34f将FET裸芯片35的上表面所形成的栅电极G和栅电极用铜连接器36b接合、以及通过焊锡34c将多个布线图案33a～33d中的另外其他布线图案33c和栅电极用铜连接器36b接合。
由此，制成半导体模块30。
在此，通过对FET裸芯片35的源电极S和基板31上的布线图案33b之间的接合使用源电极用铜连接器36a，对FET裸芯片35的栅电极G和基板31上的另外的布线图案33c之间的接合使用栅电极用铜连接器36b，从而可以通过焊锡封装作业进行该接合，所以，可以通过与将FET裸芯片35或其他基板封装部件37封装于基板31上的布线图案33a、33d上时进行的焊锡封装作业相同的工序同时进行FET裸芯片35的源电极S和基板31上的布线图案33b之间的接合以及FET裸芯片35的栅电极G和基板31上的另外的布线图案33c之间的接合。因此，可以缩短半导体模块30的制造节拍，并且不需要引线接合的专用设备，可以降低半导体模块30的制造成本。
另外，在回流炉中的接合工序中，栅电极用铜连接器36b的电极接合部36bb的与单向正交的方向上的宽度W1比基板接合部36bc的与单向正交的方向上的宽度W2窄，栅电极用铜连接器36b能够利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点(基板接合部36bc的宽度方向两端附近的2点)共计3点，在FET裸芯片35及基板31的上表面站立。因此，在利用回流将栅电极用铜连接器36b焊接在FET裸芯片35及基板31上时，能够减少栅电极用铜连接器36b倾倒的可能性。由此，即使使FET裸芯片35及栅电极用铜连接器36b小型化，也能够使其组装性良好。
接着，参照图10对栅电极用铜连接器的第一变形例进行说明。
图10所示的栅电极用铜连接器36b1的基本构成与图8所示的栅电极用铜连接器36b相同，但是，基板接合部36bc、第二连结部36be、平板部、第一连结部36bd、及电极接合部36bb的形状不同。
即，对于栅电极用铜连接器36b1，在进行压制成形的冲压时，使基板接合部36bc、第二连结部36be、平板部、第一连结部36bd、及电极接合部36bb成型为从两侧均匀地使宽度变窄的锥形，之后，进行弯折而构成栅电极用铜连接器36b1。
即使对于该栅电极用铜连接器36b1，也使栅电极用铜连接器36b1的电极接合部36bb的与单向正交的方向上的宽度比基板接合部36bc的与单向正交的方向上的宽度窄，栅电极用铜连接器36b1能够利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点(基板接合部36bc的宽度方向两端附近的2点)共计3点，在FET裸芯片35及基板31的上表面站立。因此，在利用回流将栅电极用铜连接器36b1焊接在FET裸芯片35及基板31上时，能够减少栅电极用铜连接器36b1倾倒的可能性。由此，即使使FET裸芯片35及栅电极用铜连接器36b小型化，也能够使其组装性良好。
另外，栅电极用铜连接器36b1的电极接合部36bb位于基板接合部36bc的与所述单向正交的宽度方向的大致中央部。由此，宽度窄的电极接合部36bb相对于基板接合部36bc的宽度方向位于平衡好的位置。因此，当栅电极用铜连接器36b1利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点共计3点，在FET裸芯片35和基板31上站立时，由于电极接合部36bb的位置的平衡良好，所以能够提高栅电极用铜连接器36b1的站立性。
接着，参照图11对栅电极用铜连接器的第二变形例进行说明。
图11所示的栅电极用铜连接器36b2的基本构成与图8所示的栅电极用铜连接器36b相同，但是，第一连结部36bd的形状及电极接合部36bb的位置不同。
即，对于栅电极用铜连接器36b2，如图11(A)所示，第一连结部36bd的一侧边沿平板部36ba的一侧边呈直线状延伸，另一侧边以第一连结部36bd的宽度逐渐变窄的方式向上述一侧边倾斜地延伸。而且，电极接合部36bb位于在基板接合部36bc的宽度方向上靠近上述一侧边的位置。
即使对于该栅电极用铜连接器36b2，也使栅电极用铜连接器36b2的电极接合部36bb的与单向正交的方向上的宽度比基板接合部36bc的与单向正交的方向上的宽度窄，栅电极用铜连接器36b2能够利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点(基板接合部36bc的宽度方向两端附近的2点)共计3点，在FET裸芯片35及基板31的上表面站立。因此，在利用回流将栅电极用铜连接器36b2焊接在FET裸芯片35及基板31上时，能够减少栅电极用铜连接器36b2倾倒的可能性。由此，即使使FET裸芯片35及栅电极用铜连接器36b小型化，也能够使其组装性良好。
另外，如上述那样，栅电极用铜连接器36b2的电极接合部36bb位于在基板接合部36bc的宽度方向上靠近上述一侧边的位置，平衡差。但是，利用平板部36ba的宽度(重量)调整栅电极用铜连接器36b2的站立性的平衡。由此，宽度窄的电极接合部36bb相对于基板接合部36bc的宽度方向，其平衡变好，在栅电极用铜连接器36b2利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点共计3点，在FET裸芯片35和基板31上站立时，能够提高栅电极用铜连接器36b2的站立性。
进而，参照图12对栅电极用铜连接器的第三变形例进行说明。
图12所示的栅电极用铜连接器36b3的基本构成与图8所示的栅电极用铜连接器36b相同，但是，基板接合部36bc、第二连结部36be、平板部、第一连结部36bd、及电极接合部36bb的形状不同。
即，对于栅电极用铜连接器36b3，在进行压制成形的冲压时，使基板接合部36bc、第二连结部36be、平板部、第一连结部36bd、及电极接合部36bb成型为从一侧单方面地使宽度变窄的锥形，之后，进行弯折来构成栅电极用铜连接器36b3。
即使对于该栅电极用铜连接器36b3，也使栅电极用铜连接器36b3的电极接合部36bb的与单向正交的方向上的宽度比基板接合部36bc的与单向正交的方向上的宽度窄，栅电极用铜连接器36b3能够利用宽度窄的电极接合部36bb端的1点、和宽度宽的基板接合部36bc端的2点(基板接合部36bc的宽度方向两端附近的2点)共计3点，在FET裸芯片35及基板31的上表面站立。因此，在利用回流将栅电极用铜连接器36b3焊接在FET裸芯片35及基板31上时，能够减少栅电极用铜连接器36b2倾倒的可能性。由此，即使使FET裸芯片35及栅电极用铜连接器36b小型化，也能够使其组装性良好。
另外，栅电极用铜连接器36b3的电极接合部36bb位于在基板接合部36bc的宽度方向上靠近一侧边的位置，但是，利用锥状的第一连结部36bd与平板部36ba连结，平衡比较好。
接着，参照图13对图8所示的栅电极用铜连接器及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例中应用的应力缓和部的第一变形例进行说明。
对图8所示的栅电极用铜连接器36b以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例36b1、36b2、36b3，都能够应用图13所示的栅电极用铜连接器36b的应力缓和部36bj的形状，应力缓和部36bj形成为以上方凸起的方式弯曲的弯曲形状。而且，形成为，电极接合部36bb从应力缓和部36bj的一端部弯折而向外侧延伸，基板接合部36bc从应力缓和部36bj的另一端部弯折而向外侧延伸。
即使这样使应力缓和部36bj形成为以上方凸起的方式弯曲的弯曲形状，也能够吸收FET裸芯片35和栅电极用铜连接器36b之间的线膨胀系数之差、基板31和栅电极用铜连接器36b之间的线膨胀系数之差、FET裸芯片35和基板31之间的线膨胀系数之差。
另外，参照图14，对图8所示的栅电极用铜连接器以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例中应用的应力缓和部的第二变形例进行说明。
对图8所示的栅电极用铜连接器36b以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例36b1、36b2、36b3，都能够应用图14所示的栅电极用铜连接器36b的应力缓和部36bj的形状，应力缓和部36bj形成上方凸起的三角形状。形成为，电极接合部36bb从应力缓和部36bj的倾斜度小的一片的端部弯折而向外侧延伸，基板接合部36bc从应力缓和部36bj的倾斜度大的一片的端部弯折而向外侧延伸。
即使这样使应力缓和部36bj形成为上方凸起的三角形状，也能够吸收FET裸芯片35和栅电极用铜连接器36b之间的线膨胀系数之差、基板31和栅电极用铜连接器36b之间的线膨胀系数之差、FET裸芯片35和基板31之间的线膨胀系数之差。
进而，参照图15，对图8所示的栅电极用铜连接器以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例中应用的应力缓和部的第三变形例进行说明。
对图8所示的栅电极用铜连接器36b以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例36b1、36b2、36b3，都能够应用图15所示的栅电极用铜连接器36b的应力缓和部36bj的形状，应力缓和部36bj形成为向斜上方倾斜的直线状。而且，形成为，电极接合部36bb从应力缓和部36bj的上侧的一端部弯折而向外侧延伸，基板接合部36bc从应力缓和部36bj的下侧的另一端部弯折而向外侧延伸。
即使这样使应力缓和部36bj形成为向斜上方倾斜的直线状，也能够吸收FET裸芯片35和栅电极用铜连接器36b之间的线膨胀系数之差、基板31和栅电极用铜连接器36b之间的线膨胀系数之差、FET裸芯片35和基板31之间的线膨胀系数之差。
另外，参照图16，对图8所示的栅电极用铜连接器以及图10乃至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例中应用的应力缓和部的第四变形例进行说明。
对图8所示的栅电极用铜连接器36b以及图10至图12所示的栅电极用铜连接器的第一变形例乃至第三变形例36b1、36b2、36b3，都能够应用图16所示的栅电极用铜连接器36b的应力缓和部36bj的形状，应力缓和部36bj形成上方凸起的三角形状。与图15所示的应力缓和形状36bj不同，形成为，电极接合部36bb从应力缓和部36bj的倾斜度大的一片的端部弯折而向外侧延伸，基板接合部36bc从应力缓和部36bj的倾斜度小的一片的端部弯折而向外侧延伸。
即使这样使应力缓和部36bj形成为上方凸起的三角形状，也能够吸收FET裸芯片35和栅电极用铜连接器36b之间的线膨胀系数之差、基板31和栅电极用铜连接器36b之间的线膨胀系数之差、FET裸芯片35和基板31之间的线膨胀系数之差。
以上，对本发明的实施方式进行了说明，但是，本发明不限定于此，可以进行各种变更、改进。
例如，在半导体模块30中使用了FET裸芯片35，但不限于FET裸芯片35，也可以使用IGBT裸芯片等其他晶体管裸芯片。而且，在使用其他晶体管裸芯片的情况下，只要利用铜连接器，通过焊锡使形成于晶体管裸芯片的上表面的电极和多个布线图案中的接合了晶体管裸芯片的布线图案以外的其他布线图案接合即可。由此，可以通过与将晶体管裸芯片或其他基板封装部件封装于基板上的布线图案时进行的焊接作业相同的工序同时进行晶体管裸芯片的电极和基板上的布线图案之间的接合。
而且，在作为晶体管裸芯片使用IGBT裸芯片的情况下，优选，使用铜连接器通过焊锡分别将形成于IGBT裸芯片上的发射极电极及栅电极接合于基板上的布线图案。
这样，当使用IGBT裸芯片并分别使用铜连接器将在IGBT裸芯片上形成的发射极电极及栅电极通过焊锡与基板上的布线图案接合的情况下，可以通过与将IGBT裸芯片或其他基板封装部件封装于基板上的布线图案时进行的焊接作业相同的工序同时进行IGBT裸芯片的发射极电极和基板上的布线图案之间的接合、以及IGBT裸芯片的栅电极和基板上的另外的布线图案之间的接合。
另外，表示出了对栅电极用铜连接器36b应用本发明的铜连接器的例，但是，也可以将本发明的铜连接器应用于源电极用铜连接器36a。
进而，对于应用本发明的栅电极用铜连接器36b，只要电极接合部36bb的与单向正交的方向上的宽度W1比基板接合部36bc的与单向正交的方向上的宽度W2窄即可，不限于图8、图10至图12、以及图13至图16所示的例子。
进而，在半导体模块30中，栅电极用铜连接器是一个种类，源电极用铜连接器是相对于栅电极用铜连接器进行180°直线配置的第一源电极用铜连接器(参照图4的Tr2及Tr4)和相对于栅电极用铜连接器进行90°直角配置的第二源电极用铜连接器(参照图4的Tr1、Tr3、及Tr5)这两个种类，在一个FET裸芯片中，可以将一个种类的栅电极用铜连接器与从两个种类的第一源电极用铜连接器及第二源电极用铜连接器中选择的任意一方的源电极用铜连接器组合进行。
此外，对于第一源电极用铜连接器相对于栅电极用铜连接器的配置(栅电极用铜连接器和第一源电极用铜连接器所成的角度)，优选设为95～265°，更优选设为160～200°，更进一步优选设为175～185°，最优选设为180°。
另外，对于第二源电极用铜连接器相对于栅电极用铜连接器的配置(栅电极用铜连接器和第二源电极用铜连接器所成的角度)，优选设为5～175°，更优选设为70～120°，更进一步优选设为85～95°，最优选设为90°。
根据该半导体模块，与所述的半导体模块30同样，封装于基板上的晶体管裸芯片的配置上产生自由度，基板上的布线的设计自由度增大，可以使基板上的半导体模块的布局紧凑。并且，可以容易地使基板上的三相马达的各相路径的长度相同。由此，可以容易地使三相马达的各相特性、特别是各相的阻抗特性一致，能够提高转矩和速度等的脉动精度。
符号说明
1 方向盘
2 柱轴
3 减速齿轮
4A、4B 万向接头
5 齿轮齿条机构
6 拉杆
7 转矩传感器
8 电动马达
9 车速传感器
10 控制器
11 控制运算装置
12 门极驱动电路
13 马达驱动部
14 紧急停止用的切断装置
15 电流检测电路
16 旋转传感器
17 转子位置检测电路
18IGN 电压监视部
19 电源电路部
20 外壳
21 半导体模块载置部
21a 螺钉孔
22 电力及信号用连接器封装部
23 三相输出用连接器封装部
23a 螺钉孔
24 安装柱子
24a 螺钉孔
30 半导体模块
31 基板
31a 通孔
32 绝缘层
33a～33d 布线图案
34a～34d 焊锡
35FET 裸芯片(晶体管裸芯片)
36a 源电极用铜连接器
36aa 平板部
36ab 电极接合部
36ac 基板接合部
36b 栅电极用铜连接器
36ba 平板部
36bb 电极接合部
36bc 基板接合部
36bd 第一连结部
36be 第二连结部
36bf 第一弯曲点
36bg 第二弯曲点
36bh 第三弯曲点
36bi 第四弯曲点
36bj 应力缓和部
36bk 平衡肋部
36b1 栅电极用铜连接器(第一变形例)
36b2 栅电极用铜连接器(第二变形例)
36b3 栅电极用铜连接器(第三变形例)
37 基板封装部件
38 安装螺钉
39 散热用薄板
40 控制电路基板
40a 通孔
41 安装螺钉
50 电力及信号用连接器
51 安装螺钉
60 三相输出用连接器
60a 贯通孔
61 安装螺钉
70 盖
81 电源线
81a 正极端子
82 接地线
82a 负极端子
90 三相输出部
91a a 相输出线
91b b 相输出线
91c c 相输出线
G 栅电极(电极)
S 源电极(电极)

Claims (8)

1.一种半导体模块，其特征在于，
具有：金属制的基板；形成于该基板之上的绝缘层；形成于该绝缘层上的多个布线图案；通过焊锡封装于该多个布线图案中的一个布线图案的晶体管裸芯片；以及用于通过焊锡使形成于该晶体管裸芯片的上表面的电极和所述多个布线图案中的其他布线图案接合的、由铜板构成的铜连接器，
所述铜连接器具备：与所述晶体管裸芯片的电极接合的电极接合部；以及相对于该电极接合部在单向上以相对置的方式配置的、与所述多个布线图案中的其他布线图案接合的基板接合部，
所述电极接合部的与所述单向正交的方向上的宽度比所述基板接合部的与所述单向正交的方向上的宽度窄。
2.根据权利要求1所述的半导体模块，其特征在于，
所述电极接合部位于所述基板接合部的与所述单向正交的宽度方向的大致中央部。
3.根据权利要求1或2所述的半导体模块，其特征在于，
在所述电极接合部和所述基板接合部之间设置有应力缓和部。
4.根据权利要求3所述的半导体模块，其特征在于，
所述应力缓和部形成为，具有平板部、以从该平板部的一端朝向下方延伸的方式弯折的第一连结部、以及以从所述平板部的另一端朝向下方延伸的方式弯折的第二连结部，而形成桥形，所述电极接合部从所述第一连结部弯折而向外侧延伸，所述基板接合部从所述第二连结部弯折而向外侧延伸。
5.根据权利要求4所述的半导体模块，其特征在于，
所述第一连结部形成为从所述平板部到所述电极接合部为止宽度逐渐变细的锥状，将所述电极接合部的弯曲基点设为所述第一连结部的最细的部位。
6.根据权利要求4或5所述的半导体模块，其特征在于，
在所述平板部的与所述单向正交的方向的两端分别形成有平衡肋部，该平衡肋部以从该两端朝向下方延伸的方式弯折而成。
7.根据权利要求4至6中的任意一项所述的半导体模块，其特征在于，
所述铜连接器的所述电极接合部及所述基板接合部的厚度比所述铜连接器的其他部分的厚度大。
8.根据权利要求1至7中的任意一项所述的半导体模块，其特征在于，
所述晶体管裸芯片是在上表面形成有源电极及接合面积比该源电极小的栅电极的FET裸芯片，所述铜连接器是将该铜连接器的电极接合部与所述栅电极接合的栅电极用铜连接器。
CN201380003722.6A 2012-11-05 2013-10-25 半导体模块 Expired - Fee Related CN103918076B (zh)

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