CN105474386A - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN105474386A
CN105474386A CN201480046107.8A CN201480046107A CN105474386A CN 105474386 A CN105474386 A CN 105474386A CN 201480046107 A CN201480046107 A CN 201480046107A CN 105474386 A CN105474386 A CN 105474386A
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CN
China
Prior art keywords
flat part
board connector
electrode
engagement portion
metallic board
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Granted
Application number
CN201480046107.8A
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English (en)
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CN105474386B (zh
Inventor
须永崇
金子昇
三好修
铃木良一
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NSK Ltd
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NSK Ltd
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Application filed by NSK Ltd filed Critical NSK Ltd
Priority to CN201810417475.9A priority Critical patent/CN108565254B/zh
Publication of CN105474386A publication Critical patent/CN105474386A/zh
Application granted granted Critical
Publication of CN105474386B publication Critical patent/CN105474386B/zh
Expired - Fee Related legal-status Critical Current
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    • H01L24/41Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
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Abstract

提供基于焊锡的电连接的可靠性较高并且廉价的半导体模块。电极接合部(36bb)的与裸芯片FET(35)的栅电极(G)的被接合面对置的接合面以及基板接合部(36bc)的与其他的布线图案(33c)的被接合面对置的接合面具备脱气排出机构,该脱气排出机构使在金属板连接器(36b)的焊接时熔融的焊锡中产生的脱气从介于接合面与被接合面之间的焊锡(34c、34f)排出。

Description

半导体模块
技术领域
本发明涉及一种组装于汽车用电气设备的功率模块等半导体模块。
背景技术
近来,在汽车等车辆中的各种电气设备的控制中逐渐引入了电子装置。作为组装有电子装置的电气设备的一例,在电动助力转向装置中,在容纳与汽车的转向相关的电动马达的壳体内设置有马达驱动部,将电子装置搭载于该马达驱动部。该电子装置作为功率模块组装于马达驱动部。
功率模块构成为适于电动助力转向装置那样的以比较大的电流驱动的电气设备的控制的、例如搭载了FET(FieldEffectTransistor:场效应晶体管)、IGBT(InsulatedGateBipolarTransistor:绝缘栅双极型晶体管)等功率元件的所谓的半导体模块。这种功率模块由于搭载于车辆而也被称作车载模块(In-vehicleModule)。
在制造这样的半导体模块时,通过焊接将功率元件安装于基板上,但是,在专利文献1、2中,公开有如下技术:使用呈弧形状的金属片将半导体芯片和引线框电连接。即,将呈弧形状的金属片搭在半导体芯片的电极焊盘和引线框的内引线部上,将金属片与半导体芯片的电极焊盘之间、以及金属片与引线框的内引线部之间分别焊接,由此,将半导体芯片安装于引线框。
现有技术文献
专利文献
专利文献1:日本特开2011-243752号公报
专利文献2:日本特开2012-212712号公报
专利文献3:日本特开2006-114571号公报
发明内容
发明要解决的课题
但是,在专利文献1、2中公开的技术中,金属片的接合面与半导体芯片的电极焊盘的被接合面及引线框的内引线部的被接合面分别平行。因此,从焊接时熔融的焊锡中产生的脱气(outgas)容易作为气泡而留在介于所述接合面和所述被接合面之间的焊锡中,不容易从焊锡中排出。其结果,由于介于所述接合面和所述被接合面之间的焊锡中的空隙产生率高,基于焊锡的电连接的可靠性下降,电阻变高,因此,当例如100A的高电流流过时,可能产生过热、着火等问题。
在专利文献3中,公开了如下技术:在TQFP(ThinQuadFlatPackage:薄塑封四角扁平安装)等表面安装型的半导体装置中,在对半导体装置的外部连接用的引线进行焊接时,从熔融的焊锡中产生的脱气容易从焊锡中排出。即,由于在引线的前端部的4个面(上表面、下表面及两侧面)以前端部变得尖细的方式设有锥部,因此,从焊接时熔融的焊锡中产生的脱气的气泡借助引线的下表面的锥部与相邻的气泡结合并且沿着下表面的锥部朝向引线的前端部移动,而从焊锡排出。
此外,由于熔融的焊锡不仅容易顺着下表面的锥部而浸润扩散,还容易顺着引线的侧面的锥部和引线的侧面表面而浸润扩散,进而,也容易向引线的上表面的锥部浸润扩散,因此,焊锡与引线的前端部的4个面整体接合。其结果,由于接合面积变大,因此,基于焊锡的电连接的可靠性提高。
但是,在专利文献3中公开的技术中,由于需要对引线的前端部的4个面进行加工来设置锥部,因此,存在制造成本上升的问题。
因此,本发明的课题在于,解决上述那样的现有技术所具有的问题点,提供一种提高基于焊锡的电连接的可靠性并且廉价的半导体模块。
用于解决课题的手段
为了解决所述课题,本发明的一个方式的半导体模块具备:金属制的基板、形成于所述基板上的绝缘层、形成于所述绝缘层上的多个布线图案、在所述多个布线图案中的一个布线图案上借助焊锡而安装的裸芯片晶体管以及将形成于所述裸芯片晶体管的上表面的电极与所述多个布线图案中的其他的布线图案接合的由金属板构成的金属板连接器。
所述金属板连接器具备如下部分而呈桥形:平板部;电极接合部,其配置于所述平板部的一个方向的一端侧,借助焊锡与所述裸芯片晶体管的电极接合;基板接合部,其配置于所述平板部的所述一个方向的另一端侧,借助焊锡与所述其他布线图案接合;第一连结部,其从所述平板部的所述一个方向的一端向下延伸,并且将所述平板部的所述一个方向的一端与所述电极接合部的一端连结;以及第二连结部,其从所述平板部的所述一个方向的另一端向下延伸,并且将所述平板部的所述一个方向的另一端与所述基板接合部的一端连结。
此外,所述电极接合部形成为从所述第一连结部被弯折而向所述一个方向的外侧延伸,所述基板接合部形成为从所述第二连结部被弯折而向所述一个方向的外侧延伸。
而且,所述电极接合部的与所述裸芯片晶体管的电极的被接合面对置的接合面以及所述基板接合部的与所述其他的布线图案的被接合面对置的接合面具备脱气排出机构,该脱气排出机构使在所述金属板连接器的焊接时熔融的焊锡中产生的脱气从介于所述接合面与所述被接合面之间的焊锡排出。
此外,本发明的其他的方式的半导体模块具备:金属制的基板;形成于所述基板上的绝缘层;形成于所述绝缘层上的多个布线图案;借助焊锡被安装在所述多个布线图案中的一个布线图案上的裸芯片晶体管;以及由金属板构成的金属板连接器,其将形成于所述裸芯片晶体管的上表面的电极与所述多个布线图案中的其他布线图案接合。
所述金属板连接器具备如下部分而呈桥形:平板部;电极接合部,其配置于所述平板部的一个方向的一端侧,借助焊锡与所述裸芯片晶体管的电极接合;基板接合部,其配置于所述平板部的所述一个方向的另一端侧,借助焊锡与所述其他布线图案接合;第一连结部,其从所述平板部的所述一个方向的一端向下延伸,并且将所述平板部的所述一个方向的一端与所述电极接合部的一端连结;以及第二连结部,其从所述平板部的所述一个方向的另一端向下延伸,并且将所述平板部的所述一个方向的另一端与所述基板接合部的一端连结。
此外,所述电极接合部形成为从所述第一连结部被弯折而向所述一个方向的外侧延伸,并且形成为,在与所述平板部垂直的方向上,所述电极接合部的一端与所述平板部的距离小于另一端与所述平板部的距离,所述电极接合部的接合面相对于所述裸芯片晶体管的电极的与该接合面对置的被接合面倾斜。
并且,所述基板接合部形成为从所述第二连结部被弯折而向所述一个方向的外侧延伸,并且形成为,在与所述平板部垂直的方向上,所述基板接合部的一端与所述平板部的距离小于另一端与所述平板部的距离,所述基板接合部的接合面相对于所述其他布线图案的与该接合面对置的被接合面倾斜。
在所述其他的方式的半导体模块中,也可以是,所述电极接合部的接合面与所述裸芯片晶体管的电极的被接合面所成的倾斜角度及所述基板接合部的接合面与所述其他布线图案的被接合面所成的倾斜角度为0.5°以上且7.5°以下。
此外,在所述一个方式的半导体模块及所述其他的方式的半导体模块中,也可以是,所述电极接合部的与所述一个方向垂直的方向上的宽度比所述基板接合部的与所述一个方向垂直的方向上的宽度窄。
并且,在所述一个方式的半导体模块及所述其他的方式的半导体模块中,也可以是,在所述平板部的与所述一个方向垂直的方向上的两端分别形成有从该两端向下弯折的平衡肋部。
并且,在所述一个方式的半导体模块及所述其他的方式的半导体模块中,也可以是,所述电极接合部及所述基板接合部的厚度比所述金属板连接器的其他部分的厚度大。
并且,在所述一个方式的半导体模块及所述其他的方式的半导体模块中,也可以是,所述平板部的厚度比所述金属板连接器的其他部分的厚度大。
发明效果
本发明的半导体模块提高基于焊锡的电连接的可靠性并且廉价。
附图说明
图1是示出使用了本发明的一个实施方式的半导体模块的电动助力转向装置的基本结构的图。
图2是示出图1所示的电动助力转向装置的控制器的控制系统的框图。
图3是图1所示的电动助力转向装置的包含半导体模块的控制器的分解立体图。
图4是图3所示的半导体模块的俯视图。
图5是构成裸芯片晶体管的裸芯片FET的示意的俯视图。
图6是用于说明在图3及图4所示的半导体模块中裸芯片FET的电极和基板上的布线图案之间的接合状态的示意图。
图7是说明金属板连接器的电极接合部及基板接合部的接合面与被接合面所成的倾斜角度的示意图。
图8是示出倾斜角度与空隙产生率之间的关系的图表。
图9是示出金属板连接器的形状的一例的立体图。
图10是图9的金属板连接器的图,(A)是俯视图,(B)是主视图,(C)是后视图。
图11是示出具有平衡肋部的金属板连接器的立体图。
图12是示出电极接合部及基板接合部的厚度较大的金属板连接器的立体图。
图13是说明图9、10的金属板连接器的形状的侧视图。
图14是示出平板部的厚度较大的金属板连接器的立体图。
图15是示出金属板连接器的形状的另外一个例子的立体图。
图16是用于说明半导体模块的制造工序的图。
图17是示出应力缓和部的例子的图。
图18是示出应力缓和部的另外一个例子的图。
图19是示出应力缓和部的另外一个例子的图。
图20是示出应力缓和部的另外一个例子的图。
具体实施方式
参照附图对本发明的实施方式进行详细的说明。图1是示出使用了本发明的一个实施方式的半导体模块的电动助力转向装置的基本结构的图。图2是示出图1所示的电动助力转向装置的控制器的控制系统的框图。图3是图1所示的电动助力转向装置的包含半导体模块的控制器的分解立体图。图4是图3所示的半导体模块的俯视图。
图5是构成裸芯片晶体管的裸芯片FET的示意的俯视图。图6是用于说明在图3及图4所示的半导体模块中裸芯片FET的电极和基板上的布线图案之间的接合状态的示意图。图7是说明栅电极用金属板连接器的电极接合部及基板接合部的接合面与被接合面所成的倾斜角度的示意图。
在图1的电动助力转向装置中,方向盘1的柱轴2经减速齿轮3、万向接头4A及4B、齿轮齿条机构5与转向车轮的拉杆6连结。在柱轴2上设置有对方向盘1的转向转矩进行检测的转矩传感器7,输出辅助转矩的电动马达8通过减速齿轮3与柱轴2连结,其中,该辅助转矩辅助方向盘1的转向转矩。
对控制电动助力转向装置的控制器10,在被电池(未图示)供给电力的同时,经由点火钥匙(未图示)被输入点火钥匙信号IGN(参照图2)。控制器10根据由转矩传感器7检测到的转向转矩TS和由车速传感器9检测到的车速V,进行作为助推(转向辅助)指令的转向辅助指令值的运算,根据运算出的转向辅助指令值确定向电动马达8供给的电流,控制电动马达所输出的辅助转矩。
控制器10主要由微型计算机构成,但是,若示出其控制装置的机构及构成,则如图2所示。
由转矩传感器7检测到的转向转矩TS及由车速传感器9检测到的车速V输入到作为控制运算部的控制运算装置11,将由控制运算装置11运算出的电流指令值输入到栅极驱动电路12。将在栅极驱动电路12中根据电流指令值等形成的栅极驱动信号输入到由FET的桥式结构所构成的马达驱动部13,马达驱动部13经由用于紧急停止的切断装置14驱动由三相无刷马达构成的电动马达8。
由电流检测电路15来检测三相无刷马达的各相电流,将检测出的三相的马达电流ia~ic作为反馈电流输入到控制运算装置11。此外,三相无刷马达中安装有霍尔传感器等旋转传感器16,将来自旋转传感器16的旋转信号RT输入到转子位置检测电路17,将检测到的旋转位置θ输入到控制运算装置11。
此外,将来自点火钥匙的点火钥匙信号IGN输入到点火电压监视部18及电源电路部19,从电源电路部19向控制运算装置11输入电源电压Vdd并且向控制运算装置11输入用于装置停止的复位信号Rs。而且,切断装置14由对2相进行切断的继电器触点141及142构成。
此外,对马达驱动部13的电路构成进行说明,串联连接的FETTr1及Tr2、FETTr3及Tr4、以及FETTr5及Tr6相对于电源线81串联连接。而且,相对于电源线81并联连接的FETTr1及Tr3、FETTr5及Tr2、以及FETTr4及Tr6与接地线82连接。由此,构成逆变器。
这里,FETTr1及Tr2中,FETTr1的源电极S和FETTr2的漏电极D串联连接而构成三相马达的c相臂,通过c相输出线91c输出电流。此外,FETTr3及Tr4中,FETTr3的源电极S和FETTr4的漏电极D串联连接而构成三相马达的a相臂,通过a相输出线91a输出电流。而且,FETTr5及Tr6中,FETTr5的源电极S和FETTr6的漏电极D串联连接而构成三相马达的b相臂,通过b相输出线91b输出电流。
接着,图3是图1所示的电动助力转向装置的包含半导体模块的控制器10的分解立体图,控制器10具有外壳20、作为包含马达驱动部13的功率模块的半导体模块30、散热用薄板39、包含控制运算装置11及栅极驱动电路12的控制电路基板40、电力及信号用连接器50、三相输出用连接器60、和盖70。
这里,外壳20形成为大致矩形状,并具有:用于载置半导体模块30的平板状的半导体模块载置部21;设置于半导体模块载置部21的长度方向端部并用于安装电力及信号用连接器50的电力及信号用连接器安装部22;以及设置于半导体模块载置部21的宽度方向端部并用于安装三相输出用连接器60的三相输出用连接器安装部23。
而且,在半导体模块载置部21形成有旋进用于安装半导体模块30的安装螺钉38的多个螺钉孔21a。此外,在半导体模块载置部21以及电力及信号用连接器安装部22上竖立设置有用于安装控制电路基板40的多个安装柱子24,在各安装柱子24中形成有旋进用于安装控制电路基板40的安装螺钉41的螺钉孔24a。而且,在三相输出用连接器安装部23中形成有旋进用于安装三相输出用连接器60的安装螺钉61的多个螺钉孔23a。
此外,半导体模块30具有上述马达驱动部13的电路结构,如图4所示,在基板31上安装有6个FETTr1~Tr6、与电源线81连接的正极端子81a、及与接地线82连接的负极端子82a。此外,在基板31上安装有三相输出部90,该三相输出部90具备与a相输出线91a连接的a相输出端子92a、与b相输出线91b连接的b相输出端子92b以及与c相输出线91c连接的c相输出端子92c。此外,在基板31上安装有具备电容器的其他基板安装部件37。并且,在半导体模块30的基板31设置有供用于安装半导体模块30的安装螺钉38贯插的多个通孔31a。
这里,对在该半导体模块30中向基板31上安装6个FETTr1~Tr6进行说明。各FETTr1~Tr6由裸芯片FET(裸芯片晶体管)35构成,如图5所示,在裸芯片FET35上具备源电极S和栅电极G,此外,在裸芯片FET35的下表面具有未图示的漏电极。
如图5所示,形成于该裸芯片FET35的上表面的栅电极G和源电极S沿图5中的上下方向被串联地直线配置。栅电极G形成为具有沿图5中的上下方向延伸的短边及与该短边垂直的长边的长方形。此外,源电极S形成为具有沿图5中的上下方向延伸的短边及与该短边垂直的长边的长方形。源电极S的短边及长边比栅电极G的短边及长边大,源电极S的面积比栅电极G的面积大。
如图6所示,半导体模块30具有金属制的基板31,在基板31之上形成有绝缘层32。基板31是由铝等金属制成。此外,在该绝缘层32上形成有多个布线图案33a~33d。各布线图案33a~33d由铜或铝等金属或包含该金属的合金构成。
而且,在多个布线图案33a~33d中的一个布线图案33a上,通过焊锡34a安装有构成各FETTr1~Tr6的裸芯片FET35。在裸芯片FET35的下表面所形成的漏电极,通过焊锡34a与布线图案33a接合。而且,利用源电极用金属板连接器36a分别通过焊锡34e、34b使裸芯片FET35的源电极S和多个布线图案33a~33d中的其他布线图案33b接合。此外,利用栅电极用金属板连接器36b分别通过焊锡34f、34c使裸芯片FET35的栅电极G和多个布线图案33a~33d中的此外其他布线图案33c接合。
并且,在绝缘层32上所形成的多个布线图案33a~33d中的其他布线图案33d上,通过焊锡34d安装有电容器等其他基板安装部件37。
如图3所示,这样构成的半导体模块30通过多个安装螺钉38安装于外壳20的半导体模块载置部21上。在半导体模块30的基板31形成有供安装螺钉38插入的多个通孔31a。
此外,在将半导体模块30安装于半导体模块载置部21上时,将散热用薄板39安装于半导体模块载置部21上,从该散热用薄板39之上安装半导体模块30。利用该散热用薄板39,将半导体模块30产生的热量通过散热用薄板39向外壳20散热。
此外,控制电路基板40用于将多个电子器件安装于基板上而构成包含控制运算装置11及栅极驱动电路12的控制电路。在将半导体模块30安装于半导体模块载置部21上后,利用多个安装螺钉41在从半导体模块30的上方竖立设置于半导体模块载置部21以及电力及信号用连接器安装部22的多个安装柱子24上安装控制电路基板40。在控制电路基板40上形成有供安装螺钉41插入的多个通孔40a。
此外,电力及信号用连接器50用于将来自电池(未图示)的直流电源输入到半导体模块30,将包含来自转矩传感器7和车速传感器9的信号的各种信号输入到控制电路基板40。利用多个安装螺钉51在设置于半导体模块载置部21的电力及信号用连接器安装部22上安装电力及信号用连接器50。
而且,三相输出用连接器60用于输出来自a相输出端子92a、b相输出端子92b及c相输出端子92c的电流。利用多个安装螺钉61在设置于半导体模块载置部21的宽度方向端部的三相输出用连接器安装部23安装三相输出用连接器60。在三相输出用连接器60形成有供安装螺钉61插入的多个通孔60a。
并且,相对于安装有半导体模块30、控制电路基板40、电力及信号用连接器50及三相输出用连接器60的外壳20,以从控制电路基板40的上方覆盖该控制电路基板40的方式安装盖70。
这里,栅电极用金属板连接器36b是通过对由铜(Cu)、银(Ag)、金(Au)、铜合金、铝合金导体等兼具刚性和高导电性的材料构成的金属板进行冲裁及弯曲加工、即冲压成型而形成的。
而且,如图6、7所示,栅电极用金属板连接器36b具有如下部分而呈桥形:平板部36ba;电极接合部36bb,其配置于平板部36ba的一个方向(图6、7中的左右方向)的一端侧,并且通过焊锡34f与裸芯片FET35的栅电极G接合;基板接合部36bc,其配置于平板部36ba的所述一个方向的另一端侧,并且通过焊锡34c与布线图案33c接合;第一连结部36bd,其从平板部36ba的所述一个方向的一端向下延伸并且连结平板部36ba的所述一个方向的一端与电极接合部36bb的一端;以及第二连结部36be,其从平板部36ba的所述一个方向的另一端向下延伸并且连结平板部36ba的所述一个方向的另一端与基板接合部36bc的一端。即,基板接合部36bc与电极接合部36bb被配置为在所述一个方向(图6、7中的左右方向)上对置。
并且,电极接合部36bb形成为从第一连结部36bd被弯折而朝向所述一个方向的外侧延伸。并且,电极接合部36bb形成为,在与平板部36ba垂直的方向(图6、7中的上下方向)上,电极接合部36bb的一端(基端)与平板部36ba的距离比另一端(前端)与平板部36ba的距离小。因此,如图7所示,电极接合部36bb的接合面(下表面)相对于裸芯片FET35的栅电极G的与该接合面对置的被接合面倾斜(朝向图6、7中的下方向倾斜)。
并且,基板接合部36bc形成为从第二连结部36be被弯折而朝向所述一个方向的外侧延伸。并且,基板接合部36bc形成为,在与平板部36ba垂直的方向(图6、7中的上下方向)上,基板接合部36bc的一端(基端)与平板部36ba的距离比另一端(前端)与平板部36ba的距离小。因此,如图7所示,基板接合部36bc的接合面(下表面)相对于布线图案33c的与该接合面对置的被接合面倾斜(朝向图6、7中的下方向倾斜)。
电极接合部36bb的接合面与裸芯片FET35的栅电极G的被接合面所成的倾斜角度α及基板接合部36bc的接合面与布线图案33c的被接合面所成的倾斜角度α没有特别限定,优选为0.5°以上且7.5°以下,更优选为2°以上且6°以下,进一步优选为4°。
另一方面,源电极用金属板连接器36a与栅电极用金属板连接器36b同样地是通过对由铜(Cu)、银(Ag)、金(Au)、铜合金、铝合金导体等兼具刚性和高导电性的材料构成的金属板进行冲裁及弯曲加工、即冲压成型而形成的。
而且如图6所示,源电极用金属板连接器36a具有如下部分而呈桥形:平板部36aa;电极接合部36ab,其配置于平板部36aa的一个方向(图6中的左右方向)的一端侧,并且通过焊锡34e与裸芯片FET35的源电极S接合;基板接合部36ac,其配置于平板部36aa的所述一个方向的另一端侧,并且通过焊锡34b与布线图案33b接合;第一连结部36ad,其从平板部36aa的所述一个方向的一端向下延伸并且连结平板部36aa的所述一个方向的一端与电极接合部36ab的一端;以及第二连结部36ae,其从平板部36aa的所述一个方向的另一端向下延伸并且连结平板部36aa的所述一个方向的另一端与基板接合部36ac的一端。即,基板接合部36ac与电极接合部36ab被配置为在所述一个方向(图6中的左右方向)上对置。
并且,并且,电极接合部36ab形成为从第一连结部36ad被弯折而朝向所述一个方向的外侧延伸。并且电极接合部36ab形成为,在与平板部36aa垂直的方向(图6中的上下方向)上,电极接合部36ab的一端(基端)与平板部36aa的距离比另一端(前端)与平板部36aa的距离小。因此,电极接合部36ab的接合面(下表面)相对于裸芯片FET35的源电极S的与该接合面对置的被接合面倾斜(朝向图6中的下方向倾斜)。
并且,基板接合部36ac形成为从第二连结部36ae被弯折而朝向所述一个方向的外侧延伸。并且基板接合部36ac形成为,在与平板部36aa垂直的方向(图6中的上下方向)上,基板接合部36ac的一端(基端)与平板部36aa的距离比另一端(前端)与平板部36aa的距离小。因此,基板接合部36ac的接合面(下表面)相对于布线图案33b的与该接合面对置的被接合面倾斜(朝向图6、中的下方向倾斜)。
电极接合部36ab的接合面与裸芯片FET35的源电极S的被接合面所成的倾斜角度α及基板接合部36ac的接合面与布线图案33b的被接合面所成的倾斜角度α没有特别限定,优选为0.5°以上且7.5°以下,更优选为2°以上且6°以下,进一步优选为4°。
这样,电极接合部36ab、36bb的接合面相对于裸芯片FET35的电极S、G的与该接合面对置的被接合面倾斜,此外,由于基板接合部36ac、36bc的接合面相对于布线图案33b、33c的与该接合面对置的被接合面倾斜,因此,从在两电极用金属板连接器36a、36b的焊接时熔融的焊锡中产生的脱气的气泡容易从介于所述接合面与所述被接合面之间的焊锡排出。
即,由于从熔融的焊锡中产生的脱气的气泡与相邻的气泡结合并且沿着倾斜的所述接合面朝向斜上方移动,因此,容易从焊锡排出。并且,在焊接时,由于熔融的焊锡借助浸透现象而沿着第一连结部36ad、36bd及第二连结部36ae、36be流动至平板部36aa、36ba的下表面(参照图7),因此,气泡伴随着该焊锡的流动而移动,气泡更容易从介于所述接合面与所述被接合面之间的焊锡排出。
特别地,当在回流炉中进行两电极用金属板连接器36a、36b的焊接的情况下,由于以下的理由,更容易产生焊锡向平板部36aa、36ba的流动。由于回流炉内的温度是在较高的位置为高温,因此,关于回流炉内的两电极用金属板连接器36a、36b,相比于位于下方的电极接合部36ab、36bb及基板接合部36ac、36bc,位于上方的平板部36aa、36ba是高温的。一般情况下,由于焊锡具有从温度低的部位朝向温度高的部位流动的倾向,因此,在回流炉内的两电极用金属板连接器36a、36b中,焊锡容易从低温的电极接合部36ab、36bb及基板接合部36ac、36bc朝向高温的平板部36aa、36ba流动。
这样,通过同时利用电极接合部36ab、36bb及基板接合部36ac、36bc的接合面的倾斜、焊锡的浸透现象及两电极用金属板连接器36a、36b的温度分布这3点,气泡变得极其容易地从焊锡排出。
其结果,由于介于所述接合面与所述被接合面之间的焊锡中的空隙产生率被抑制为较低,因此,基于焊锡的电连接的可靠性变高,焊接部分的电阻变低。因此,即使在例如100A的高电流流过焊接部分时,也不容易产生过热、着火等问题。
若与本实施方式相反,电极接合部36ab、36bb形成为,在与平板部33aa、36ba垂直的方向上,电极接合部36ab、36bb的一端与平板部33aa、36ba的距离比另一端与平板部33aa、36ba的距离大,并且基板接合部36ac、36bc形成为,在与平板部33aa、36ba垂直的方向上,基板接合部36ac、36bc的一端与平板部33aa、36ba的距离比另一端与平板部33aa、36ba的距离大(即,倾斜方向是与本实施方式相反的方向,接合面朝向图6、7的上方向倾斜),则基本不会得到上述那样的通过焊锡的流动而使气泡变得更容易排出的效果。即,由于熔融的焊锡基本不会流动至平板部36aa、36ba的下表面,因此,基本不会得到上述那样的通过焊锡的流动而使气泡变得更容易排出的效果。
并且,由于这样的源电极用金属板连接器36a及栅电极用金属板连接器36b能够通过对金属板进行冲压成型而容易地形成,因此,能够廉价地制造本实施方式的半导体模块30。
如上述那样,所述倾斜角度α优选为0.5°以上且7.5°以下,但是,若倾斜角度α小于0.5°,则气泡变得不容易从介于所述接合面与所述被接合面之间的焊锡排出。其结果,空隙产生率变高,基于焊锡的电连接的可靠性不充分,在例如100A的高电流流过焊接部分时可能产生过热、着火等问题。
另一方面,若倾斜角度α超过7.5°,则所述接合面与所述被接合面借助焊锡的接合面积变小,因此,在例如100A的高电流流过焊接部分时可能产生过热、着火等问题。此外,焊接部分的强度可能不够。若进行详细叙述,则在倾斜角度α较大的情况下,由于所述接合面与所述被接合面之间的距离(间隙)变大,因此,应该借助焊锡进行接合的间隙的空间体积变大,但是,例如在通过回流进行焊接的情况下,由于涂布于接合部分的焊锡的涂布量(供给量)是确定的,因此,所述接合面与所述被接合面借助焊锡的接合面积变小。因而,焊接部分的强度可能不够。
此外,同样地,在倾斜角度α较大的情况下,焊锡的最小接合长度D(所述一个方向的长度,参照图7)变小。因此,若倾斜角度α超过7.5°,则焊锡的最终状态可能不满足规定了电子组装品的品质容许条件的IPC-A-610的容许基准。
IPC-A-610的规定在下面示出。若设电极接合部36ab、36bb及基板接合部36ac、36bc的所述一个方向(图7中的左右方向)的长度为L、设焊锡的最小接合长度(所述一个方向的长度)为D、设电极接合部36ab、36bb及基板接合部36ac、36bc的最小宽度(与所述一个方向垂直的方向的长度)为W,则在L>3W的情况下,D>0.75L,在L<3W的情况下,D≥L。
这里,对所述倾斜角度α进行各种变更来制造半导体模块,对调查了是否满足IPC-A-610的容许基准的结果进行说明。例如,在W=1.2mm、L=1.7mm的情况下(即L<3W的情况下),若设倾斜角度α为5°,则D=1.88mm,若设倾斜角度α为7.5°,则D=1.70mm,它们都满足IPC-A-610的容许基准。与此相对,由于若设倾斜角度α为8.5°,则D=1.68mm,因此,不满足IPC-A-610的容许基准。
接下来,对所述倾斜角度α进行各种变更来制造半导体模块,在图8的图表中示出调查了介于所述接合面与所述被接合面之间的焊锡中的空隙产生率的结果。若详述,则在各角度下,制造100个半导体模块,设它们为1批量,对在任何角度下都是3批量以上的半导体模块调查空隙产生率。而且,在各角度下,绘制整个半导体模块的空隙产生率中的最大值、最小值,并且,绘制所有的空隙产生率的平均值。
根据图8的图表,可知:若倾斜角度α为0.5°以上,则空隙产生率被抑制为5%以下。若倾斜角度α为0.5°以上,则除了空隙产生率较低之外,空隙产生率的不均匀也较小。若倾斜角度α小于0.5°,则除了空隙产生率急剧变高之外,空隙产生率的不均匀也急剧变大。
但是,若倾斜角度α较大,则所述接合面与所述被接合面之间的距离变大,夹着的焊锡的厚度变大。因而,优选倾斜角度α为7.5°以下,更优选为6.0°以下,进一步优选为5.0°以下。
此外,若考虑金属板连接器的形状的制造上的误差和不均匀,则优选倾斜角度α为2.5°以上,更优选为3.0°以上。
并且,作为在制造金属板连接器时(金属板的加工时)目标的倾斜角度α,作为所述优选的范围的下限值0.5°和上限值7.5°的中央值的4°是最优选的,但是,从设公差的量为正负2°这一点考虑,更优选倾斜角度α为2°以上且6°以下。
因而,若综合考虑这些点,则优选倾斜角度α为0.5°以上且7.5°以下,更优选为2°以上且6°以下,进一步优选为3.0°以上且5.0°以下。
另一方面,在倾斜角度α为0°的情况下(即,所述接合面与所述被接合面平行的情况下),当然,即使在倾斜角度α小于0°的情况下(即,在所述的倾斜方向为本实施方式的相反方向的情况下),由于气泡不容易从介于所述接合面与所述被接合面之间的焊锡排出,因此,存在空隙产生率的不均匀较大并且空隙产生率超过5%的情况。
这样,金属板连接器36a、36b具有使从金属板连接器36a、36b的焊接时熔融的焊锡中产生的脱气从介于接合面与被接合面之间的焊锡34b、34c、34e、34f中排出的脱气排出机构。即,电极接合部36ab、36bb的与裸芯片FET35的电极S、G的被接合面对置的接合面以及基板接合部36ac、36bc的与其他的布线图案33b、33c的被接合面对置的接合面分别相对于各被接合面倾斜,由此,分别构成脱气排出机构。其结果,由于介于接合面与被接合面之间的焊锡34b、34c、34e、34f中的空隙产生率被抑制为较低,因此,基于焊锡的电连接的可靠性较高。
此外,电极接合部36ab、36bb的接合面与裸芯片FET35的电极S、G的被接合面所成的倾斜角度α、和基板接合部36ac、36bc的接合面与布线图案33b、33c的被接合面所成的倾斜角度α可以相同,也可以不同。
此外,由于电极接合部36ab、36bb及基板接合部36ac、36bc的接合面分别相对于被接合面倾斜,因此,接合面与被接合面的接触形态不是面接触而是线接触。因而,对于金属板连接器36a、36b,与接合面与被接合面的接触形态是面接触的情况相比,相对来说,不容易站立。
但是,由于若接合面相对于被接合面倾斜,则在第一连结部36ad、36bd及第二连结部36ae、36be中产生朝向所述一个方向的内侧的力,因此,金属板连接器36a、36b能够稳定地站立。因而,金属板连接器36a、36b不容易由于振动等而倾倒。此外,为了提高金属板连接器36a、36b的站立性,可以通过后述的手段(设置平衡肋部的手段、使电极接合部及基板接合部的厚度比金属板连接器的其他部分的厚度大的手段)而使金属板连接器36a、36b的重心变得更低。
并且,可以对电极接合部36ab、36bb的接合面或基板接合部36ac、36bc的接合面实施憎水性的表面处理。这样,由于通过表面处理而提高了浸润性,因此,气泡沿着所述接合面朝向斜上方移动时的电阻变小,气泡更容易从介于所述接合面与所述被接合面之间的焊锡排出。憎水性的表面处理的种类没有特别限定,能够列举例如锡铜合金镀层。
并且,可以对电极接合部36ab、36bb的接合面或基板接合部36ac、36bc的接合面实施防氧化处理。若在接合面上形成氧化膜,则焊锡的浸润性下降,但是由于若实施防氧化处理,则不形成氧化膜,焊锡的浸润性较高,因此,焊锡容易从电极接合部36ab、36bb及基板接合部36ac、36bc朝向平板部36aa、36ba流动。其结果,能够更稳定地形成焊锡的焊脚。防氧化处理的种类没有特别限定,能够列举例如锡镀层。
防氧化处理既可以对金属板连接器36a、36b的表面的整个面实施,也可以仅对与形成的焊锡的焊脚接触的部分实施。例如,也可以对电极接合部36ab、36bb的接合面及基板接合部36ac、36bc的接合面的整个面、第一连结部36ad、36bd及第二连结部36ae、36be的内侧面的整个面以及平板部36aa、36ba的下表面的整个面实施防氧化处理。
或者,也可以对电极接合部36ab、36bb的接合面及基板接合部36ac、36bc的接合面的整个面以及第一连结部36ad、36bd及第二连结部36ae、36be的内侧面中的下方部分(例如,至金属板连接器36a、36b的上下方向的一半的高度位置)实施防氧化处理。这样,由于若只对第一连结部36ad、36bd及第二连结部36ae、36be的内侧面中的下方部分实施防氧化处理,则焊锡的焊脚不容易形成于平板部36aa、36ba的下表面,因此,能够控制焊锡的焊脚的形成部位。若在对金属板连接器36a、36b的表面的一部分进行了遮蔽处理的基础上实施防氧化处理,则能够对期望的部位实施防氧化处理。
并且,源电极用金属板连接器36a及栅电极用金属板连接器36b的形状也可以例如图9,10所示。由于源电极用金属板连接器36a及栅电极用金属板连接器36b的形状大致相同,因此,以后,只对栅电极用金属板连接器36b的形状在下文进行说明,省略源电极用金属板连接器36a的形状的说明。
栅电极用金属板连接器36b的形状是所述那样的桥形,但是若更详细地进行说明,栅电极用金属板连接器36b具备平板部36ba、从平板部36ba的所述一个方向(图9的X轴方向)的一端借助第一弯曲部36bf向下延伸的第一连结部36bd以及从平板部36ba的所述一个方向的另一端借助第3弯曲部36bh向下延伸的第二连结部36be而形成为桥形(构成帽子形状的桥)。而且,电极接合部36bb形成为从第一连结部36bd借助第二弯曲部36bg弯折并向所述一个方向的外侧延伸,基板接合部36bc形成为从第二连结部36be借助第4弯曲部36bi弯折并向所述一个方向的外侧延伸。
此外,第一连结部36bd在电极接合部36bb的附近具有窄幅部36bj。该窄幅部36bj是宽度(图9的Y轴方向的长度)从第一弯曲部36bf朝向第二弯曲部36bg变窄的锥形。另一方面,第二连结部36be不具有窄幅部,与平板部36ba大致相同宽度。因而,如图10所示,电极接合部36bb在与所述一个方向垂直的方向上(图9的Y轴方向,图10中的上下方向)的宽度W1比基板接合部36bc在与所述一个方向垂直的方向上的宽度W2窄。
这样,通过使栅电极用金属板连接器36b的电极接合部36bb在与所述一个方向垂直的方向上的宽度W1比基板接合部36bc在与所述一个方向垂直的方向上的宽度W2窄,能够利用宽度窄的电极接合部36bb侧的1点、和宽度宽的基板接合部36bc侧的2点(基板接合部36bc的宽度方向两端附近的2点)共计3点,使栅电极用金属板连接器36b在裸芯片FET35及基板31的上表面站立。因此,如后述那样,在利用回流将栅电极用金属板连接器36b焊接在裸芯片FET35及基板31上时,能够减少栅电极用金属板连接器36b发生倾倒的可能性。由此,即使使裸芯片FET35及栅电极用金属板连接器36b小型化,也能够使其组装性良好。
此外,栅电极用金属板连接器36b能够借助宽度窄的电极接合部36bb侧的1点、和宽度宽的基板接合部36bc侧的2点共计3点而在裸芯片FET35及基板31上站立。因此,即使由于冲压成型而扭曲,电极接合部36bb也在适当的位置与FET35裸芯片的栅电极G接触,焊接中的配置位置精度良好。因此,能够较高地维持被焊接的电极接合部36bb与裸芯片FET35的栅电极G的接合可靠性。此外,为了裸芯片FET35的小型化,优选使在其上表面形成的栅电极G小。即使使电极接合部36bb的宽度W1比基板接合部36bc的宽度W2窄,在裸芯片FET35所形成的栅电极G小的情况下,接合的可靠性也没有问题。
此外,在栅电极用金属板连接器36b中,在使电极接合部36bb及基板接合部36bc的两者为窄幅,并利用宽度窄的电极接合部36bb侧的1点、和宽度窄的基板接合部36bc侧的1点共计2点使其在裸芯片FET35及基板31上站立的情况下,栅电极用金属板连接器36b非常容易倾倒。
此外,栅电极用金属板连接器36b的电极接合部36bb位于基板接合部36bc的与所述一个方向垂直的宽度方向的大致中央部。由此,宽度窄的电极接合部36bb相对于基板接合部36bc的宽度方向位于平衡好的位置。因此,在栅电极用金属板连接器36b利用宽度窄的电极接合部36bb侧的1点、和宽度宽的基板接合部36bc侧的2点共计3点,在裸芯片FET35和基板31上站立时,由于电极接合部36bb的位置的平衡良好,因此,能够提高栅电极用金属板连接器36b的站立性。
并且,为了进一步提高栅电极用金属板连接器36b的站立性,可以在栅电极用金属板连接器36b上设置平衡肋部36bl,或者使电极接合部36bb及基板接合部36bc的厚度比金属板连接器的其他部分的厚度大,来使栅电极用金属板连接器36b的重心更低。
首先,对平衡肋部36bl进行说明。在栅电极用金属板连接器36b中,如图11(A)所示,可以在设于电极接合部36bb与基板接合部36bc之间的平板部36ba的与所述一个方向垂直的方向的两端分别形成从该两端向下弯折的平衡肋部36bl、36bl。
借助该平衡肋部36bl,栅电极用金属板连接器36b的重心位置下降,栅电极用金属板连接器36b的站立性得以改善。因此,在栅电极用金属板连接器36b利用宽度窄的电极接合部36bb侧的1点、和宽度宽的基板接合部36bc侧的2点共计3点,在裸芯片晶体管及基板的上表面站立时,其站立性向稳定的方向改善。因此,在利用回流将栅电极用金属板连接器36b焊接在裸芯片晶体管及基板上时,能够可靠地避免栅电极用金属板连接器36b的倾倒,能够提高焊接的可靠性。
接下来,对电极接合部36bb及基板接合部36bc的厚度进行说明。在栅电极用金属板连接器36b中,如图12(A)所示,栅电极用金属板连接器36b的电极接合部36bb及基板接合部36bc的板厚也可以比栅电极用金属板连接器36b的其他部分(即,平板部36ba、第一连结部36bd、第二连结部36be)的板厚大。电极接合部36bb及基板接合部36bc的板厚的大小不被特别限定,但是,例如,也可以是栅电极用金属板连接器36b的其他部分(即,平板部36ba、第一连结部36bd、第二连结部36be)的板厚L的大约3倍(3L)。
通过使电极接合部36bb及基板接合部36bc的板厚变大,从而栅电极用金属板连接器36b的重心位置变低,站立性得到改善。因此,在栅电极用金属板连接器36b利用宽度窄的电极接合部36bb侧的1点、和宽度宽的基板接合部36bc侧的2点共计3点,在裸芯片晶体管及基板的上表面站立时,其站立性向稳定的方向改善。因此,在利用金属回流将栅电极用金属板连接器36b焊接在裸芯片晶体管及基板上时,能够可靠地避免栅电极用金属板连接器36b的倾倒,能够提高焊接的可靠性。
此外,在栅电极用金属板连接器36b中,在电极接合部36bb与基板接合部36bc之间设有应力缓和部。该应力缓和部以桥形构成,具备平板部36ba、从平板部36ba的一端借助第一弯曲部36bf向下弯折的第一连结部36bd以及从平板部36ba的另一端借助第三弯曲部36bh向下弯折的第二连结部36be。
通过使栅电极用金属板连接器36b为桥形,则桥形的各边(平板部36ba、第一连结部36bd、第二连结部36be)不仅能够伸缩还在各弯曲部36bf、36bg、36bh、36bi弯折的方向上变形,因此,得到板簧的效果,并且利用桥形骨架能够吸收上下左右方向(图9的Z轴方向、X轴方向)的位移。即,即使在由于热膨胀、热收缩而产生了基板31或金属板连接器36a、36b的变形的情况下,也可以容易地弯曲金属板连接器36a、36b。
这样,通过在电极接合部36bb与基板接合部36bc之间设置应力缓和部,从而能够吸收裸芯片FET35和栅电极用金属板连接器36b之间的线膨胀系数之差、基板31和栅电极用金属板连接器36b之间的线膨胀系数之差、裸芯片FET35和基板31之间的线膨胀系数之差。因此,能够缓和针对裸芯片FET35与栅电极用金属板连接器36b的焊接部分及栅电极用金属板连接器36b与基板31(即布线图案33c)的焊接部分的热应力,能够确保栅电极用金属板连接器36b相对于裸芯片FET35及基板31的接合可靠性。顺便说明一下,基板31是铝材,其线膨胀系数为23.6×10-6/℃左右、由铜板构成的栅电极用金属板连接器36b的线膨胀系数为16.8×10-6/℃左右、裸芯片FET是硅,其线膨胀系数为2.5×10-6/℃左右。
另一方面,若在电极接合部36bb和基板接合部36bc之间设置应力缓和部,则由于一般情况下应力缓和部由波形等构成(本实施方式中为桥形),因此,栅电极用金属板连接器36b为难以站立的形状。但是,通过使栅电极金属板连接器36b的电极接合部36bb在与所述一个方向垂直的方向上的宽度W1比基板接合部36bc在与所述一个方向垂直的方向上的宽度W2窄,能够使栅电极用金属板连接器36b利用宽度窄的电极接合部36bb侧的1点、和宽度宽的基板接合部36bc侧的2点共计3点在裸芯片FET35及基板31上站立,因此,保证了栅电极用金属板连接器36b的站立性。
此外,如图10所示的那样,栅电极用金属板连接器36b的第一连结部36bd形成为从平板部36ba到电极接合部36bb为止宽度逐渐变细的锥状,将电极接合部36bb的弯曲基点、即第二弯曲部36bg的基点设为第一连结部36bd的最细部位。
这样,由于电极接合部36bb的弯曲基点是锥状的第一连结部36bd的最细部位,因此容易变形。因此,在焊接等中,由于裸芯片FET35和栅电极用金属板连接器36b之间的线膨胀系数之差、基板31和栅电极用金属板连接器36b之间的线膨胀系数之差、裸芯片FET35和基板31之间的线膨胀系数之差而使栅电极用金属板连接器36b发生变形时,电极接合部36bb的弯曲基点能够容易地变形。由此,能够确保电极接合部36bb相对于栅电极G的接合可靠性。
并且,如图9、10所示,栅电极用金属板连接器36b在平板部36ba的宽度方向(图9的Y轴方向,图10中的上下方向)的两端部设置有冲压成型时的跳步切割部36bk。该跳步切割部36bk形成为向平板部36ba的幅方向外侧突出。
由于在栅电极用金属板连接器36b的平坦面(平板部36ba)上设置有跳步切割部36bk,因此容易进行切割,可以抑制切割工序中的部件变形。进而,由于使该跳步切割部36bk形成为从平板部36ba向外侧突出,因此可以不使平板部36ba的平坦面变形而进行切割。
并且,栅电极用金属板连接器36b具备4个弯曲部(36bf、36bg、36bh、36bi),呈桥形。这里,各弯曲部(36bf、36bg、36bh、36bi)的角度能够如图13所示的例子那样为钝角(例如95°、99°)。由此,能够更适合于基于冲压成型的制造。
即,能够防止基于冲压加工的回弹,提高部件精度。并且,由于设4个弯曲部的角度为钝角,因此,能够改善冲压成型时的脱模性,有助于降低制造成本。此外,若4个弯曲部的角度为钝角,则对于栅电极用金属板连接器36b,应力朝向平板部36ba的所述一个方向内向作用,因此,能够以稳定的状态设置栅电极用金属板连接器36b。
并且,通过使栅电极用金属板连接器36b为桥形,能够在栅电极用金属板连接器36b的大致中央部的平坦面(平板部36ba)上设置重心C(参照图9)。因此,在向基板31搭载时,在将栅电极用金属板连接器36b吸附保持于搬送工具时,能够吸附位于该平坦面的重心C。
因此,能够均衡地对栅电极用金属板连接器36b进行吸附保持,能够确保栅电极用金属板连接器36b的转移时的稳定性,使部件配置位置精度提高。其结果,能够确保栅电极用金属板连接器36b的电连接的可靠性。栅电极用金属板连接器36b的位于平板部ba的重心位置的吸附范围优选为2mm2左右的面积,更优选为2mm2~5mm2左右的面积。
为了使重心(C)位于栅电极用金属板连接器36b的平板部36ba的平面(平坦面)上,例如如图14(A)所示,优选使平板部36ba的厚度比栅电极用金属板连接器36b的其他部分,即,电极接合部36bb、基板接合部36bc、第一连结部36bd、第二连结部36be的厚度大。平板部36ba的板厚的大小没有特别限定,例如可以是栅电极用金属板连接器36b的其他部分,即,电极接合部36bb、基板接合部36bc、第一连结部36bd、第二连结部36be的板厚L的大约3倍(3L)。
此外,栅电极用金属板连接器36b的形状只要是能够将栅电极G与布线图案33c接合的桥形即可,能够是任意的形状。例如,如图15所示,也可以是不设窄幅部36bj的形状。即,也可以是第一连结部36bd、电极接合部36bb、第二连结部36be及基板接合部36bc的宽度与平板部36ba的宽度大致相同的形状。
在图15所示的形状的栅电极用金属板连接器36b中,也可以与前述的图9所示的形状的栅电极用金属板连接器36b的情况同样地,为了进一步提高栅电极用金属板连接器36b的站立性而设置平衡肋部36bl(参照图11(B))。此外,同样地,也可以使电极接合部36bb及基板接合部36bc的厚度比金属板连接器的其他部分的厚度大(参照图12(B))。并且,为了使重心(C)位于栅电极用金属板连接器36b的平板部36ba的平面(平坦面)上,也可以使平板部36ba的厚度比栅电极用金属板连接器36b的其他部分的厚度大(参照图14(B))。
接下来,参照图16对半导体模块30的制造工序进行说明。
在制造半导体模块30时,如图16(A)所示,首先,在金属制的基板31的一方的主面上形成绝缘层32(绝缘层形成工序)。
接着,如图16(A)所示,在绝缘层32上形成多个布线图案33a~33d(布线图案形成工序)。
之后,如图16(B)所示,在多个布线图案33a~33d上分别涂布焊膏(焊锡34a~34d)(焊膏涂布工序)。
然后,如图16(C)所示那样,在多个布线图案33a~33d中的一个布线图案33a上所涂布的焊膏(焊锡34a)上搭载一个裸芯片FET35(裸芯片FET搭载工序),并且在其他布线图案33d上所涂布的焊膏(焊锡34d)上搭载其他基板安装部件37。对于其他裸芯片FET35,也将其搭载于与布线图案33a相同的或者另一个布线图案。
接着,如图16(D)所示,在形成于裸芯片FET35的上表面的源电极S及栅电极G上涂布焊膏(焊锡34e,34f)(焊膏涂布工序)。
之后,如图16(E)所示那样,在裸芯片FET35的源电极S上所涂布的焊膏(焊锡34e)上、以及、多个布线图案33a~33d中的除了搭载了裸芯片FET35的布线图案33a以外的其他布线图案33b上所涂布的焊膏(焊锡34b)上,搭载源电极用金属板连接器36a(源电极用金属板连接器搭载工序)。
此外,如图16(E)所示,在涂布于裸芯片FET35的栅电极G上的焊膏(焊锡34f)上、以及涂布于多个布线图案33a~33d中的除了搭载了裸芯片FET35的布线图案33a及搭载了源电极用金属板连接器36a的布线图案33b以外的另外其他布线图案33c上的焊膏(焊锡34c)上,搭载栅电极用金属板连接器36b(栅电极用金属板连接器搭载工序)。由此,构成半导体模块中间组装体。
而且,将通过以上的工序构成的半导体模块中间组装体放入到回流炉(未图示),并集中进行如下的接合:通过焊锡34a将多个布线图案33a~33d中的一个布线图案33a和裸芯片FET35接合、通过焊锡34d将布线图案33d和其他基板安装部件37接合、通过焊锡34e将在裸芯片FET35的上表面所形成的源电极S和源电极用金属板连接器36a接合、将多个布线图案33a~33d中的其他布线图案33b和源电极用金属板连接器36a接合、通过焊锡34f将在裸芯片FET35的上表面所形成的栅电极G和栅电极用金属板连接器36b接合、以及通过焊锡34c将多个布线图案33a~33d中的另外其他布线图案33c和栅电极用金属板连接器36b接合(接合工序)。由此,制成半导体模块30。
这里,通过使用源电极用金属板连接器36a及栅电极用金属板连接器36b,通过焊锡安装作业进行裸芯片FET35的源电极S与基板31上的布线图案33b的接合、以及裸芯片FET35的栅电极G与基板31上的其他布线图案33c的接合,因此,可以通过与将裸芯片FET35或其他基板安装部件37安装于基板31上的布线图案33a、33d上时进行的焊锡安装作业相同的设备、相同的工序同时进行裸芯片FET35的源电极S和基板31上的布线图案33b之间的接合以及裸芯片FET35的栅电极G和基板31上的其他布线图案33c之间的接合。因此,可以缩短半导体模块30的制造节拍,并且不再需要线接合的专用设备,可以降低半导体模块30的制造成本。
此外,在回流炉中的接合工序中,栅电极用金属板连接器36b的电极接合部36bb的与所述一个方向垂直的方向上的宽度W1比基板接合部36bc的与所述一个方向垂直的方向上的宽度W2窄,栅电极用金属板连接器36b能够利用宽度窄的电极接合部36bb侧的1点、和宽度宽的基板接合部36bc侧的2点(基板接合部36bc的宽度方向两端附近的2点)共计3点,在裸芯片FET35及基板31的上表面站立。因此,在利用回流将栅电极用金属板连接器36b焊接在裸芯片FET35及基板31上时,能够减少栅电极用金属板连接器36b倾倒的可能性。由此,即使使裸芯片FET35及栅电极用金属板连接器36b小型化,也能够使其组装性良好。
并且,对于半导体模块30的基板31,使用了铝,对于源电极用金属板连接器36a及栅电极用金属板连接器36b使用了兼具刚性和高导电性的金属材料。铝的线膨胀系数是23.6×10-6/℃,作为一例,铜材的线膨胀系数是16.8×10-6/℃。即,与源电极用金属板连接器36a及栅电极用金属板连接器36b相比,针对温度变化,基板31更容易变形。
因此,若由于回流工序或电动助力转向(EPS)工作过程中的发热而形成高温,则由于基板31和金属板连接器36a、36b之间的膨胀率不同,使得在金属板连接器36a、36b产生应力。这时,若金属板连接器36a、36b为不能缓和该应力的结构,则有可能使与裸芯片FET35之间的焊接剥落。
与此相对,在本实施方式中,通过将金属板连接器36a、36b设为桥形,从而不仅桥形的各边(平板部36aa、36ba、第一连结部36ad、36bd、第二连结部36ae、36be)进行伸缩,而且各弯曲部也可以在弯折的方向变形,因此得到板簧的效果,并且利用桥形骨架能够吸收上下左右方向(图9的Z轴方向、X轴方向)的位移。即,即使在由于热膨胀、热收缩而产生了基板31或金属板连接器36a、36b的变形的情况下,也可以容易地弯曲金属板连接器36a、36b。
这样,金属板连接器36a及36b在因回流工序而变形的情况或因EPS工作过程中的发热而变形的情况下,可以适当地吸收位移,因此可以防止金属板连接器36a及36b与裸芯片FET35之间的焊接的剥落,可以确保电连接的可靠性。
以上,对本发明的实施方式进行了说明,但是,本发明不限定于此,可以进行各种变更、改进。
例如,在半导体模块30中使用了裸芯片FET35,但不限于裸芯片FET35,也可以使用裸芯片IGBT等其他裸芯片晶体管。
而且,在使用其他裸芯片晶体管的情况下,只要利用金属板连接器通过焊锡使形成于裸芯片晶体管的上表面的电极和多个布线图案中的接合了裸芯片晶体管的布线图案以外的其他布线图案接合即可。由此,可以通过与在将裸芯片晶体管或其他基板安装部件安装于基板上的布线图案上时进行的焊接作业相同的设备、相同的工序同时进行裸芯片晶体管的电极和基板上的布线图案之间的接合。
而且,在使用裸芯片IGBT作为裸芯片晶体管的情况下,优选,使用金属板连接器通过焊锡分别将形成于裸芯片IGBT上的发射极电极及栅电极接合于基板上的布线图案。
这样,当使用裸芯片IGBT并分别使用金属板连接器将在裸芯片IGBT上形成的发射极电极及栅电极通过焊锡与基板上的布线图案接合的情况下,可以通过与在将裸芯片IGBT或其他基板安装部件安装于基板上的布线图案上时进行的焊接作业相同的设备、相同的工序同时进行裸芯片IGBT的发射极电极和基板上的布线图案之间的接合、以及裸芯片IGBT的栅电极和基板上的其他的布线图案之间的接合。
此外,在金属板连接器36a、36b上可以进一步设置以桥形构成的应力缓和部以及由其他结构构成的应力缓和部。即,可以进一步设置通过在电极接合部36ab、36bb或基板接合部36ac、36bc上形成缺口部36bm而构成的应力缓和部(参照图17)、通过在电极接合部36ab、36bb或基板接合部36ac、36bc的前端的角部上形成倒角部36bn(对于倒角部,也可以是C倒角来替代图示的R倒角)而构成的应力缓和部(参照图18),通过在电极接合部36ab、36bb或基板接合部36ac、36bc的中央形成孔36bp而构成的应力缓和部(参照图19),通过使电极接合部36ab、36bb或基板接合部36ac、36bc的厚度比金属板连接器36a、36b的其他部分的厚度小而构成的应力缓和部(参照图20)。此外,图17~20中的标号P表示源PAD。
在电极接合部36ab、36bb或基板接合部36ac、36bc伴随着通电时等产生的温度变化而发生热变形时,对于电极接合部36ab、36bb或基板接合部36ac、36bc,在膨胀时产生压缩应力,在收缩时产生拉伸应力。通过设置上述那样的应力缓和部,能够使基于该热量的压缩应力或拉伸应力分散而缓和,减少了基于热量的形变。其结果,通过与由桥形构成的应力缓和部的协同效果,能够提高电连接的可靠性。
并且,通过在电极接合部36ab、36bb或基板接合部36ac、36bc上设置上述那样的应力缓和部,能够缓和扭转方向的应力。特别地,在设置有通过形成缺口部36bm而构成的应力缓和部的情况下,由于电极接合部36ab、36bb与裸芯片FET35的触点和基板接合部36ac、36bc与布线图案33b、33c的触点成为2个,并且各自的接触部分的宽度变窄,因此,即使电极接合部36ab、36bb或基板接合部36ac、36bc受到基于热变形的扭转,也容易随动。此外,通过触点成为2个而能够构成所谓的双重系统,因此,提高了电连接的可靠性。
此外,在设置通过使电极接合部36ab、36bb或基板接合部36ac、36bc的厚度比金属板连接器36a、36b的其他部分的厚度小而构成的应力缓和部的情况下,由于电极接合部36ab、36bb或基板接合部36ac、36bc的板厚较薄,因此,在热变形时,容易扭转,容易进行位移吸收。
并且,在设置通过在电极接合部36ab、36bb或基板接合部36ac、36bc的前端的角部形成倒角部36bn而构成的应力缓和部的情况下,起到了如下效果:避免在受到基于热变形的扭转时应力向角部集中。
并且,在设置通过在电极接合部36ab、36bb或基板接合部36ac、36bc的中央形成孔36bp而构成的应力缓和部的情况下,即使受到基于热变形的扭转,也容易随动。此外,由于焊锡因浸透浸润现象而流过电极接合部36ab、36bb或基板接合部36ac、36bc的上表面而放射状地扩散,因此,即使受到扭转,焊锡也不容易剥离。
并且,在半导体模块30中,能够设栅电极用金属板连接器为1个种类,设源电极用金属板连接器为2个种类。即,能够设源电极用金属板连接器为第一源电极用金属板连接器(参照图4的Tr2及Tr4)以及第二源电极用金属板连接器(参照图4的Tr1、Tr3及Tr5)这2个种类,其中,该第一源电极用金属板连接器相对于栅电极用金属板连接器呈180°直线配置,该第二源电极用金属板连接器相对于栅电极用金属板连接器呈90°直角配置。而且,在1个裸芯片FET中,只要将1个种类的栅电极用金属板连接器和从2个种类的第一源电极用金属板连接器及第二源电极用金属板连接器中选择的任一方的源电极用金属板连接器组合来使用即可。
此外,对于第一源电极用金属板连接器相对于栅电极用金属板连接器的配置(栅电极用金属板连接器和第一源电极用金属板连接器所成的角度,即各个连接器的所述一个方向所成的角度),优选为95°~265°,更优选为160°~200°,更进一步优选为175°~185°,最优选为180°。
此外,对于第二源电极用金属板连接器相对于栅电极用金属板连接器的配置(栅电极用金属板连接器和第二源电极用金属板连接器所成的角度,即各个连接器的所述一个方向所成的角度),优选为5°~175°,更优选为70°~120°,更进一步优选为85°~95°,最优选为90°。
根据该半导体模块,与所述的半导体模块30同样,安装于基板上的裸芯片晶体管的配置上产生自由度,基板上的布线的设计自由度增大,可以使半导体模块在基板上的布局紧凑。并且,可以容易地使基板上的三相马达的各相路径的长度相同。由此,可以容易地使三相马达的各相特性、特别是各相的阻抗特性一致,能够提高转矩和速度等的脉动精度。
标号说明
30:半导体模块;31:基板;32:绝缘层;33a~33d:布线图案;34a~34d:焊锡;35:裸芯片FET(裸芯片晶体管);36a:源电极用金属板连接器;36aa:平板部;36ab:电极接合部;36ac:基板接合部;36b:栅电极用金属板连接器;36ba:平板部;36bb:电极接合部;36bc:基板接合部;36bd:第一连结部;36be:第二连结部;36bf:第一弯曲点;36bg:第二弯曲点;36bh:第3弯曲点;36bi:第4弯曲点;36bl:平衡肋部;G:栅电极(电极);S:源电极(电极)。

Claims (7)

1.一种半导体模块,其特征在于,
该半导体模块具备:
金属制的基板;
形成于所述基板上的绝缘层;
形成于所述绝缘层上的多个布线图案;
借助焊锡被安装在所述多个布线图案中的一个布线图案上的裸芯片晶体管;以及
由金属板构成的金属板连接器,其将形成于所述裸芯片晶体管的上表面的电极与所述多个布线图案中的其他布线图案接合,
所述金属板连接器具备如下部分而呈桥形:
平板部;
电极接合部,其配置于所述平板部的一个方向的一端侧,借助焊锡与所述裸芯片晶体管的电极接合;
基板接合部,其配置于所述平板部的所述一个方向的另一端侧,借助焊锡与所述其他布线图案接合;
第一连结部,其从所述平板部的所述一个方向的一端向下延伸,并且将所述平板部的所述一个方向的一端与所述电极接合部的一端连结;以及
第二连结部,其从所述平板部的所述一个方向的另一端向下延伸,并且将所述平板部的所述一个方向的另一端与所述基板接合部的一端连结,
所述电极接合部形成为从所述第一连结部被弯折而向所述一个方向的外侧延伸,所述基板接合部形成为从所述第二连结部被弯折而向所述一个方向的外侧延伸,
所述电极接合部的与所述裸芯片晶体管的电极的被接合面对置的接合面以及所述基板接合部的与所述其他的布线图案的被接合面对置的接合面具备脱气排出机构,该脱气排出机构使在所述金属板连接器的焊接时熔融的焊锡中产生的脱气从介于所述接合面与所述被接合面之间的焊锡排出。
2.一种半导体模块,其特征在于,
该半导体模块具备:
金属制的基板;形成于所述基板上的绝缘层;
形成于所述绝缘层上的多个布线图案;
借助焊锡被安装在所述多个布线图案中的一个布线图案上的裸芯片晶体管;以及
由金属板构成的金属板连接器,其将形成于所述裸芯片晶体管的上表面的电极与所述多个布线图案中的其他布线图案接合,
所述金属板连接器具备如下部分而呈桥形:
平板部;
电极接合部,其配置于所述平板部的一个方向的一端侧,借助焊锡与所述裸芯片晶体管的电极接合;
基板接合部,其配置于所述平板部的所述一个方向的另一端侧,借助焊锡与所述其他布线图案接合;
第一连结部,其从所述平板部的所述一个方向的一端向下延伸,并且将所述平板部的所述一个方向的一端与所述电极接合部的一端连结;以及
第二连结部,其从所述平板部的所述一个方向的另一端向下延伸,并且将所述平板部的所述一个方向的另一端与所述基板接合部的一端连结,
所述电极接合部形成为从所述第一连结部被弯折而向所述一个方向的外侧延伸,并且形成为,在与所述平板部垂直的方向上,所述电极接合部的一端与所述平板部的距离小于另一端与所述平板部的距离,所述电极接合部的接合面相对于所述裸芯片晶体管的电极的与该接合面对置的被接合面倾斜,
所述基板接合部形成为从所述第二连结部被弯折而向所述一个方向的外侧延伸,并且形成为,在与所述平板部垂直的方向上,所述基板接合部的一端与所述平板部的距离小于另一端与所述平板部的距离,所述基板接合部的接合面相对于所述其他布线图案的与该接合面对置的被接合面倾斜。
3.根据权利要求2所述的半导体模块,其中,
所述电极接合部的接合面与所述裸芯片晶体管的电极的被接合面所成的倾斜角度及所述基板接合部的接合面与所述其他布线图案的被接合面所成的倾斜角度为0.5°以上且7.5°以下。
4.根据权利要求1~3中的任一项所述的半导体模块,其中,
所述电极接合部的与所述一个方向垂直的方向上的宽度比所述基板接合部的与所述一个方向垂直的方向上的宽度窄。
5.根据权利要求1~4中的任一项所述的半导体模块,其中,
在所述平板部的与所述一个方向垂直的方向上的两端分别形成有从该两端向下弯折的平衡肋部。
6.根据权利要求1~5中的任一项所述的半导体模块,其中,
所述电极接合部及所述基板接合部的厚度比所述金属板连接器的其他部分的厚度大。
7.根据权利要求1~5中的任一项所述的半导体模块,其中,
所述平板部的厚度比所述金属板连接器的其他部分的厚度大。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3193406A4 (en) * 2014-09-11 2018-08-15 NSK Ltd. Multipolar lead component, and connection device for substrate
JP6364556B1 (ja) * 2017-02-20 2018-07-25 新電元工業株式会社 電子装置
CN107039384B (zh) * 2017-04-29 2020-07-24 深圳市劲阳电子有限公司 一种贴片式元件
EP3792961A4 (en) * 2018-05-08 2021-04-07 Mitsubishi Electric Corporation WIRING ELEMENT AND SEMICONDUCTOR MODULE INCLUDING IT
CN111886695A (zh) * 2018-10-05 2020-11-03 富士电机株式会社 半导体装置、半导体模块及车辆
JP7329919B2 (ja) * 2018-12-07 2023-08-21 新電元工業株式会社 半導体装置、半導体装置の製造方法及びクリップリード
US11557564B2 (en) * 2019-04-08 2023-01-17 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device
TWI726313B (zh) * 2019-04-30 2021-05-01 作同 柯 功率半導體
DE112023000186T5 (de) 2022-04-25 2024-05-02 Fuji Electric Co., Ltd. Halbleitervorrichtung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008258649A (ja) * 2008-06-06 2008-10-23 Sanyo Electric Co Ltd 半導体装置
JP2010034350A (ja) * 2008-07-30 2010-02-12 Sanyo Electric Co Ltd 半導体装置
JP2012235010A (ja) * 2011-05-06 2012-11-29 Denso Corp 電子装置
CN103268877A (zh) * 2012-02-15 2013-08-28 瑞萨电子株式会社 半导体器件及其制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10144841A (ja) 1996-11-14 1998-05-29 Sony Corp リード成形方法およびリード形状修正装置
US5872403A (en) * 1997-01-02 1999-02-16 Lucent Technologies, Inc. Package for a power semiconductor die and power supply employing the same
JP2002246721A (ja) 2001-02-14 2002-08-30 Matsushita Electric Ind Co Ltd 半導体装置
JP2006114571A (ja) 2004-10-12 2006-04-27 Hitachi Ltd 半導体装置およびこれを実装した電子機器
JP4764692B2 (ja) * 2005-09-29 2011-09-07 日立オートモティブシステムズ株式会社 半導体モジュール
JP4777745B2 (ja) 2005-11-01 2011-09-21 セイコーインスツル株式会社 圧電振動子及びこれを備える発振器、電波時計並びに電子機器
JP2008016469A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置
JP2011243752A (ja) 2010-05-18 2011-12-01 Panasonic Corp 半導体装置の製造方法、半導体内部接続部材および半導体内部接続部材群
JP5578326B2 (ja) 2011-03-29 2014-08-27 日立金属株式会社 リード部品及びその製造方法、並びに半導体パッケージ
JP6043049B2 (ja) 2011-03-30 2016-12-14 株式会社東芝 半導体装置の実装構造及び半導体装置の実装方法
JP2012212713A (ja) * 2011-03-30 2012-11-01 Toshiba Corp 半導体装置の実装構造
US8399997B2 (en) * 2011-06-10 2013-03-19 Shanghai Kalhong Electronic Company Limited Power package including multiple semiconductor devices
JP5555206B2 (ja) * 2011-07-11 2014-07-23 株式会社 日立パワーデバイス 半導体パワーモジュール
US8895998B2 (en) * 2012-03-30 2014-11-25 Cree, Inc. Ceramic-based light emitting diode (LED) devices, components and methods
WO2014041601A1 (ja) * 2012-09-11 2014-03-20 株式会社メイコー 部品内蔵基板の製造方法及びこの方法を用いて製造した部品内蔵基板
US8636198B1 (en) * 2012-09-28 2014-01-28 Sunpower Corporation Methods and structures for forming and improving solder joint thickness and planarity control features for solar cells
EP2916353B1 (en) * 2012-11-05 2017-07-26 NSK Ltd. Semiconductor module
CN103918066B (zh) * 2012-11-05 2016-08-24 日本精工株式会社 半导体模块
EP2916349B1 (en) * 2012-11-05 2021-03-03 NSK Ltd. Semiconductor module
EP2757582A1 (en) * 2013-01-17 2014-07-23 Nxp B.V. Packaged electrical components

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008258649A (ja) * 2008-06-06 2008-10-23 Sanyo Electric Co Ltd 半導体装置
JP2010034350A (ja) * 2008-07-30 2010-02-12 Sanyo Electric Co Ltd 半導体装置
JP2012235010A (ja) * 2011-05-06 2012-11-29 Denso Corp 電子装置
CN103268877A (zh) * 2012-02-15 2013-08-28 瑞萨电子株式会社 半导体器件及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MERVI PAULASTO ET AL.: "Reliability of flip chip die attach in multichip mcchatronic power module", 《IEEE》 *

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