CN103871959A - 互连结构及其制造方法 - Google Patents

互连结构及其制造方法 Download PDF

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CN103871959A
CN103871959A CN201210548617.8A CN201210548617A CN103871959A CN 103871959 A CN103871959 A CN 103871959A CN 201210548617 A CN201210548617 A CN 201210548617A CN 103871959 A CN103871959 A CN 103871959A
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dielectric layer
manufacture method
interconnection structure
hard mask
silane
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CN103871959B (zh
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周鸣
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to US15/240,260 priority patent/US20160358811A1/en
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Abstract

本发明提供一种互连结构及其制造方法。所述制造方法包括：在基底上形成含碳的介质层；采用含硅、氢的气体对所述介质层进行表面处理，以形成用于抑制碳损失的保护层；在所述保护层上形成硬掩模；以所述硬掩模对所述介质层进行图形化，以形成连接插塞。所述互连结构为所述互连结构的制造方法所形成的互连结构。本发明提高了互连结构的制造良率，还提高了互连结构的可靠性。

Description

互连结构及其制造方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种互连结构及其制造方法。
背景技术
现今集成电路设计和制造领域所遇到的一个挑战是如何降低信号传输RC延迟(Resistive Capacitive delay)，对此，现在技术已经采用的一种方法是将铝金属层替换为铜金属层，降低金属层串联电阻；还有一种方法是降低金属层之间的寄生电容，这可以通过在金属层之间的介质层中构造多孔的(Porous)低介电常数(即低k)材料或者空气隙(Air Gap)来实现。
在公开号为US7279427B2的美国专利中公开了一种互连结构的制造方法，参考图1，示出了所述美国专利中互连结构的示意图。所述互连结构的制造方法包括：提供基底5，所述基底5中形成有半导体元件；在基底5上形成低k介质层4；在低k介质层4上形成掩模6；通过所述掩模6对所述低k介质层4进行图形化，以形成通孔(图未示)；在所述通孔中填充金属材料，以形成与所述半导体元件相连的连接插塞。
然而实际工艺中发现，互连结构中低k介质层与所述掩模之间容易出现底切(undercut)现象。
参考图2，示出了现有技术一种具有底切现象的互连结构的示意图。在所述互连结构的制造过程中，以硬掩模12为掩模，通过湿法蚀刻对所述低k介质层11进行图形化之后，在低k介质层11与所述硬掩模12的交界面处会形成底切13。严重情况下，所述底切13的尺寸能达到5nm。所述底切13的存在容易导致硬掩模12剥离等的问题，从而影响互连结构的制造良率，严重地，还会影响互连结构的可靠性。
发明内容
本发明解决的是提供一种互连结构及其制造方法，以提高互连结构的制造良率。
为了解决上述技术问题，本发明提供一种互连结构的制造方法，包括：在基底上形成含碳的低k介质层；采用含硅、氢的气体对所述低k介质层进行表面处理，以形成用于抑制碳损失的保护层；在所述保护层上形成硬掩模；以所述硬掩模对所述低k介质层进行图形化，以形成连接插塞。
相应地，本发明还提供一种由所述的互连结构的制造方法所形成的互连结构。
与现有技术相比，本发明具有以下优点：
在介质层表面形成抑制碳损失的保护层，可以使介质层表面在图形化的工艺中的去除速率与表面下方的介质层保持一致，从而减弱甚至防止图形化工艺中的底切问题。
附图说明
图1为现有技术中互连结构的制造方法的示意图；
图2是现有技术一种具有底切现象的互连结构的示意图；
图3至图7是本发明互连结构制造方法一实施例的示意图。
具体实施方式
在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施的限制。
其次，本发明利用示意图进行详细描述，在详述本发明实施例时，为便于说明，所述示意图只是实例，其在此不应限制本发明保护的范围。
为了解决现有技术的问题，发明人对现有技术中的互连结构进行了大量研究，发明人发现互连结构的制造过程中之所以会出现底切现象，是因为在介质层上形成硬掩模时，由于硬掩模的形成采用了氧等离子体，氧与低k介质层表面的碳容易发生反应，因此造成低k介质层表面碳损失的问题，图形化工艺对碳损失后的介质层表面具有较高的去除速率，因而，在图形化工艺中，介质层表面与硬掩模接触的地方被过多地去除，从而造成底切。
相应地，本发明提供一种互连结构的制造方法，大致包括以下步骤：
步骤S1，在基底上形成含碳的介质层；
步骤S2，采用含硅、氢的气体对所述介质层进行表面处理，以形成用于抑制碳损失的保护层；
步骤S3，在所述保护层上形成硬掩模；
步骤S4，以所述硬掩模对所述介质层进行图形化，以形成连接插塞。
本发明通过在介质层表面形成抑制碳损失的保护层，可以保证介质层表面在图形化的工艺中的去除速率与表面下方的介质层保持一致，从而减弱甚至防止图形化工艺中容易出现底切的问题。
下面结合附图和具体实施例对本发明技术方案做详细说明。
参考图3至7，示出了本发明互连结构制造方法第一实施例的示意图。所述互连结构的制造方法大致包括以下步骤：
如图3，执行步骤S1，提供基底100；
本实施例中，所述基底100包括：形成有晶体管等半导体元件的衬底层(图未示)，形成于衬底层上的金属层(图未示)，形成于金属层上的阻挡层(图未示)。其中所述金属层用于通过本实施例形成的互连结构实现与其他器件的电连接。此处所述阻挡层用于防止金属层中金属的扩散。
具体地，金属层的材料为铜或铝。所述阻挡层的材料为掺氮的碳化硅(Nitrogen Doped Silicon Carbon，NDC)。但是本发明对金属层和阻挡层的材料不作限制。
如图4，继续执行步骤S1，先在基底100上形成介质材料，对所述介质材料进行紫外光处理，以形成含碳的低k介质层101(即低介电常数介质层)。此处“含碳的低k介质层”的含义是，在低k介质层101的材料中含有碳这种元素。
需要说明的是，此处介质层以低k介质层为例进行说明，但是本发明对此不作限制，在其他实施例中，所述介质层还可以是含碳的普通的介质层，或者为含碳的超低k介质层。本领域技术人员可以根据互连结构的设计规格，选择不同的介质层。
本实施例中，通过紫外光对所述介质材料进行辅助热处理，以形成一种多孔介质层。所述多孔介质层为常见低k介质层101的一种，但是本发明对低k介质层101的材料不作限制。
具体地，可以通过二乙氧基甲基硅烷和原子转移自由基聚合形成所述多孔介质层。实际工艺中可以通过溶胶凝胶的方式形成所述多孔介质层。
需要说明的是，本发明对介质材料不作限制，对介质材料的形成方式也不作限制。此处所述介质材料还可以是SiCOH、SiCO、SiCON、黑金刚石中的一种或多种。还可以通过化学气相沉积的方式沉积所述介质材料。
本实施例通过二乙氧基甲基硅烷和原子转移自由基聚合形成的低k介质层101为含有碳元素的介质层。
如图5，执行步骤S2，采用硅烷对所述低k介质层101进行表面处理，以形成用于抑制碳损失的保护层102。具体地，所述硅烷提供硅和氢元素，而所述低k介质层101提供氧和碳，所述保护层102为在低k介质层101的表面形成含C、H、O、Si的致密薄膜。
需要说明的是，在本实施例中，采用硅烷进行表面处理，但是本发明对此不做限制，还可以采用其他含硅、氢的气体进行所述表面处理，以使形成的保护层102为含C、H、O、Si的致密薄膜。
还需要说明的是，本发明对保护层102的材料不作限制，只要形成的所述保护层102比较致密，可以起到保护低k介质层101的作用、使低k介质层101中的碳不损失或碳较少地损失即可。
所述保护层102用于抑制低k介质层101中碳的损失，从而使低k介质层101的表面在后续图形化步骤中不容易被去除，进而防止低k介质层101的表面处发生的底切问题，提高了互连结构的制造良率。
需要说明的是，如果硅烷的浓度过大，会与过多的低k介质层101发生反应，从而过多地减少低k介质层101的厚度；如果硅烷的浓度过小，则较难形成所述保护层102。
因此优选地，实际工艺中，采用硅烷和氦气对所述低k介质层进行表面处理的步骤，所述氦气起到载气的作用，具体工艺条件为：硅烷的浓度为100~300毫克每立方米；氦气的流量为2000~4000标况毫升每分；高频的功率为300~600瓦特；低频的功率为150~250瓦特；腔室内气压位于3~8托。
但是本发明对此不作限制，在其他实施例中，还可以采用硅烷和氩气对所述低k介质层进行表面处理。所述氩气也是起到载气的作用，具体工艺条件为：硅烷的浓度为100~300毫克每立方米；氩气的流量为1000~2000标况毫升每分；高频的功率为300~600瓦特；低频的功率为150~250瓦特；腔室内气压位于3~8托。
需要说明的是，由于本实施例通过紫外光处理的方式对介质材料进行表面处理，以形成多孔的低k介质层101。本实施例中，通过硅烷进行表面处理的过程中，可以在所述紫外光处理的腔室中对所述低k介质层进行原位的表面处理。
需要说明的是，通过原位方式进行表面处理，所述表面处理的步骤可以与现有设备实现良好的集成。此外，在进行表面处理时无需将待形成的互连结构从真空腔中去除并移至其他腔体内，可以减少工艺步骤，简化工艺。但是本发明对此不作限制，在其他实施例中，还可以不在紫外光处理的腔室中进行原位的表面处理，而是采用单独的步骤在单独的反应腔室中进行所述表面处理。
如图6所示，执行步骤S3，在所述保护层102上形成硬掩模103。
本实施例中，在所述保护层102上形成硬掩模103的步骤包括：通过等离子体增强正硅酸乙脂层(Plasma Enhanced Tetraethylorthosilicate，PETEOS)沉积的方式形成所述硬掩模103。所述硬掩模103的材料可以是二氧化硅。但是，本发明对硬掩模103的材料不做限制，对硬掩模103的形成工艺也不作限制。
通过等离子体增强正硅酸乙脂层形成硬掩模103的过程中，优选地，所述等离子体为非氧的等离子体。即不采用氧的等离子体形成所述硬掩模103，这样可以进一步防止部分氧等离子体穿过所述保护层102、与所述低k介质层101反应所引起的碳损失的问题。
如图7所示，执行步骤S4，以所述硬掩模103对所述低k介质层101进行图形化。所述图形化工艺包括：通过光刻和蚀刻的方法以所述硬掩模对所述低k介质层101进行图形化。通过所述图形化工艺可以在所述低k介质层101中形成露出基底100的通孔104。
由于保护层102起到了保护低k介质层101的作用，因此低k介质层101的表面不会有过多碳的损失。因此，蚀刻工艺对与所述硬掩模103相接触的、处于表面的低k介质层101的去除速率与对处于表面下方的低k介质层101的去除速率保持一致，从而可以防止低k介质层101与硬掩模103相接触的位置处被过多地去除而引起的底切现象，进而防止了硬掩模103容易剥离的问题，提高了互连结构的制造良率。
在本实施例中，所述蚀刻的步骤包括：通过湿法蚀刻进行图形化。需要说明的是，此处所述湿法蚀刻的步骤包括：通过稀释的氢氟酸进行湿法蚀刻。但是本发明对蚀刻的方法不作限制。还可以采用干刻的方法进行蚀刻，也可以采用其他溶液的湿法蚀刻进行蚀刻。基于所述保护层102的保护，所述蚀刻对低k介质层101表面及表面下方的材料的速率均能保持一致。
需要说明的是，本实施例中所述通孔104露出所述基底100中的金属层。所述互连结构的制造方法还包括：向所述通孔104中填充金属材料以形成连接插塞，所述连接插塞用于实现所述基底100中的金属层与其他器件的电连接。
所述互连结构的制造方法还包括化学机械研磨等的步骤。具体地，所述化学机械研磨用于去除多余的金属材料，还用于去除所述硬掩模103和所述保护层102，以露出所述低k介质层101和连接插塞。其他步骤与现有技术相同，在此不再赘述。
本发明提供的互连结构的制造方法，抑制了介质层和硬掩模交界处的底切现象的发生，提高了互连结构的制造良率。
相应地，本发明还提供一种由所述的互连结构的制造方法所形成的互连结构。所述互连结构的制造方法可参考上述内容，此处不再赘述。
通过所述制造方法形成的互连结构提高了互连结构电连接可靠性。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (17)

1.一种互连结构的制造方法，其特征在于，包括：
在基底上形成含碳的介质层；
采用含硅、氢的气体对所述介质层进行表面处理，以形成用于抑制碳损失的保护层；
在所述保护层上形成硬掩模；
以所述硬掩模对所述介质层进行图形化，以形成连接插塞。
2.如权利要求1所述的互连结构的制造方法，其特征在于，所述介质层为低k介质层或超低k介质层。
3.如权利要求1所述的互连结构的制造方法，其特征在于，所述介质层由二乙氧基甲基硅烷和原子转移自由基聚合形成。
4.如权利要求1所述的互连结构的制造方法，其特征在于，所述介质层的材料为SiCOH、SiCO或SiCON。
5.如权利要求1所述的互连结构的制造方法，其特征在于，所述保护层的材料包含碳、硅、氢和氧。
6.如权利要求1所述的互连结构的制造方法，其特征在于，所述含硅、氢的气体为硅烷。
7.如权利要求6所述的互连结构的制造方法，其特征在于，采用硅烷对所述介质层进行表面处理的步骤包括：采用硅烷和氦气对所述介质层进行表面处理。
8.如权利要求7所述的互连结构的制造方法，其特征在于，采用硅烷和氦气对所述介质层进行表面处理的步骤中，硅烷的浓度为100~300毫克每立方米；氦气的流量为2000~4000标况毫升每分；高频的功率为300~600瓦特；低频的功率为150~250瓦特；腔室内气压位于3~8托。
9.如权利要求6所述的互连结构的制造方法，其特征在于，采用硅烷对所述介质层进行表面处理的步骤包括：采用硅烷和氩气对所述介质层进行表面处理。
10.如权利要求9所述的互连结构的制造方法，其特征在于，采用硅烷和氩气对所述介质层进行表面处理的步骤中，硅烷的浓度为100~300毫克每立方米；氩气的流量为1000~2000标况毫升每分；高频的功率为300~600瓦特；低频的功率为150~250瓦特；腔室内气压位于3~8托。
11.如权利要求1所述的互连结构的制造方法，其特征在于，在所述保护层上形成硬掩模的步骤包括：通过等离子体增强正硅酸乙脂层沉积的方法形成所述硬掩模。
12.如权利要求11所述的互连结构的制造方法，其特征在于，所述等离子体为非氧的等离子体。
13.如权利要求1所述的互连结构的制造方法，其特征在于，所述硬掩模的材料为二氧化硅。
14.如权利要求1所述的互连结构的制造方法，其特征在于，以所述硬掩模对所述介质层进行图形化的步骤包括：通过光刻和蚀刻的方法以所述硬掩模对所述介质层进行图形化。
15.如权利要求14所述的互连结构的制造方法，其特征在于，所述蚀刻的步骤包括：通过湿法蚀刻进行图形化。
16.如权利要求15所述的互连结构的制造方法，其特征在于，所述湿法蚀刻的步骤包括：通过稀释的氢氟酸进行湿法蚀刻。
17.一种如权利要求1-16中任意一权利要求所述的互连结构的制造方法所形成的互连结构。
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CN110783263B (zh) * 2019-08-26 2022-12-16 上海新微技术研发中心有限公司 半导体结构的形成方法

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