CN103854967A - 平坦化处理方法 - Google Patents

平坦化处理方法 Download PDF

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CN103854967A
CN103854967A CN201210505908.9A CN201210505908A CN103854967A CN 103854967 A CN103854967 A CN 103854967A CN 201210505908 A CN201210505908 A CN 201210505908A CN 103854967 A CN103854967 A CN 103854967A
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material layer
composition
grid
layer
sputter
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CN103854967B (zh
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朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

本申请公开了一种平坦化处理方法。一示例方法可以包括：对材料层进行构图；以及通过溅射，对构图后的材料层进行平坦化，其中，对材料层的构图使得对材料层进行溅射的负载条件在衬底上的不均匀性相比于构图前降低。

Description

平坦化处理方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种平坦化处理方法。
背景技术
在半导体工艺中，经常用到平坦化工艺，例如化学机械抛光(CMP)，以获得相对平坦的表面。然而，在通过CMP对材料层进行平坦化的情况下，如果需要研磨掉相对较厚的部分，则难以控制CMP后材料层的表面平坦度，例如控制到几个纳米之内。
另一方面，如果要对覆盖特征、特别是不一致(例如，长、宽等尺度不一致)特征的材料层进行平坦化，那么材料层由于特征的存在而可能出现凹凸起伏，因此可能导致平坦化不能一致地执行。
发明内容
本公开的目的至少部分地在于提供一种能够实现大致均匀的相对平坦表面的平坦化处理方法。
根据本公开的一个方面，提供了一种对衬底上形成的材料层进行平坦化的方法，包括：对材料层进行构图；以及通过溅射，对构图后的材料层进行平坦化，其中，对材料层的构图使得对材料层进行溅射的负载条件在衬底上的不均匀性相比于构图前降低。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-14示出了制造半导体器件的示例流程，其中利用了根据本公开实施例的平坦化处理方法；
图3a示出了根据本公开另一实施例的图3所示操作的替代操作；
图5a示出了根据本公开另一实施例的图5所示操作的替代操作；
图9a示出了根据本公开另一实施例的图9所示操作的替代操作；以及
图11a示出了根据本公开另一实施例的图11所示操作的替代操作。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的示例，可以通过溅射(sputtering)，例如Ar或N等离子体溅射，来对材料层进行平坦化处理。通过这种溅射平坦化处理，而非常规的CMP平坦化处理，可以实现更加平坦的材料层表面。这种材料层可以包括半导体制造工艺中使用的多种材料层，例如，包括但不限于绝缘体材料层、半导体材料层和导电材料层。
另外，在进行溅射时，可能存在负载效应(loading effect)。所谓“负载相应”，是指溅射所针对的材料层上存在的图案以及图案的密度(或者说，材料层的形貌)等将会影响溅射后材料层的厚度和/或形貌等。因此，为了获得较为平坦的表面，优选地在溅射时考虑负载效应。
例如，如果材料层由于之下存在(凸出的)特征而存在凸起，那么相对于其他没有凸起的部分而言，存在凸起的部分需要经受“更多”的溅射，才能与其他部分保持平坦。在此，所谓“更多”的溅射，例如是指在相同的溅射参数(如，溅射功率和/或气压)情况下，需要进行更长时间的溅射；或者，在相同溅射时间的情况下，溅射强度的更大(如，溅射功率和/或气压更大)；等等。也就是说，对于溅射而言，这种凸起对应的负载条件(loading condition)更大。
另一方面，如果材料层由于之下存在(凹入的)特征而存在凹陷，那么相对于其他没有凹陷的部分而言，存在凹陷的部分需要经受“更少”的溅射，才能与其他部分保持平坦。也就是说，对于溅射而言，这种凹陷对应的负载条件更小。
另外，如果存在多个不一致(例如长、宽等尺度不一致)的特征，那么材料层可能由于特征而具有非一致的凸起和/或凹陷，因此导致负载条件在衬底上发生变化。例如，对于凸起而言，尺度较大凸起的负载条件要高于尺度较小凸起的负载条件；而对于凹陷而言，尺度较大凹陷的负载条件要低于尺度较小凹陷的负载条件。非一致的负载条件可能不利于溅射均匀地进行。
根据本公开的示例，在通过溅射对材料层进行平坦化的处理中，可以结合光刻，以便能够实现选择性平坦化。例如，在进行溅射之前，可以通过光刻对材料层进行构图。在构图时，考虑将要进行的溅射的负载条件。具体地，可以对材料层如此进行构图，使得对材料层进行溅射的负载条件在衬底上的不均匀性相比于构图前降低。这样，之后的溅射可以在衬底上大致均匀地进行，从而有助于获得平坦的表面。
根据一优选实施例，可以对材料层进行构图，使得对于构图后的材料层，溅射的负载条件在衬底上具有(局部或全局)大致均匀的分布。具体地，可以对材料层进行构图，使得构图后的材料层存在(局部或全局)大致均匀分布的突起部。
根据另一实施例，可以对材料层进行构图，以去除材料层中负载条件相对高的部分。例如，可以去除材料层中由于之下的特征而存在的凸起。
上述特征可以包括能够在衬底上形成的各种特征，例如，包括但不限于衬底上的凸出特征如栅、鳍等，和/或衬底上的凹入特征如替代栅工艺中去除牺牲栅而形成的栅槽等。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1所示，提供衬底1000。该衬底1000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在衬底1000上，可以形成浅沟槽隔离(STI)1002，以隔离各器件的有源区。例如，STI1002可以保护氧化物(如，氧化硅)。
在衬底1000上，可以形成(牺牲)栅堆叠100-1、100-2。栅堆叠100-1包括在衬底1000上依次形成的牺牲栅介质层1004-1和牺牲栅导体层1006-1，以及在牺牲栅介质层1004-1和牺牲栅导体层1006-1侧壁上形成的栅侧墙1008-1。同样，栅堆叠100-2包括在衬底1000上依次形成的牺牲栅介质层1004-2和牺牲栅导体层1006-2，以及在牺牲栅介质层1004-2和牺牲栅导体层1006-2侧壁上形成的栅侧墙1008-2。例如，牺牲栅介质层1004-1和1004-2可以包括氧化物(如，氧化硅)，牺牲栅导体层1006-1和1006-2可以包括多晶硅，栅侧墙1008-1和1008-2可以包括氮化物(如，氮化硅)。另外，还在衬底1000中在栅堆叠100-1、100-2两侧，例如通过离子注入，形成了器件的源/漏区S/D。本领域技术人员知道多种方法来形成这种栅堆叠和源/漏区，在此不再赘述。
在图1所示的示例中，为了获得具有不同驱动能力的器件，栅堆叠100-1和栅堆叠100-2各自的栅长不一致。例如，栅堆叠100-2的栅长大于栅堆叠100-1的栅长。
这里需要指出的是，尽管在图1的示例中示出了两个栅堆叠，但是本公开不局限于栅堆叠的具体数目。例如，可以存在一个或者三个乃至更多的栅堆叠。另外，在图1的示例中，描述了利用牺牲栅堆叠的后栅工艺，但是本公开也可以应用于先栅工艺。
接下来，如图2所示，可以在衬底上例如通过淀积形成层间电介质(ILD)层1012。例如，ILD层1012可以包括氧化物，其厚度足以覆盖栅堆叠100-1、100-2。优选地，在淀积氧化物的ILD层1012之前，还可以先淀积氮化物的衬层1010。该氮化物衬层1010的厚度可以为约5-50nm。
从图2清楚可见，由于栅堆叠100-1、100-2的存在，ILD层1012的顶面存在凹凸起伏。为此，需要对ILD层1012进行平坦化。根据本公开的优选实施例，在进行平坦化之前，可以对ILD层1012进行构图，以降低随后的平坦化(例如，溅射)的负载条件在衬底上的不均匀性。
具体地，如图3所示，可以在ILD层1012上涂覆光刻胶1014，并通过掩模进行曝光、显影等操作对光刻胶1014进行构图。在对光刻胶1014进行构图时考虑随后进行的溅射的负载条件。具体地，在图3所示的示例中，将光刻胶1014构图为使得在随后利用该构图的光刻胶1014为掩模对ILD层1012进行构图时，构图后的ILD层1012上存在大致均匀分布的突起部。例如，可以根据用来形成栅堆叠100-1、100-2的掩模(确定栅堆叠100-1、100-2的位置和形状等，并因此部分地确定ILD层1012的起伏特性)，来设计用来对光刻胶1014进行曝光的掩模。
随后，如图4所示，利用构图的光刻胶1014为掩模，对ILD层1012进行构图，例如反应离子刻蚀(RIE)。在此，控制对ILD层1012的构图，使得大致停止于ILD层1012的最低顶面(图4中虚线所示的表面)附近，例如最低顶面的上下约50nm之间的范围处。ILD层1012的最低顶面例如可以根据淀积的ILD层1012的厚度确定。另外，可以根据RIE的刻蚀速度等工艺参数，来确定对ILD层1012构图的停止点。之后，可以去除光刻胶1014。
这样，ILD层1012上形成了多个突起部1016。可以看到，这多个突起部1016在衬底上的分布大致是均匀的(例如，大小相当和/或间距相当)。
然后，如图5所示，可以对ILD层1012进行溅射，来对ILD层1012进行平坦化处理。例如，溅射可以使用等离子体，如Ar或N等离子体。在此，例如可以根据等离子体溅射对ILD层1012的切削速度，控制溅射参数例如溅射功率和气压等，来确定进行等离子体溅射的时间，使得等离子体溅射能够执行一定的时间段以充分平滑ILD层1012的表面。由于如上所述，突出部1016在衬底上具有大致均匀的分布，因此在溅射时，溅射的负载条件在衬底上也具有大致均匀的分布。从而，溅射可以大致均匀地执行，并因此可以实现更加平坦的表面。
图6示出了通过溅射进行平坦化之后的结果。尽管在图6中示出了微观上的起伏，但是事实上ILD层1012的顶面具有充分的平坦度，其起伏可以控制在几个纳米之内。在图6所示的示例中，等离子体溅射可以在到达栅堆叠100-1、100-2的顶面之前结束，以避免对栅堆叠造成损伤。根据本公开的另一实施例，还可以根据需要，对通过溅射平坦化后的ILD层1012进行少许CMP。
在ILD层1012的表面通过等离子体溅射而变得充分平滑之后，如图7所示，可以对ILD层1012进行回蚀(例如，RIE)，并进一步回蚀氮化物衬层1010(如果存在的话)，以露出栅堆叠100-1、100-2(具体地，露出牺牲栅导体1006-1、1006-2)。由于回蚀之前ILD层1012的表面通过溅射而变得平滑，所以回蚀之后ILD层1012的表面在衬底上基本上保持平坦。
在如上所述形成平坦的ILD层1012之后，可以进行替代栅工艺，以形成最终半导体器件的真正栅堆叠。以下，将描述替代栅工艺的一个示例。但是需要指出的是，本公开不限于替代栅工艺的具体实现。
具体地，如图8所示，例如通过RIE，选择性去除牺牲栅导体层1006-1、1006-2和牺牲栅介质层1004-1、1004-2，从而在栅侧墙1008-1、1008-2内侧留下了栅槽。可以通过向栅槽中填充栅介质层和栅导体层来形成栅堆叠。例如，可以通过淀积，依次形成栅介质层1018和栅导体层1022。栅介质层1018可以包括高K栅介质例如HfO2，厚度为约2-5nm。栅导体层1022可以包括金属栅导体如W等，其厚度足以填满栅槽。优选地，在栅介质层1018和栅导体层1022之间还可以形成功函数调节层1020。功函数调节层1020例如可以包括TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTa、NiTa、MoN、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSi、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx及其组合，厚度可以约为2-10nm。优选地，在形成栅介质层1018之前，还可以淀积一薄界面层(未示出)。界面层例如包括氧化物(例如，氧化硅)，厚度为约0.2-1.2nm。
在图8所示的示例中，由于牺牲栅堆叠100-1去除之后形成的栅槽(具体地，其栅长)较小，因此其上形成的栅导体层1022中不存在明显的凹入。
在此，同样可以利用根据本公开的技术来对栅导体层1022进行平坦化。具体地，如图9所示，可以在栅导体层1022上形成构图的光刻胶1024。如上所述，将光刻胶1024构图为使得在随后利用该构图的光刻胶1024为掩模对栅导体层1022进行构图时，构图后的栅导体层1022上存在大致均匀分布的突起部。例如，可以根据用来形成栅堆叠100-1、100-2的掩模(确定栅堆叠100-1、100-2的位置和形状等，从而确定栅槽的位置，并因此部分地确定栅导体层1022的起伏特性)，来设计用来对光刻胶1024进行曝光的掩模。
随后，如图10所示，利用构图的光刻胶1024为掩模，对栅导体层1022进行构图，例如RIE。在此，控制对栅导体层1022的构图，使得大致停止于栅导体层1022位于较宽栅槽中部的顶面(图10中虚线所示的表面)附近，例如该顶面的上下约50nm之间的范围处。栅导体层1022在较宽栅槽中部的顶面例如可以根据淀积的栅导体层1022的厚度确定。另外，可以根据RIE的刻蚀速度等工艺参数，来确定对栅导体层1022构图的停止点。之后，可以去除光刻胶1024。
这样，栅导体层1022上形成了多个突起部1026。可以看到，这多个突起部1026在衬底上的分布大致是均匀的(例如，大小相当和/或间距相当)。
然后，如图11所示，可以对栅导体层1022进行溅射，来对栅导体层1022进行平坦化处理。例如，溅射可以使用等离子体，如Ar或N等离子体。在此，例如可以根据等离子体溅射对栅导体层1022的切削速度，控制溅射参数例如溅射功率和气压等，来确定进行等离子体溅射的时间，使得等离子体溅射能够执行一定的时间段以充分平滑栅导体层1022的表面。由于如上所述，突出部1026在衬底上具有大致均匀的分布，因此在溅射时，溅射的负载条件在衬底上也具有大致均匀的分布。从而，溅射可以大致均匀地执行，并因此可以实现更加平坦的表面。
图12示出了通过溅射进行平坦化之后的结果。尽管在图12中示出了微观上的起伏，但是事实上栅导体层1022的顶面具有充分的平坦度，其起伏可以控制在几个纳米之内。根据本公开的另一实施例，还可以根据需要，对通过溅射平坦化后的栅导体层1022进行少许CMP。
在溅射时，优选地将栅导体层1022接地，以避免等离子体损伤栅介质层。为了保证用于每一栅堆叠的栅导体在溅射过程中始终接地，优选地溅射停止时用于各栅堆叠的栅导体层1022尚未断开，而是保持连续(如图12所示，在功函数调节层1018上方尚存在一薄层栅导体层1022)，从而可以确保整个栅导体层1022接地。
在栅导体层1022的表面通过等离子体溅射而变得充分平滑之后，如图13所示，可以对栅导体层1022进行回蚀(例如，RIE)，并进一步回蚀功函数调节层1020(如果存在的话)，使得它们位于栅槽之内。可选地，也可以对栅介质层1018进行回蚀。由于回蚀之前栅导体层1022的表面通过溅射而变得平滑，所以回蚀之后栅导体层1022的表面在衬底上基本上保持平坦。
随后，如图14所示，可以进行后继工艺，以完成半导体器件。例如，可以在图13所示的结构上通过淀积形成另一ILD层1028。该ILD层1028也可以包括氧化物。可以对该ILD层1028进行平坦化，例如，化学机械抛光(CMP)或者溅射。然后，在与源/漏区相对应的位置处，形成接触孔。接触孔可以从ILD层1028的表面延伸进入源/漏区中。向接触孔中填充导电材料如W、Cu等，以形成接触部1030。为了增加接触部1030与源/漏区之间的接触，在形成接触孔之后，可以首先进行硅化处理，以在源/漏区上/中形成金属硅化物(未示出)，然后再向接触孔中填充导电材料。
尽管在以上实施例中，描述了在衬底上形成栅长不一致的两个栅堆叠的情况。但是，本公开不限于此。例如，本公开也可以适用于仅形成单个栅堆叠的情况(可以参见图8-9所示的示例，其中尽管图示了两个栅堆叠，但是左侧的栅堆叠对于栅导体层的表面形貌没有明显影响，与只形成单个栅堆叠的情况类似)，或者三个乃至更多栅堆叠的情况。另外，栅堆叠的栅长无需一定不同，它们也可以相同。
另外，降低衬底上负载条件的不均匀性的操作不限于上述实施例。
例如，代替以上图3所示的操作，如图3a所示，可以在ILD层1012上涂覆光刻胶1014a，并通过掩模进行曝光、显影等操作对光刻胶1014a进行构图。在此，可以将光刻胶1014a构图为露出ILD层1012上由于之下的特征(栅堆叠100-1、100-2)而存在的凸起(其对应的负载条件较高)，使得在随后进行构图时可以至少部分地去除这些凸起，从而降低其负载条件。例如，可以根据用来形成栅堆叠100-1、100-2的掩模(确定栅堆叠100-1、100-2的位置和形状等，并因此部分地确定ILD层1012的起伏特性)，来设计用来对光刻胶1014a进行曝光的掩模。
以如此构图的光刻胶1014a对ILD层1012进行构图(例如，RIE)，可以得到突起部1016a(参见图5a)。突起部1016a的宽度D大致取决于掩模的对准(overlay)以及所淀积ILD层1012上凸起的侧壁外观。例如，由于工艺限制，D可以在大约10-1000nm的范围内。一般而言，D越小，则效果越佳。
然后，代替以上图5的操作，如图5a所示，对ILD层1012进行溅射，来对ILD层1012进行平坦化处理。溅射的控制条件可以与以上结合图5描述的条件相同。在此，尽管仍然存在突起部1016a，但是与构图之前的ILD层1012相比，栅堆叠100-1、100-2上方的负载条件大大降低从而与其他大部分ILD层1012上的负载条件大致相当，从而整个衬底上负载条件的不均匀性可以降低。
同样，例如，代替以上图9所示的操作，如图9a所示，可以在栅导体层1022上涂覆光刻胶1024a，并通过掩模进行曝光、显影等操作对光刻胶1024a进行构图。在此，可以将光刻胶1024a构图为遮蔽栅导体层1022上由于之下的特征(栅槽)而存在的凹陷(其对应的负载条件较小)，使得在随后进行构图时可以至少部分地去除这些凹陷之外(相对于这些凹陷)的升高部分，从而降低其负载条件。例如，可以根据用来形成栅堆叠100-1、100-2的掩模(确定栅堆叠100-1、100-2的位置和形状等，从而确定栅槽的位置，并因此部分地确定栅导体层1022的起伏特性)，来设计用来对光刻胶1024a进行曝光的掩模。
这里需要指出的是，在图9a所示的示例中，同图8的示例中一样，图中左侧的栅槽(具体地，其栅长)较小，因此其上形成的栅导体层1022中不存在明显的凹入。因此，光刻胶1024a可以并不遮蔽于其上。
一般而言，当衬底上形成有凹入特征且在其上淀积材料层时，如果淀积的材料层厚度大于凹入特征宽度的二分之一，则淀积的材料层在凹入特征上不存在明显的凹陷。
因此，在利用形成栅堆叠100-1、100-2的掩模来设计用来对光刻胶1024a进行曝光的掩模时，可以考虑不在栅长较短(例如，短于淀积的栅导体层1022厚度的两倍)的位置处留有光刻胶。
以如此构图的光刻胶1024a对栅导体层1022进行构图(例如，RIE)，可以得到突起部1026a(参见图11a)。突起部1026a的宽度D′大致取决于掩模的对准(overlay)以及所淀积栅导体层1022上凹入的侧壁外观。例如，由于工艺限制，D′可以在大约10-1000nm的范围内。一般而言，D′越小，则效果越佳。
然后，代替以上图11的操作，如图11a所示，对栅导体层1022进行溅射，来对栅导体层1022进行平坦化处理。溅射的控制条件可以与以上结合图11描述的条件相同。在此，尽管仍然存在突起部1026a，但是与构图之前的栅导体层1022相比，栅槽上方的负载条件(原本由于凹陷而较小)已经与其他大部分栅导体层上的负载条件大致相当，从而整个衬底上负载条件的不均匀性可以降低。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (15)

1.一种对衬底上形成的材料层进行平坦化的方法，包括：
对材料层进行构图；以及
通过溅射，对构图后的材料层进行平坦化，
其中，对材料层的构图使得对材料层进行溅射的负载条件在衬底上的不均匀性相比于构图前降低。
2.根据权利要求1所述的方法，其中，所述衬底上形成有多个不一致的特征，所述材料层形成于衬底上覆盖所述特征。
3.根据权利要求1所述的方法，其中，对材料层进行构图，使得构图后的材料层存在大致均匀分布的突起部。
4.根据权利要求2所述的方法，其中，对材料层进行构图包括：
在材料层上涂覆光刻胶；
利用掩模对光刻胶进行构图；以及
利用构图后的光刻胶为掩模，对材料层进行构图，
其中，利用形成所述特征的掩模来设计用来对光刻胶进行构图的掩模，使得构图后的材料层存在大致均匀分布的突起部。
5.根据权利要求1所述的方法，其中，对材料层进行构图，以去除材料层中负载条件相对高的部分的至少一部分。
6.根据权利要求2所述的方法，其中，对材料层进行构图包括：
在材料层上涂覆光刻胶；
利用掩模对光刻胶进行构图，使得露出材料层上由于所述特征而存在的凸起的至少一部分和/或遮蔽材料层上由于所述特征而存在的凹陷；以及
利用构图后的光刻胶为掩模，对材料层进行构图，
其中，利用形成所述特征的掩模来设计用来对光刻胶进行构图的掩模。
7.根据权利要求2所述的方法，其中，所述特征是衬底上的凸出特征，并且对材料层的构图停止于材料层的大致最低顶面附近。
8.根据权利要求2所述的方法，其中，所述特征包括栅长不一致的多个栅极，且对材料层的构图停止于材料层的大致最低顶面上下约50nm之间的范围处。
9.根据权利要求8所述的方法，其中，所述材料层包括氧化物，且介由氮化物衬层形成于衬底上。
10.根据权利要求2所述的方法，其中，所述特征是衬底上的凹入特征，并且对材料层的构图停止于材料层的大致最低顶面左右。
11.根据权利要求2所述的方法，其中，所述特征包括栅长不一致的多个栅槽，该方法还包括：
在所述栅槽中形成栅介质层和栅导体层，
其中，所述材料层包括栅导体层，且对材料层的构图停止于栅导体层位于较宽栅槽中部的大致顶面位置处。
12.根据权利要求1所述的方法，其中，利用Ar或N等离子体进行溅射。
13.根据权利要求1所述的方法，其中，在溅射之后，该方法还包括：进行化学机械抛光处理。
14.根据权利要求11所述的方法，其中，在溅射时，使材料层接地。
15.根据权利要求14所述的方法，其中，溅射结束时，材料层是连续的。
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