CN103594433A - 一种制作刚柔结合板的三维封装散热结构的方法 - Google Patents
一种制作刚柔结合板的三维封装散热结构的方法 Download PDFInfo
- Publication number
- CN103594433A CN103594433A CN201310533103.XA CN201310533103A CN103594433A CN 103594433 A CN103594433 A CN 103594433A CN 201310533103 A CN201310533103 A CN 201310533103A CN 103594433 A CN103594433 A CN 103594433A
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- chip
- rigid substrates
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 230000017525 heat dissipation Effects 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 110
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052802 copper Inorganic materials 0.000 claims abstract description 32
- 239000010949 copper Substances 0.000 claims abstract description 32
- 238000005452 bending Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 8
- 229910000831 Steel Inorganic materials 0.000 claims abstract description 7
- 239000010959 steel Substances 0.000 claims abstract description 7
- 230000001680 brushing effect Effects 0.000 claims abstract description 4
- 238000010992 reflux Methods 0.000 claims abstract description 4
- 229910000679 solder Inorganic materials 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 238000009434 installation Methods 0.000 claims description 6
- 239000006071 cream Substances 0.000 claims description 4
- 230000005496 eutectics Effects 0.000 claims description 3
- 238000003466 welding Methods 0.000 abstract 2
- 238000003825 pressing Methods 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310533103.XA CN103594433B (zh) | 2013-10-31 | 2013-10-31 | 一种制作刚柔结合板的三维封装散热结构的方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310533103.XA CN103594433B (zh) | 2013-10-31 | 2013-10-31 | 一种制作刚柔结合板的三维封装散热结构的方法 |
Publications (2)
Publication Number | Publication Date |
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CN103594433A true CN103594433A (zh) | 2014-02-19 |
CN103594433B CN103594433B (zh) | 2016-02-10 |
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CN201310533103.XA Active CN103594433B (zh) | 2013-10-31 | 2013-10-31 | 一种制作刚柔结合板的三维封装散热结构的方法 |
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CN (1) | CN103594433B (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107548223A (zh) * | 2016-06-24 | 2018-01-05 | 苏州天脉导热科技有限公司 | 一种bga与pcb板的安装方法 |
CN107978593A (zh) * | 2017-12-26 | 2018-05-01 | 深圳铨力半导体有限公司 | 一种集成可调谐天线阵与射频模块的封装结构以及封装方法 |
CN111385448A (zh) * | 2018-12-27 | 2020-07-07 | 松下知识产权经营株式会社 | 电子装置的散热结构和散热方法 |
CN111863717A (zh) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | 一种芯片互连方法 |
CN111863719A (zh) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | 一种芯片互连方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020127779A1 (en) * | 1999-10-19 | 2002-09-12 | Ching-Huei Su | Chip scale package and manufacturing method thereof |
US20070202306A1 (en) * | 2006-02-27 | 2007-08-30 | Fujikura Ltd. | Connection configuration for rigid substrates |
US20090090541A1 (en) * | 2007-10-04 | 2009-04-09 | Phoenix Precision Technology Corporation | Stacked semiconductor device and fabricating method thereof |
CN103094256A (zh) * | 2011-11-08 | 2013-05-08 | 中国科学院微电子研究所 | 一种封装系统 |
CN103327738A (zh) * | 2012-03-22 | 2013-09-25 | 富葵精密组件(深圳)有限公司 | 软硬结合电路板及其制作方法 |
-
2013
- 2013-10-31 CN CN201310533103.XA patent/CN103594433B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020127779A1 (en) * | 1999-10-19 | 2002-09-12 | Ching-Huei Su | Chip scale package and manufacturing method thereof |
US20070202306A1 (en) * | 2006-02-27 | 2007-08-30 | Fujikura Ltd. | Connection configuration for rigid substrates |
US20090090541A1 (en) * | 2007-10-04 | 2009-04-09 | Phoenix Precision Technology Corporation | Stacked semiconductor device and fabricating method thereof |
CN103094256A (zh) * | 2011-11-08 | 2013-05-08 | 中国科学院微电子研究所 | 一种封装系统 |
CN103327738A (zh) * | 2012-03-22 | 2013-09-25 | 富葵精密组件(深圳)有限公司 | 软硬结合电路板及其制作方法 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107548223A (zh) * | 2016-06-24 | 2018-01-05 | 苏州天脉导热科技有限公司 | 一种bga与pcb板的安装方法 |
CN107978593A (zh) * | 2017-12-26 | 2018-05-01 | 深圳铨力半导体有限公司 | 一种集成可调谐天线阵与射频模块的封装结构以及封装方法 |
CN107978593B (zh) * | 2017-12-26 | 2024-02-20 | 华进半导体封装先导技术研发中心有限公司 | 一种集成可调谐天线阵与射频模块的封装结构以及封装方法 |
CN111385448A (zh) * | 2018-12-27 | 2020-07-07 | 松下知识产权经营株式会社 | 电子装置的散热结构和散热方法 |
CN111863717A (zh) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | 一种芯片互连方法 |
CN111863719A (zh) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | 一种芯片互连方法 |
CN111863717B (zh) * | 2020-07-28 | 2022-07-15 | 南通通富微电子有限公司 | 一种芯片互连方法 |
CN111863719B (zh) * | 2020-07-28 | 2022-07-19 | 南通通富微电子有限公司 | 一种芯片互连方法 |
Also Published As
Publication number | Publication date |
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CN103594433B (zh) | 2016-02-10 |
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SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20190524 Address after: 214213 China Sensor Network International Innovation Park D1, 200 Linghu Avenue, Taihu International Science Park, Wuxi New District, Jiangsu Province Patentee after: National Center for Advanced Packaging Co.,Ltd. Address before: 100083 3 north Tu Cheng West Road, Chaoyang District, Beijing Co-patentee before: National Center for Advanced Packaging Co.,Ltd. Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
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TR01 | Transfer of patent right | ||
EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20140219 Assignee: Shanghai Meadville Science & Technology Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2023980035123 Denomination of invention: A Method for Manufacturing a 3D Packaging Heat Dissipation Structure of a Rigid Flexible Composite Board Granted publication date: 20160210 License type: Common License Record date: 20230427 |
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EE01 | Entry into force of recordation of patent licensing contract |