CN103594433A - 一种制作刚柔结合板的三维封装散热结构的方法 - Google Patents

一种制作刚柔结合板的三维封装散热结构的方法 Download PDF

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CN103594433A
CN103594433A CN201310533103.XA CN201310533103A CN103594433A CN 103594433 A CN103594433 A CN 103594433A CN 201310533103 A CN201310533103 A CN 201310533103A CN 103594433 A CN103594433 A CN 103594433A
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CN103594433B (zh
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侯峰泽
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明公开了一种制作刚柔结合板的三维封装散热结构的方法,包括:制作柔性基板;将底部基板和两个刚性基板压合在柔性基板上;在两个刚性基板中挖空腔;将两个铜基分别粘接固定在两个刚性基板的背面;将底部芯片焊接到底部基板上,将两个顶部芯片分别焊到或粘到刚性基板由于挖空腔而露出的两个铜基上,并将两个顶部芯片键合到刚性基板上;弯曲柔性基板,使柔性基板两侧的两个刚性基板置于底部基板上的底部芯片上方,灌入塑封材料使之固定成型;在底部基板背面的焊盘上刷焊锡膏,钢网植BGA球,回流,形成封装体;将底部基板的背面固定于PCB板之上,在两个铜基之上安装散热器。利用本发明,增加了封装体的散热路径,能够更为有效的散出热量。

Description

一种制作刚柔结合板的三维封装散热结构的方法
技术领域
本发明涉及微电子三维系统级封装技术领域,尤其是一种制作刚柔结合板的三维封装散热结构的方法。
背景技术
其中202为下层芯片;204为上层芯片;206为柔性基板;208为柔性基板内表面;212为下层芯片引脚;214为上层芯片引脚;216为底部填充胶;222为BGA球阵列;224为单个BGA球;226为柔性基板外表面;232为下层芯片正面;234为上层芯片背面;236为贴片胶;238为PCB板。
该三维堆叠结构首先进行平面安装,将两颗芯片202和204焊接在柔性基板206的两端,并于芯片与柔性基板之间填充底部填充胶216;然后在芯片202和204朝上部分涂上导热的贴片胶236;最后将柔性基板206弯曲,使两芯片202和204上下对齐堆叠,通过导热的贴片胶236固接,两芯片202和204的电互连通过柔性基板206上的电路实现。
该三维堆叠结构的缺点是上层芯片204在散热方面存在较大的问题,上层芯片204产生的大部分热量需依次经导热的贴片胶236、下层芯片202、底部填充胶216、柔性基板206、BGA球224以及PCB 238散出,热量不容易散出,最终导致上层芯片204结温升高,影响寿命。
发明内容
(一)要解决的技术问题
有鉴于此,本发明的主要目的在于提供一种制作刚柔结合板的三维封装散热结构的方法,以更为有效的散出热量。
(二)技术方案
为达到上述目的,本发明提供了一种制作刚柔结合板的三维封装散热结构的方法,该方法包括:步骤101:制作柔性基板100;步骤102:将底部基板102和两个刚性基板101压合在柔性基板100上,其中两个刚性基板101对称分布在底部基板102的两侧;步骤103:在两个刚性基板101中挖空腔;步骤104:将两个铜基103分别粘接固定在两个刚性基板101的背面;步骤105:将底部芯片201焊接到底部基板102上,将两个顶部芯片203分别焊到或粘到刚性基板101由于挖空腔而露出的两个铜基103上,并通过键合引线302将两个顶部芯片203键合到刚性基板101上;步骤106:弯曲柔性基板100,使柔性基板100两侧的两个刚性基板101置于底部基板102上的底部芯片201上方,并灌入塑封材料600使之固定成型;然后在底部基板102背面的焊盘上刷焊锡膏,钢网植BGA球700,回流,形成封装体;步骤107:将底部基板102的背面固定于PCB板1000之上,并通过导热膏800在封装体顶部的两个铜基103之上安装散热器900,形成刚柔结合板弯折后的三维封装散热结构。
上述方案中,步骤102中所述底部基板102采用刚性基板或柔性基板。
上述方案中,步骤104中所述两个铜基103是使用导电银浆分别粘接固定在两个刚性基板101的背面,铜基103的长宽尺寸与刚性基板101的长宽尺寸相同,左右结构对称的分布在底部基板102背面的两侧。
上述方案中,步骤105中所述底部芯片201是通过倒装焊(flip-chip)的方式焊接到底部基板102上,且在底部芯片201与底部基板102之间形成芯片下凸点301并填充底部填充胶400。所述底部芯片201为小功率芯片,其功率为20~500mW。
上述方案中,步骤105中所述顶部芯片203是通过共晶焊料或导电银浆500焊到或粘到刚性基板101由于挖空腔而露出的两个铜基103上。所述顶部芯片203为大功率芯片,其功率至少为1瓦。
上述方案中,步骤106中所述塑封材料600用于保护键合引线302和支撑顶部刚性基板101。
上述方案中,步骤107中所述BGA球700是通过在底部基板102背面的焊盘上刷焊锡膏,钢网植BGA球而形成。
上述方案中,该刚柔结合板的三维封装散热结构是左右对称结构。
(三)有益效果
从上述技术方案可以看出,本发明具有以下有益效果:
1、本发明提供的制作刚柔结合板的三维封装散热结构的方法,通过使用刚性基板和柔性基板相结合,并在刚性基板上附加铜基结构,对大小功率芯片分别进行散热处理,增加了封装体的散热路径,能够更为有效的散出热量。
2、本发明提供的制作刚柔结合板的三维封装散热结构的方法,通过在刚柔结合板上进行平面工艺安装芯片,再通过弯折柔性基板实现三维堆叠,成本低,工艺简单成熟。
3、本发明提供的制作刚柔结合板的三维封装散热结构的方法,通过在上层芯片的刚性基板上,附加高热导率的铜基模块,增加了堆叠芯片的散热路径,使上层芯片的热量通过顶部铜基,迅速传导至封装体外部散出,有效散出热量。
4、本发明提供的制作刚柔结合板的三维封装散热结构的方法,,可在刚性基板上同时安装多颗小芯片,使堆叠芯片的数量增加,便于高密度芯片集成;并且产生的热量可通过铜基迅速散出封装体。
5、本发明提供的制作刚柔结合板的三维封装散热结构的方法,裸露在封装体外的铜基,可在其上方便的安装散热装置,如热沉,可对大功率芯片进行更为有效的散热。
附图说明
图1是现有技术中通过弯曲柔性基板实现芯片三维堆叠结构的示意图;
图2为本发明提供的刚柔结合板的三维封装散热结构的示意图;
图3至图8为依照本发明实施例的制作刚柔结合板的三维封装散热结构的工艺流程图;其中:
图3为柔性基板的结构示意图;
图4为刚柔结合板的结构示意图;
图5为刚柔结合板挖腔后的结构示意图;
图6为刚柔结合板粘贴在铜基上的结构示意图;
图7刚柔结合板平面封装的结构示意图;
图8刚柔结合板弯折后的三维封装的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。
图2为本发明提供的刚柔结合板的三维封装散热结构的示意图,该三维封装散热结构包括:
一个柔性基板100;
压合在柔性基板100上的一个底部基板102和两个刚性基板101,其中,两个刚性基板101对称分布在底部基板102的两侧,且两个刚性基板101中挖有空腔,底部基板102采用刚性基板和柔性基板均可,本实施例中采用的是刚性基板;
粘接固定在两个刚性基板101背面的两个铜基103;两个铜基103是使用导电银浆分别粘接固定在两个刚性基板101的背面,铜基103长宽尺寸与刚性基板101长宽尺寸相同,左右结构对称的分布在底部基板102背面的两侧;
焊接在底部基板102上的一个底部芯片201;底部芯片201一般为小功率芯片,其功率为20~500mW;
形成于底部芯片201与底部基板102之间的芯片下凸点301;
填充于底部芯片201与底部基板102之间芯片下凸点301周围的底部填充胶400;
分别焊到或粘到刚性基板101由于挖空腔而露出的两个铜基103上的两个顶部芯片203;顶部芯片203一般为大功率芯片,其功率至少为1瓦;
将两个顶部芯片203键合到刚性基板101上的键合引线302;
塑封材料600,灌入于由于弯曲柔性基板100使柔性基板100两侧的两个刚性基板101置于底部基板102上的底部芯片201上方而形成的空间,用于保护键合引线302和支撑顶部刚性基板101;
形成于底部基板102背面的BGA球700,BGA球700是通过在底部基板102背面的焊盘上刷焊锡膏,钢网植BGA球而形成;
通过BGA球700来固定底部基板102的PCB板1000,底部基板102的背面通过BGA球700固定于PCB板1000之上;以及
通过导热膏800安装于顶部的两个铜基103之上的散热器900。
本发明提供的刚柔结合板的三维封装散热结构,通过对散热器900实施风冷等方式,将铜基103导出的热量更迅速有效的散出。该刚柔结合板的三维封装散热结构是左右对称结构。
基于图2所示的刚柔结合板的三维封装散热结构,图3至图8为依照本发明实施例的制作刚柔结合板的三维封装散热结构的工艺流程图,具体包括以下步骤:
步骤101:制作柔性基板100,如图3所示;
步骤102:将底部基板102和两个刚性基板101压合在柔性基板100上,其中两个刚性基板101对称分布在底部基板102的两侧,如图4所示,底部基板102采用刚性基板和柔性基板均可,本实施例中采用的是刚性基板;
步骤103:在两个刚性基板101中挖空腔,如图5所示;
步骤104:使用导电银浆将两个铜基103分别粘接固定在两个刚性基板101的背面,铜基103长宽尺寸与刚性基板101长宽尺寸相同,左右结构对称的分布在底部基板102背面的两侧,如图6所示;
步骤105:如图7所示,通过倒装焊(flip-chip)的方式将底部芯片201焊接到底部基板102上,在底部芯片201与底部基板102之间形成芯片下凸点301并填充底部填充胶400;然后,通过共晶焊料或导电银浆500将两个顶部芯片203分别焊到或粘到刚性基板101由于挖空腔而露出的两个铜基103上,然后通过键合引线302将两个顶部芯片203键合到刚性基板101上。
步骤106:如图8所示,通过弯曲柔性基板100,使柔性基板100两侧的两个刚性基板101置于底部基板102上的底部芯片201上方,并通过灌入塑封材料600使之固定成型,塑封材料600起到保护键合引线302和支撑顶部刚性基板101的作用;然后在底部基板102背面的焊盘上刷焊锡膏,钢网植BGA球700,回流,形成封装体。
步骤107:将底部基板102的背面通过BGA球700固定于PCB板1000之上,并通过导热膏800在封装体顶部的两个铜基103之上安装散热器900,形成刚柔结合板弯折后的三维封装散热结构。最终形成的刚柔结合板弯折后的三维封装散热结构如图2所示,通过对散热器900实施风冷等方式,将铜基103导出的热量更迅速有效的散出。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (10)

1.一种制作刚柔结合板的三维封装散热结构的方法,其特征在于,该方法包括:
步骤101:制作柔性基板(100);
步骤102:将底部基板(102)和两个刚性基板(101)压合在柔性基板(100)上,其中两个刚性基板(101)对称分布在底部基板(102)的两侧;
步骤103:在两个刚性基板(101)中挖空腔;
步骤104:将两个铜基(103)分别粘接固定在两个刚性基板(101)的背面;
步骤105:将底部芯片(201)焊接到底部基板(102)上,将两个顶部芯片(203)分别焊到或粘到刚性基板(101)由于挖空腔而露出的两个铜基(103)上,并通过键合引线(302)将两个顶部芯片(203)键合到刚性基板(101)上;
步骤106:弯曲柔性基板(100),使柔性基板(100)两侧的两个刚性基板(101)置于底部基板(102)上的底部芯片(201)上方,并灌入塑封材料(600)使之固定成型;然后在底部基板(102)背面的焊盘上刷焊锡膏,钢网植BGA球(700),回流,形成封装体;
步骤107:将底部基板(102)的背面固定于PCB板1000之上,并通过导热膏(800)在封装体顶部的两个铜基(103)之上安装散热器(900),形成刚柔结合板弯折后的三维封装散热结构。
2.根据权利要求1所述的制作刚柔结合板的三维封装散热结构的方法,其特征在于,步骤102中所述底部基板(102)采用刚性基板或柔性基板。
3.根据权利要求1所述的制作刚柔结合板的三维封装散热结构的方法,其特征在于,步骤104中所述两个铜基(103)是使用导电银浆分别粘接固定在两个刚性基板(101)的背面,铜基(103)的长宽尺寸与刚性基板(101)的长宽尺寸相同,左右结构对称的分布在底部基板(102)背面的两侧。
4.根据权利要求1所述的制作刚柔结合板的三维封装散热结构的方法,其特征在于,步骤105中所述底部芯片(201)是通过倒装焊(flip-chip)的方式焊接到底部基板(102)上,且在底部芯片(201)与底部基板(102)之间形成芯片下凸点(301)并填充底部填充胶(400)。
5.根据权利要求4所述的制作刚柔结合板的三维封装散热结构的方法,其特征在于,所述底部芯片(201)为小功率芯片,其功率为20~500mW。
6.根据权利要求1所述的制作刚柔结合板的三维封装散热结构的方法,其特征在于,步骤105中所述顶部芯片(203)是通过共晶焊料或导电银浆(500)焊到或粘到刚性基板(101)由于挖空腔而露出的两个铜基(103)上。
7.根据权利要求6所述的制作刚柔结合板的三维封装散热结构的方法,其特征在于,所述顶部芯片(203)为大功率芯片,其功率至少为1瓦。
8.根据权利要求1所述的制作刚柔结合板的三维封装散热结构的方法,其特征在于,步骤106中所述塑封材料(600)用于保护键合引线(302)和支撑顶部刚性基板(101)。
9.根据权利要求1所述的制作刚柔结合板的三维封装散热结构的方法,其特征在于,步骤107中所述BGA球(700)是通过在底部基板(102)背面的焊盘上刷焊锡膏,钢网植BGA球而形成。
10.根据权利要求1所述的制作刚柔结合板的三维封装散热结构的方法,其特征在于,该刚柔结合板的三维封装散热结构是左右对称结构。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107548223A (zh) * 2016-06-24 2018-01-05 苏州天脉导热科技有限公司 一种bga与pcb板的安装方法
CN107978593A (zh) * 2017-12-26 2018-05-01 深圳铨力半导体有限公司 一种集成可调谐天线阵与射频模块的封装结构以及封装方法
CN111385448A (zh) * 2018-12-27 2020-07-07 松下知识产权经营株式会社 电子装置的散热结构和散热方法
CN111863719A (zh) * 2020-07-28 2020-10-30 南通通富微电子有限公司 一种芯片互连方法
CN111863717A (zh) * 2020-07-28 2020-10-30 南通通富微电子有限公司 一种芯片互连方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020127779A1 (en) * 1999-10-19 2002-09-12 Ching-Huei Su Chip scale package and manufacturing method thereof
US20070202306A1 (en) * 2006-02-27 2007-08-30 Fujikura Ltd. Connection configuration for rigid substrates
US20090090541A1 (en) * 2007-10-04 2009-04-09 Phoenix Precision Technology Corporation Stacked semiconductor device and fabricating method thereof
CN103094256A (zh) * 2011-11-08 2013-05-08 中国科学院微电子研究所 一种封装系统
CN103327738A (zh) * 2012-03-22 2013-09-25 富葵精密组件(深圳)有限公司 软硬结合电路板及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020127779A1 (en) * 1999-10-19 2002-09-12 Ching-Huei Su Chip scale package and manufacturing method thereof
US20070202306A1 (en) * 2006-02-27 2007-08-30 Fujikura Ltd. Connection configuration for rigid substrates
US20090090541A1 (en) * 2007-10-04 2009-04-09 Phoenix Precision Technology Corporation Stacked semiconductor device and fabricating method thereof
CN103094256A (zh) * 2011-11-08 2013-05-08 中国科学院微电子研究所 一种封装系统
CN103327738A (zh) * 2012-03-22 2013-09-25 富葵精密组件(深圳)有限公司 软硬结合电路板及其制作方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107548223A (zh) * 2016-06-24 2018-01-05 苏州天脉导热科技有限公司 一种bga与pcb板的安装方法
CN107978593A (zh) * 2017-12-26 2018-05-01 深圳铨力半导体有限公司 一种集成可调谐天线阵与射频模块的封装结构以及封装方法
CN107978593B (zh) * 2017-12-26 2024-02-20 华进半导体封装先导技术研发中心有限公司 一种集成可调谐天线阵与射频模块的封装结构以及封装方法
CN111385448A (zh) * 2018-12-27 2020-07-07 松下知识产权经营株式会社 电子装置的散热结构和散热方法
CN111863719A (zh) * 2020-07-28 2020-10-30 南通通富微电子有限公司 一种芯片互连方法
CN111863717A (zh) * 2020-07-28 2020-10-30 南通通富微电子有限公司 一种芯片互连方法
CN111863717B (zh) * 2020-07-28 2022-07-15 南通通富微电子有限公司 一种芯片互连方法
CN111863719B (zh) * 2020-07-28 2022-07-19 南通通富微电子有限公司 一种芯片互连方法

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