CN103579231A

CN103579231A - Semiconductor power device

Info

Publication number: CN103579231A
Application number: CN201210262785.0A
Authority: CN
Inventors: 黄勤
Original assignee: VERSINE SEMICONDUCTOR Co Ltd
Current assignee: VERSINE SEMICONDUCTOR Co Ltd
Priority date: 2012-07-26
Filing date: 2012-07-26
Publication date: 2014-02-12

Abstract

The invention provides a semiconductor power device. A traditional IGBT and a traditional VDMOS are ingeniously combined to form the novel semiconductor power device provided with a common part and consisting of a basic longitudinal IGBT and a basic transverse DMOS. The doping concentration of a re-doped second electric conduction type region is adjusted or a service life controlling method is adopted to decrease first forward breakover current produced by the basic longitudinal IGBT and meanwhile increase second forward breakover current produced by the basic transverse VDMOS, and even the first forward breakover current is smaller than the second forward breakover current. Compared with an IGBT and a VDMOS in the prior art, the switching speed of the device is improved while the reduction of the breakover resistance loss and the breakover power loss of the device is ensured. Therefore, the semiconductor power device has wide application prospect and can be applied to the fields of power supplies, solar inverters, motor driving and other fields needing high-voltage and high-frequency switching.

Description

Semiconductor power device

Technical field

The invention belongs to field of semiconductor devices, relate to a kind of semiconductor power device.

Background technology

Igbt (Insulated Gate Bipolar Transistor, IGBT) be by bipolar transistor (Bipolar Transistor) and mos field effect transistor (Metal-Oxide-Semiconductor Field Effect Transisitor, MOSFET) the compound full-control type voltage driven type power semiconductor forming, and IGBT is bipolar device, two kinds of charge carriers (electronics and hole) conduct electricity simultaneously.IGBT is generally divided into punch (Punch Through, PT), non-punch (Non-Punch Through, NPT), electric field cut-off (electric field termination) type (Field Stop, FS), wherein, collector electrode 1 ', emitter 2 ' and grid 3 ' as depicted in figs. 1 and 2, and Fig. 1 structural representation that is NPT-IGBT, Fig. 2 is the structural representation of PT-IGBT or FS-IGBT.The main distinction of PT-IGBT, FS-IGBT and NPT-IGBT is, NPT-IGBT does not adopt the designed N+ resilient coating of corresponding given blocking voltage and needs more Hou N-district (drift region).IGBT has the numerous characteristics of MOSFET, and as easy driving, safety operation area is wide, and peak current is large, sturdy and durable etc.; Simultaneously, IGBT has extraordinary on state characteristic, this is due to few son (hole) ShiN-district (drift region) carrier concentration that substrate P+ injects be significantly improved (refer to 1 and Fig. 2), generation conducts mudulation effect, the injection of this few son (hole) greatly reduces the equivalent resistance of LiaoN-district (drift region), thereby reduces the conduction voltage drop in LiaoN-district.But IGBT inside does not exist reverse-conducting diode, during use, need external recovery diode; Meanwhile, the switching speed of IGBT (comprising opening speed and turn-off speed) is generally significantly less than MOSFET.

Vertical double-diffusion metal-oxide-semiconductor field effect transistor (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor, VDMOSFET) be how sub-device, and be voltage-controlled device, wherein, source electrode 4 ' ', drain 5 ' ', grid 3 ' ' and raceway groove 6 ' ' as shown in Figure 3.Under the control of suitable grid voltage, semiconductor surface transoid, forms conducting channel, then between drain electrode and source electrode, flow through appropriate electric current, and electric current perpendicular flow.VDMOS is mainly used in electric machine speed regulation, inverter, uninterrupted power supply, electronic switch, high-fidelity music center, car electrics and electric ballast etc., have and approach infinitely-great static input impedance characteristic, the distinguishing features such as very fast switching speed (comprising opening speed and turn-off speed), but its shortcoming is not have electricity to lead modulation, under certain puncture voltage designing requirement, normal state conducting resistance and on-state voltage drop are larger than IGBT, so conducting power loss is large, are unfavorable for large electric current application.

At present, the improvement of semiconductor power device characteristic is mainly when its switching speed (comprising opening speed and turn-off speed) is improved, to reduce dependent loss, and the switching frequency of device also improves thereupon.Therefore, need a kind of semiconductor power device badly, both there is very fast switching speed (comprising opening speed and turn-off speed), there is again lower conducting resistance and conducting power loss simultaneously.

Summary of the invention

The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of semiconductor power device, for solving semiconductor power device of the prior art, can not take into account very fast switching speed (comprising opening speed and turn-off speed) and lower conducting resistance and the problem of conducting power loss, solve the problem that IGBT of the prior art needs external reverse-conducting diode simultaneously.

For achieving the above object and other relevant objects, the invention provides a kind of semiconductor power device, described device at least comprises:

Collector electrode;

Heavy doping the second conductivity regions, is formed on described collector electrode;

Drift region, is light dope the first conduction type, is formed in described heavy doping the second conductivity regions;

Tagma, is the second conduction type, is formed at a side at top, described drift region;

Source region, is heavy doping the first conduction type, is formed at top, described tagma, and the surface, lateral body district outside described source region is formed with raceway groove;

Gate region, is formed on described raceway groove and drift region, and contacts with tagma with described source region;

Drain region, is heavy doping the first conduction type, is formed at top, described drift region and with respect to the opposite side in described tagma;

Isolation structure, is covered in the surface of described gate region and drift region, and is respectively equipped with the through hole that exposes part described source region and tagma and expose the described drain region of part;

Source/emitter, is covered in the isolation structure on described gate region surface, and contacts with tagma by the through hole of the described isolation structure source region described with part, for described source region, tagma, realizes and being electrically connected to;

Drain electrode, is formed on described drain region, and the described drain region of through hole and part by described isolation structure contacts, and described drain electrode links together by lead-in wire with collector electrode, the drain/collector of formation realization electrical connection;

Terminal structure, is formed at the top of described drift region, and is formed between described tagma and drain region, to reduce surface field, the position of electrical breakdown is shifted under described tagma by surface, improves the barotolerance of device.

Alternatively, between described drift region and heavy doping the second conductivity regions, be also provided with buffering area, described buffering area is formed in heavy doping the second conductivity regions, and described drift region is formed on buffering area, wherein, described buffering area is heavy doping the first conduction type.

Alternatively, described buffering area doping content is lower than source region doping content and drain region doping content.

Alternatively, described terminal structure at least comprises knot termination extension terminal structure, a limiting protecting ring terminal structure, field plate terminal structure, field plate and a limiting protecting ring composite terminal structure or field plate and knot termination extension composite terminal structure.

Alternatively, described gate region comprises gate dielectric layer and is formed at the grid on described gate dielectric layer.

Alternatively, on described grid, be also provided with insulating barrier.

Alternatively, described semiconductor power device forward conduction, in described device, form the forward conduction electric current that at least comprises the first forward conduction electric current and the second forward conduction electric current, wherein, the first conduction type is N-type, when the second conduction type is P type, described the first forward conduction electric current flows to raceway groove by described heavy doping the second conductivity regions, and described the second forward conduction electric current flows to raceway groove by described drain region; The first conduction type is P type, and when the second conduction type is N-type tagma, described the first forward conduction electric current flows to heavy doping the second conductivity regions by described raceway groove, and described the second forward conduction electric current flows to drain region by described raceway groove.

Alternatively, the first described forward conduction electric current is less than the second forward conduction electric current, to guarantee that the conducting resistance of device and conducting power loss improve the switching speed of device when reducing.

Alternatively, described semiconductor power device reverse-conducting, described tagma, ,Ji drain region, drift region form reverse-conducting diode, wherein, the first conduction type is that N-type, the second conduction type form the reverse-conduction current that is flowed to drain region by described tagma while being P type, and the first conduction type is that P type, the second conduction type form the reverse-conduction current that is flowed to tagma by described drain region while being N-type.

As mentioned above, semiconductor power device of the present invention, there is following beneficial effect: by dexterously in conjunction with conventional I GBT and power MOSFET (VDMOS), formation has the novel semi-conductor power device of the present invention being comprised of basic longitudinal IGBT and basic lateral DMOS of common sparing, wherein, described common sparing is drift region, tagma, source region, gate region, isolation structure, source/emitter, further, adjust the doping content of heavy doping the second conductivity regions of the present invention or the method for employing life-span control, to reduce the size of the first forward conduction electric current of basic longitudinal IGBT generation, increased the size of the second forward conduction electric current of basic lateral DMOS generation simultaneously, and make described the first forward conduction electric current be less than the second forward conduction electric current, make the present invention compared to IGBT of the prior art and VDMOS, in the switching speed (comprising opening speed and turn-off speed) that guarantees to improve when the conducting resistance of device and conducting power loss reduce device, combine the advantage that conventional I GBT and VDMOS have, make the bright semiconductor power device of this law there is more wide application prospect, can be used in power supply, solar inverter, motor driving etc. needs the application of high voltagehigh frequency switch.

Accompanying drawing explanation

Fig. 1 is shown as the structural representation of NPT-IGBT in prior art.

Fig. 2 is shown as the structural representation of PT-IGBT in prior art or FS-IGBT.

Fig. 3 is shown as the structural representation of VDMOS in prior art.

Fig. 4 is shown as semiconductor power device of the present invention structural representation in an embodiment.

Fig. 5 is shown as the schematic diagram of semiconductor power device the first forward conduction electric current of the present invention and the second forward conduction electric current.

Fig. 6 is shown as the schematic diagram of semiconductor power device reverse-conduction current of the present invention.

Element numbers explanation

101,5 ' ' drain electrode

102,1 ' collector electrode

20 drain regions

30 drift regions

40 tagmas

50 source regions

60 gate region

601 gate dielectric layers

602,3 ', 3 ' ' grid

603 insulating barriers

70 heavy doping the second conductivity regions

80 isolation structures

90 source/emitter

110 terminal structures

120 buffering areas

130,6 ' ' raceway groove

2 ' emitter

4 ' ' source electrode

Embodiment

Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.

Refer to Fig. 4 to Fig. 6.It should be noted that, the diagram providing in following specific embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.

As shown in Figure 4, the invention provides a kind of semiconductor power device, described device at least comprises:

drain

101,40, source region, 30, tagma, 20, drift region, drain region 50, gate region 60, heavy doping the second conductivity regions 70, isolation structure 80, source/emitter 90, collector electrode 102, terminal structure 110.

It is pointed out that in the present embodiment, the first conduction type is N-type, and the second conduction type is P type, but is not limited to this, and in other embodiments, described the first conduction type can be P type, and described the second conduction type is N-type; The material of 40, source region, 30, tagma, 20, drift region, described drain region 50, heavy doping the second conductivity regions 70, terminal structure 110 is silicon materials, but is not limited to this, and in other embodiments, the material in described respectively this region also can be carborundum or gallium nitride.

Described collector electrode 102 is formed at described heavy doping the second conductivity regions 70 times, for being electrically connected to, uses, and in the present embodiment, described collector electrode 102 is aluminium, and in other embodiments, the material of described drain electrode 101 is polysilicon, copper or aluminium copper.

Described heavy doping the second conductivity regions 70 is formed on described collector electrode 102, and particularly, in the present embodiment, described heavy doping the second conductivity regions 70 is heavy doping P Xing Gui ，JiP+Xing district 70.

Described drift region 30 is light dope the first conduction type, is formed in described heavy doping the second conductivity regions 70, and particularly, in the present embodiment, described drift region 30 is light dope N-type silicon, i.e. N-type drift region 30.

It should be noted that, in order to prevent that depletion layer arrives heavy doping the second conductivity regions 70 when the blocking voltage, and for controlling the ability of described heavy doping the second conductivity regions 70 injected minority carriers, control the injection efficiency of described heavy doping the second conductivity regions 70, between described drift region 30 and heavy doping the second conductivity regions 70, be also provided with buffering area 120, described resilient coating 120 is heavy doping the first conduction type, meanwhile, the heavy dopant concentration of described buffering area 120 is higher than the light dope concentration of drift region 30.Particularly, in the present embodiment, the first conduction type is N-type, the second conduction type is P type, described buffering area 120 is N+ type, and 120Wei silicon materials district, described N+ type buffering area, but is not limited to this, in other embodiments, the material of described N+ type buffering area 120 also can be carborundum or gallium nitride; Described N+ type buffering area 120 is formed at heavy doping the second conductivity regions 70(P+ type) on, and described N-type drift region 30 is formed on N+ type buffering area 120, described N+ type buffering area 120 is formed at described N-type drift region 30 and heavy doping the second conductivity regions 70(P+ type) between.

Described tagma 40 is the second conduction type, is formed at a side at 30 tops, described drift region, and particularly, in the present embodiment, described tagma 40 is P type silicon.

Described source region 50 is heavy doping the first conduction type, be formed at 40 tops, described tagma, and 40 surfaces, tagma of the side outside described source region 50 are formed with raceway groove 130, particularly, in the present embodiment, the described source region 50 doped N-type silicon of attaching most importance to, i.e. N+ type source region 50, and the doping content in described source region 50 and the doping content in drain region 20 are at the same order of magnitude; Described tagma 40 is formed between 50Yu drift region, source region 30.

It is pointed out that the heavy dopant concentration of described buffering area 120 is generally lower than the heavy dopant concentration in source region 50 heavy dopant concentration and drain region 20, but, the heavy dopant concentration of described buffering area 120 is higher than the light dope concentration of drift region 30.

Described gate region 60 is formed on described raceway groove 130 and drift region 30, and contacts with described 50He tagma, source region 40.It should be noted that, described gate region 60 comprises gate dielectric layer 601 and is formed at the grid 602 on described gate dielectric layer 601; Further, on described grid 602, be also provided with insulating barrier 603, wherein, described gate dielectric layer 601 is silicon nitride, silicon oxynitride or silica, described grid 602 is polysilicon, aluminium, copper or aluminium copper, and described insulating barrier 603 is silicon nitride, silicon oxynitride or silica.In the present embodiment, described gate region 60 comprises gate dielectric layer 601, grid 602 and insulating barrier 603, wherein, described gate dielectric layer 601 is silica, and insulating barrier 603 is silicon nitride, and described grid 602 is heavy doping the first conduction type (N+ type) polysilicon, but be not limited to this, in other embodiments, described gate region 60 comprises gate dielectric layer and grid, and gate dielectric layer 131 also can be silicon nitride.

Described drain region 20 is heavy doping the first conduction type, is formed at 30 tops, described drift region and with respect to the opposite side in described tagma 40, particularly, in the present embodiment, described drain region 20 attach most importance to doped N-type silicon, i.e. N+ type drain region 20.

Described isolation structure 80 is covered in the surface of described gate region 60 and drift region 30, and be respectively equipped with and expose the described source region 50 of part and with respect to the opposite side tagma 40 of described raceway groove 130, and expose the described drain region of part 20 through holes, thereby guarantee between described gate region 60 and described source/emitter 90, described drain electrode 101 and the device surface between source/emitter 90 can bear high voltage, wherein, described isolation structure 80 is single layer structure or laminated construction, described single layer structure wherein or the material of the every one deck in described laminated construction are silica, silicon nitride, silicon oxynitride, phosphorosilicate glass, or semi-insulating polysilicon (Semi-insulating polycrystalline-silicon, SIPOS) any one in, in the present embodiment, described isolation structure 80 is mono-layer oxidized silicon structure.

Described source/emitter 90 is covered in the isolation structure 80 on described gate region 60 surfaces, and contact by the through hole of the described isolation structure 80 50He tagma, source region 40 described with part, for described 50, tagma, source region 40, realize and being electrically connected to, particularly, in the present embodiment, described source/emitter 90 is aluminium, and in other embodiments, the material of described source/emitter 90 also can be polysilicon, copper or aluminium copper.

Described drain electrode 101 is formed on described drain region 20, through hole by described isolation structure 80 contacts with the described drain region 20 of part, and described drain electrode 101 links together by lead-in wire with collector electrode 102, form and realize the drain/collector being electrically connected to, in the present embodiment, described drain electrode 101 is aluminium, and in other embodiments, the material of described drain electrode 101 is polysilicon, copper or aluminium copper.

Described terminal structure 110 is formed at the top of described drift region 30, and is formed between 40Yu drain region, described tagma 20, to reduce surface field, the position of electrical breakdown is shifted under described tagma by surface, improves the high pressure resistant property of device.Wherein, described terminal structure 110 is in order to make the PN junction being produced by low pressure IC technique can bear high pressure design, and described terminal structure 110 is the necessary and basic fundamentals of producing high tension apparatus.Described terminal structure at least comprises adopting ties termination extension (Junction Termination Extension; JTE) the knot termination extension terminal structure of technology, an employing limiting protecting ring (Floating Ring; FR) the field limiting protecting ring terminal structure of technology, employing field plate (Field Plate; FP) the field plate terminal structure of technology, field plate (FP) and limiting protecting ring (FR) composite terminal structure or field plate (FP) and knot termination extension (JTE) composite terminal structure, and respectively this terminal structure technique simple and with IC process compatible.Particularly; in the present embodiment, adopt a limiting protecting ring terminal structure 110; as shown in Figure 4; its midfield limiting protecting ring terminal structure 110 is illustrated with three the second conduction types (P type) district; and shown in the second conduction type (P type) district in limiting protecting ring number and between distance according to concrete puncture voltage, can be optimized design; be not limited to the second conduction type shown in Fig. 4 (P) district number and between distance, at this, do not repeat one by one.

For the ease of understanding the characteristic of the semiconductor power device described in embodiment, below introduce its relevant operation principle:

Semiconductor power device in the embodiment of the present invention is the New Type Power Devices of comprehensive IGBT and MOSFET advantage, wherein, gate region 60, source/emitter 90, source region 50, tagma 40, drift region 30, heavy doping the second conductivity regions 70, resilient coating 120, collector electrode 102, isolation structure 80 forms basic longitudinal IGBT, drain electrode 101, drain region 20, drift region 30, tagma 40, source region 50, gate region 60, source/emitter 90, isolation structure 80 has formed basic lateral DMOS, and described basic longitudinal IGBT and basic lateral DMOS have shared described drift region 30, tagma 40, source region 50, gate region 60, isolation structure 80, source/emitter 90.

The first conduction type in the present embodiment is N-type, and the second conduction type is P type, and channel type is N raceway groove.When the threshold voltage of described grid 602 voltages higher than described semiconductor power device, and when 101/ collector electrode 102 voltages that drain are greater than the voltage of source/emitter 90, the semiconductor power device forward conduction in the embodiment of the present invention, form the forward conduction electric current that at least comprises the first forward conduction electric current and the second forward conduction electric current, as shown in Figure 5.Wherein, described the first forward conduction electric current is the forward conduction electric current of basic longitudinal IGBT, is longitudinal current, flows to raceway groove, by described heavy doping the second conductivity regions 70 as shown in the dotted line of the attached arrow in Fig. 5; Described the second forward conduction electric current is the forward conduction electric current of basic lateral DMOS, is transverse current, flows to raceway groove, by described drain region 20 as shown in the solid line of the attached arrow in Fig. 5.

It is to be noted, by adjusting the doping content of described heavy doping the second conductivity regions 70 or the method for employing life-span control, the CURRENT DISTRIBUTION size that can regulate described the first forward conduction electric current and the second forward conduction electric current, diminishes the first described forward conduction electric current and is even less than the second forward conduction electric current.Wherein, owing to being also provided with buffering area 120 in the present embodiment, when adjusting the doping content of described heavy doping the second conductivity regions 70, the doping content of described buffering area 120 is adjusted, also can be reached the effect that regulates forward conduction CURRENT DISTRIBUTION; The method that the described life-span is controlled at least comprises electron irradiation.

Now, described the second forward conduction electric current is taken electric current as the leading factor, and to guarantee that the conducting resistance of device and conducting power loss improve the switching speed (comprising opening speed and turn-off speed) of device when reducing, reason is:

On the one hand, in the present embodiment, heavy doping the second conductivity regions (P+ type) 70 of basic longitudinal IGBT is injected into described N-type drift region 30 by hole, the injection in this hole (few son) has greatly reduced the equivalent resistance of described N-type drift region 30, greatly increased conductivity, conductivity is modulated, the little electric current (the first forward conduction electric current) that is basic longitudinal IGBT is led modulation for electricity, the conducting resistance of the N-type drift region 30 of power device of the present invention is reduced, therefore, the conductive capability of power device of the present invention is improved, reduced conduction voltage drop, reduced conducting power loss,

On the other hand, because described the second forward conduction electric current (the forward conduction electric current of basic lateral DMOS) is taken electric current as the leading factor, it is much larger than described the first forward conduction electric current (the forward conduction electric current of basic longitudinal IGBT), therefore, for the switching speed impact of (comprising opening speed and turn-off speed), the impact that the second forward conduction electric current produces much larger than the first forward conduction electric current, in other words, the switching speed of semiconductor power device of the present invention depends primarily on (comprising opening speed and turn-off speed) impact of the second forward conduction electric current in forward conduction electric current, the the first forward conduction electric current producing compared with basic longitudinal IGBT of slow switching speed is little on the impact of semiconductor power device switching speed of the present invention, further, owing to producing the basic lateral DMOS of the second forward conduction electric current, be many sons (electronics) conductions, thereby its switching speed (comprising opening speed and turn-off speed) is very fast, therefore, the switching speed of semiconductor power device of the present invention (comprising opening speed and turn-off speed) is improved significantly compared to conventional I GBT, the device of optimal design of the present invention can arrive 100 kHz more than, device of the present invention can be worked under the switching frequency at high 10 times than conventional I GBT.

The first conduction type in the present embodiment is N-type, and the second conduction type is P type, and channel type is N raceway groove.When described drain electrode 101/ collector electrode 102 voltages are less than the voltage of source/emitter 90, the semiconductor power device reverse-conducting in the embodiment of the present invention, as shown in Figure 6, the reverse-conducting diode that described P type tagma 40, N-type drift region 30 and N+ type drain region 20 form, formation is flowed to the reverse-conduction current in N+ type drain region 20 by described P type tagma 40, solve the problem that IGBT of the prior art needs external reverse-conducting diode.

It is to be noted, for the semiconductor power device in other embodiment, the first conduction type is P type, when the second conduction type is N-type, channel type is P raceway groove, the condition of described semiconductor power device forward conduction and reverse-conducting and the flow direction of forward conduction electric current and reverse-conducting are different from the situation of the present embodiment, but size of current is not affected by it, specific as follows;

When the threshold voltage of described grid voltage lower than described semiconductor power device, and when drain/collector voltage is less than the voltage of source/emitter, described semiconductor power device forward conduction, and the first forward conduction electric current flows to described heavy doping the second conductivity regions (N+) (not shown) by raceway groove, the second forward conduction electric current flows to described drain region (P+) (not shown) by raceway groove;

When drain/collector voltage is greater than the voltage of source/emitter, described semiconductor power device reverse-conducting, the reverse-conducting diode that described N-type tagma, P-type drift region and P+ type drain region form, formation is flowed to the reverse-conduction current (not shown) in N-type tagma by described P+ type drain region, solve the problem that IGBT of the prior art needs external reverse-conducting diode.

In sum, semiconductor power device of the present invention, in conjunction with the advantage of conventional I GBT and power MOSFET (VDMOS), forms the novel semi-conductor power device being comprised of basic longitudinal IGBT and basic lateral DMOS with common sparing by dexterously, adjust the doping content of heavy doping the second conductivity regions of the present invention or the method for employing life-span control, with the first forward conduction electric current that regulates basic longitudinal IGBT to produce, be less than the electric current of the second forward conduction electric current of basic lateral DMOS generation, make the present invention compared to IGBT of the prior art and VDMOS, in the switching speed (comprising opening speed and turn-off speed) that guarantees to improve when the conducting resistance of device and conducting power loss reduce device, combine the advantage that conventional I GBT and VDMOS have, make the bright semiconductor power device of this law there is more wide application prospect, can be used on power supply, solar inverter, motor driving etc. needs the application of high voltagehigh frequency switch.So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.

Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.

Claims

1. a semiconductor power device, is characterized in that, described device at least comprises:

Collector electrode;

Terminal structure, is formed at the top of described drift region, and is formed between described tagma and drain region, to reduce surface field, the position of electrical breakdown is shifted under described tagma by surface, improves the high pressure resistant property of device.

2. semiconductor power device according to claim 1, it is characterized in that: between described drift region and heavy doping the second conductivity regions, be also provided with buffering area, described buffering area is formed in heavy doping the second conductivity regions, and described drift region is formed on buffering area, wherein, described buffering area is heavy doping the first conduction type.

3. semiconductor power device according to claim 2, is characterized in that: described buffering area doping content is lower than source region doping content and drain region doping content.

4. semiconductor power device according to claim 1, is characterized in that: described terminal structure at least comprises knot termination extension terminal structure, a limiting protecting ring terminal structure, field plate terminal structure, field plate and a limiting protecting ring composite terminal structure or field plate and knot termination extension composite terminal structure.

5. semiconductor power device according to claim 1, is characterized in that: described gate region comprises gate dielectric layer and is formed at the grid on described gate dielectric layer.

6. semiconductor power device according to claim 5, is characterized in that: on described grid, be also provided with insulating barrier.

7. semiconductor power device according to claim 1, it is characterized in that: described semiconductor power device forward conduction, in described device, form the forward conduction electric current that at least comprises the first forward conduction electric current and the second forward conduction electric current, wherein, the first conduction type is N-type, when the second conduction type is P type, described the first forward conduction electric current flows to raceway groove by described heavy doping the second conductivity regions, and described the second forward conduction electric current flows to raceway groove by described drain region; The first conduction type is P type, and when the second conduction type is N-type tagma, described the first forward conduction electric current flows to heavy doping the second conductivity regions by described raceway groove, and described the second forward conduction electric current flows to drain region by described raceway groove.

8. semiconductor power device according to claim 7, is characterized in that: the first described forward conduction electric current is less than the second forward conduction electric current, to guarantee that the conducting resistance of device and conducting power loss improve the switching speed of device when reducing.

9. semiconductor power device according to claim 1, it is characterized in that: described semiconductor power device reverse-conducting, described tagma, ,Ji drain region, drift region form reverse-conducting diode, wherein, the first conduction type is that N-type, the second conduction type form the reverse-conduction current that is flowed to drain region by described tagma while being P type, and the first conduction type is that P type, the second conduction type form the reverse-conduction current that is flowed to tagma by described drain region while being N-type.