CN103579230A - Semiconductor power device - Google Patents
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- CN103579230A CN103579230A CN201210262720.6A CN201210262720A CN103579230A CN 103579230 A CN103579230 A CN 103579230A CN 201210262720 A CN201210262720 A CN 201210262720A CN 103579230 A CN103579230 A CN 103579230A
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Abstract
The invention provides a semiconductor power device. A traditional IGBT and a traditional VDMOS are ingeniously combined to form the novel semiconductor power device provided with a common part and consisting of a basic transverse IGBT and a basic VDMOS. The doping concentration of a re-doped second electric conduction type region is adjusted or a service life controlling method is adopted to decrease first forward breakover current produced by the basic transverse IGBT and meanwhile increase second forward breakover current produced by the basic VDMOS, and the first forward breakover current is smaller than the second forward breakover current. Compared with the traditional IGBT and the traditional VDMOS, the switching speed of the device is improved while the reduction of the breakover resistance loss and the breakover power loss of the device is ensured. By improving a structure of a drifting region, a forward breakover negative resistance region is eliminated, and the performance of the semiconductor power device is improved. The semiconductor power device is applied to the fields of power supplies, solar inverters, motor driving and other fields needing high-voltage and high-frequency switching.
Description
Technical field
The invention belongs to field of semiconductor devices, relate to a kind of semiconductor power device.
Background technology
Igbt (Insulated Gate Bipolar Transistor, IGBT) be by bipolar transistor (Bipolar Transistor) and mos field effect transistor (Metal-Oxide-Semiconductor Field Effect Transisitor, MOSFET) the compound full-control type voltage driven type power semiconductor forming, and IGBT is bipolar device, two kinds of charge carriers (electronics and hole) conduct electricity simultaneously.IGBT is generally divided into punch (Punch Through, PT), non-punch (Non-Punch Through, NPT), electric field cut-off (electric field termination) type (Field Stop, FS), wherein, collector electrode 1 ', emitter 2 ' and grid 3 ' as depicted in figs. 1 and 2, and Fig. 1 structural representation that is NPT-IGBT, Fig. 2 is the structural representation of PT-IGBT or FS-IGBT.The main distinction of PT-IGBT, FS-IGBT and NPT-IGBT is, NPT-IGBT does not adopt the designed N+ resilient coating of corresponding given blocking voltage and needs more Hou N-district (drift region).IGBT has the numerous characteristics of MOSFET, and as easy driving, safety operation area is wide, and peak current is large, sturdy and durable etc.; Simultaneously, IGBT has extraordinary on state characteristic, this is due to few son (hole) ShiN-district (drift region) carrier concentration that substrate P+ injects be significantly improved (refer to 1 and Fig. 2), generation conducts mudulation effect, the injection of this few son (hole) greatly reduces the equivalent resistance of LiaoN-district (drift region), thereby reduces the conduction voltage drop in LiaoN-district.But IGBT inside does not exist reverse-conducting diode, during use, need external recovery diode; Meanwhile, the switching speed of IGBT (comprising opening speed and turn-off speed) is generally significantly less than MOSFET.
Vertical double-diffusion metal-oxide-semiconductor field effect transistor (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor, VDMOSFET) be how sub-device, and be voltage-controlled device, wherein, source electrode 4 ' ', drain 5 ' ', grid 3 ' ' and raceway groove 6 ' ' as shown in Figure 3.Under the control of suitable grid voltage, semiconductor surface transoid, forms conducting channel, then between drain electrode and source electrode, flow through appropriate electric current, and electric current perpendicular flow.VDMOS is mainly used in electric machine speed regulation, inverter, uninterrupted power supply, electronic switch, high-fidelity music center, car electrics and electric ballast etc., have and approach infinitely-great static input impedance characteristic, the distinguishing features such as very fast switching speed (comprising opening speed and turn-off speed), but its shortcoming is not have electricity to lead modulation, under certain puncture voltage designing requirement, normal state conducting resistance and on-state voltage drop are larger so conducting power loss is large than IGBT, are unfavorable for large electric current application.
At present, the improvement of semiconductor power device characteristic is mainly when its switching speed (comprising opening speed and turn-off speed) is improved, to reduce dependent loss, and the switching frequency of device also improves thereupon.Therefore, need a kind of semiconductor power device badly, both there is very fast switching speed (comprising opening speed and turn-off speed), there is again lower conducting resistance and conducting power loss simultaneously.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of semiconductor power device, for solving semiconductor power device of the prior art, can not take into account very fast switching speed (comprising opening speed and turn-off speed) and lower conducting resistance and the problem of conducting power loss, solve the problem that IGBT of the prior art needs external reverse-conducting diode simultaneously.
For achieving the above object and other relevant objects, the invention provides a kind of semiconductor power device, described device at least comprises:
Drain electrode;
Drain region, is heavy doping the first conduction type, is formed in described drain electrode;
Drift region, is light dope the first conduction type, is formed on described drain region;
Tagma, is the second conduction type, is formed at a side at top, described drift region;
Source region, is heavy doping the first conduction type, be formed at top, described tagma, and the surface, tagma of the side outside described source region is formed with raceway groove;
Gate region, is formed on described raceway groove and drift region, and contacts with tagma with described source region;
Heavy doping the second conductivity regions, is formed at top, described drift region and with respect to the opposite side in described tagma;
Isolation structure, is covered in the surface of described gate region and drift region, and is respectively equipped with the through hole that exposes part described source region and tagma and expose described heavy doping the second conductivity regions of part;
Source/emitter, is covered in the isolation structure on described gate region surface, and contacts with tagma by the through hole of the described isolation structure source region described with part, for described source region, tagma, realizes and being electrically connected to;
Collector electrode, be formed in described heavy doping the second conductivity regions, through hole by described isolation structure contacts with described heavy doping the second conductivity regions of part, and described collector electrode is joined together to form and is realized the drain/collector being electrically connected to by lead-in wire with drain electrode;
Terminal structure, is formed at the top of described drift region, and is formed between described tagma and heavy doping the second conductivity regions, to reduce surface field, the position of electrical breakdown is shifted under described tagma by surface, improves the high pressure resistant property of device.
Alternatively, described drift region comprises the first drift region and is formed at the second drift region on described the first drift region, described tagma, heavy doping the second conductivity regions and be formed at the top that terminal structure between the two is all formed at described the second drift region.
Alternatively, the doping content of the second described drift region is less than the doping content of the first drift region.
Alternatively, the thickness of the second described drift region is less than the thickness of the first drift region.
Alternatively, between the second described drift region and heavy doping the second conductivity regions, be also provided with buffering area, described buffering area is formed at the second top, drift region and with respect to the opposite side in described tagma, described heavy doping the second conductivity regions is formed at the top of buffering area, wherein, described buffering area is heavy doping the first conduction type.
Alternatively, between described drift region and heavy doping the second conductivity regions, be also provided with buffering area, described buffering area is formed at top, drift region and with respect to the opposite side in described tagma, and described heavy doping the second conductivity regions is formed at the top of buffering area, wherein, described buffering area is heavy doping the first conduction type.
Alternatively, described buffering area doping content is lower than source region doping content and drain region doping content.
Alternatively, described terminal structure at least comprises knot termination extension terminal structure, a limiting protecting ring terminal structure, field plate terminal structure, field plate and a limiting protecting ring composite terminal structure or field plate and knot termination extension composite terminal structure.
Alternatively, described gate region comprises gate dielectric layer and is formed at the grid on described gate dielectric layer.
Alternatively, on described grid, be also provided with insulating barrier.
Alternatively, described semiconductor power device forward conduction, in described device, form the forward conduction electric current that at least comprises the first forward conduction electric current and the second forward conduction electric current, wherein, the first conduction type is that N-type, the second conduction type are while being P type, described the first forward conduction electric current flows to raceway groove by described heavy doping the second conductivity regions, and described the second forward conduction electric current flows to raceway groove by described drain region; The first conduction type is P type, the second conduction type while being N-type, and described the first forward conduction electric current flows to heavy doping the second conductivity regions by described raceway groove, and described the second forward conduction electric current flows to drain region by described raceway groove.
Alternatively, the first described forward conduction electric current is less than the second forward conduction electric current, to guarantee that the conducting resistance of device and conducting power loss improve the switching speed of device when reducing.
Alternatively, described semiconductor power device reverse-conducting, described tagma, ,Ji drain region, drift region form reverse-conducting diode, wherein, the first conduction type is that N-type, the second conduction type form the reverse-conduction current that is flowed to drain region by described tagma while being P type, and the first conduction type is that P type, the second conduction type form the reverse-conduction current that is flowed to tagma by described drain region while being N-type.
As mentioned above, semiconductor power device of the present invention, there is following beneficial effect: by dexterously in conjunction with conventional I GBT and VDMOS, formation has the novel semi-conductor power device of the present invention being comprised of basic transversal I GBT and basic VDMOS of common sparing, wherein, described common sparing is drift region, tagma, source region, gate region, isolation structure, source/emitter, further, adjust the doping content of heavy doping the second conductivity regions of the present invention or the method for employing life-span control, to reduce the size of the first forward conduction electric current of basic transversal I GBT generation, increased the size of the second forward conduction electric current of basic VDMOS generation simultaneously, and make described the first forward conduction electric current be less than the second forward conduction electric current, make the present invention compared to IGBT of the prior art and VDMOS, in the switching speed (comprising opening speed and turn-off speed) that guarantees to improve when the conducting resistance of device and conducting power loss reduce device, combine the advantage that conventional I GBT and VDMOS have, make the bright semiconductor power device of this law there is more wide application prospect, can be used on power supply, solar inverter, motor driving etc. needs the application of high voltagehigh frequency switch, by improving the structure of drift region, the negative differential resistance region of further eliminating forward conduction, the perfect bright performance of this law.
Accompanying drawing explanation
Fig. 1 is shown as the structural representation of NPT-IGBT in prior art.
Fig. 2 is shown as the structural representation of PT-IGBT in prior art or FS-IGBT.
Fig. 3 is shown as the structural representation of VDMOS in prior art.
Fig. 4 is shown as the structural representation of semiconductor power device of the present invention in embodiment mono-.
Fig. 5 is shown as the schematic diagram of semiconductor power device the first forward conduction electric current of the present invention and the second forward conduction electric current.
Fig. 6 is shown as the schematic diagram of semiconductor power device reverse-conduction current of the present invention.
Fig. 7 is shown as the structural representation of semiconductor power device of the present invention in embodiment bis-.
Fig. 8 is shown as the forward conduction characteristic comparison diagram of the embodiment of the present invention one and the semiconductor power device of embodiment bis-when puncture voltage is 600V.
Element numbers explanation
101,5 ' ' drain electrode
102,1 ' collector electrode
20 drain regions
30 drift regions
301 first drift regions
302 second drift regions
40 tagmas
50 source regions
60 gate region
601 gate dielectric layers
602,3 ', 3 ' ' grid
603 insulating barriers
70 heavy doping the second conductivity regions
80 isolation structures
90 source/emitter
110 terminal structures
120 buffering areas
130,6 ' ' raceway groove
2 ' emitter
4 ' ' source electrode
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to Fig. 4 to Fig. 8.It should be noted that, the diagram providing in following specific embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
Embodiment mono-
As shown in Figure 4, the invention provides a kind of semiconductor power device, described device at least comprises: drain 101,40, source region, 30, tagma, 20, drift region, drain region 50, gate region 60, heavy doping the second conductivity regions 70, isolation structure 80, source/emitter 90, collector electrode 102, terminal structure 110.
It is pointed out that in the present embodiment one, the first conduction type is N-type, and the second conduction type is P type, but is not limited to this, and in other embodiments, described the first conduction type can be P type, and described the second conduction type is N-type; The material of 40, source region, 30, tagma, 20, drift region, described drain region 50, heavy doping the second conductivity regions 70, terminal structure 110 is silicon materials, but is not limited to this, and in other embodiments, the material in described respectively this region also can be carborundum or gallium nitride.
Described drain electrode 101 is formed at described drain region 20 times, for being electrically connected to, uses, and in the present embodiment one, described drain electrode 101 is aluminium, and in other embodiments, the material of described drain electrode 101 is polysilicon, copper or aluminium copper.
Described drain region 20 is heavy doping the first conduction type, is formed in described drain electrode 101, particularly, and in the present embodiment one, described drain region 20 attach most importance to doped N-type silicon, i.e. N+ type drain region 20.
Described drift region 30 is light dope the first conduction type, is formed on described drain region 20, and particularly, in the present embodiment one, described drift region 30 is light dope N-type silicon, i.e. N-type drift region 30.
Described tagma 40 is the second conduction type, is formed at a side at 30 tops, described drift region, and particularly, in the present embodiment one, described tagma 40 is P type silicon.
Described source region 50 is heavy doping the first conduction type, be formed at 40 tops, described tagma, and 40 surfaces, tagma of the side outside described source region 50 are formed with raceway groove 130, particularly, in the present embodiment one, the described source region 50 doped N-type silicon of attaching most importance to, i.e. N+ type source region 50, and the doping content in described source region 50 and the doping content in drain region 20 are at the same order of magnitude; Described tagma 40 is formed between 50Yu drift region, source region 30.
Described gate region 60 is formed on described raceway groove 130 and drift region 30, and contacts with described 50He tagma, source region 40.It should be noted that, described gate region 60 comprises gate dielectric layer 601 and is formed at the grid 602 on described gate dielectric layer 601; Further, on described grid 602, be also provided with insulating barrier 603, wherein, described gate dielectric layer 601 is silicon nitride, silicon oxynitride or silica, described grid 602 is polysilicon, aluminium, copper or aluminium copper, and described insulating barrier 603 is silicon nitride, silicon oxynitride or silica.In the present embodiment one, described gate region 60 comprises gate dielectric layer 601, grid 602 and insulating barrier 603, wherein, described gate dielectric layer 601 is silica, and insulating barrier 603 is silicon nitride, and described grid 602 is heavy doping the first conduction type (N+ type) polysilicon., but be not limited to this, in other embodiments, described gate region 60 comprises gate dielectric layer and grid, and gate dielectric layer 131 also can be silicon nitride.
Described heavy doping the second conductivity regions 70 is formed at 30 tops, described drift region and with respect to the opposite side in described tagma 40, particularly, in the present embodiment one, described heavy doping the second conductivity regions 70 is heavy doping P Xing Gui ，JiP+Xing district 70.
It should be noted that, in order to prevent that depletion layer arrives heavy doping the second conductivity regions 70 when the blocking voltage, and for controlling the ability of described heavy doping the second conductivity regions 70 injected minority carriers, control the injection efficiency of described heavy doping the second conductivity regions 70, between described drift region 30 and heavy doping the second conductivity regions 70, be also provided with buffering area 120, described resilient coating 120 is heavy doping the first conduction type, simultaneously, the heavy dopant concentration of described buffering area 120 is generally lower than the heavy dopant concentration in source region 50 heavy dopant concentration and drain region 20, wherein, the doping content in described source region 50 doping contents and drain region 20 is at the same order of magnitude, but, the heavy dopant concentration of described buffering area 120 is higher than the light dope concentration of drift region 30.Particularly, in the present embodiment one, the first conduction type is N-type, the second conduction type is P type, 120Wei silicon materials district, described N+ type buffering area, but be not limited to this, in other embodiments, the material of described N+ type buffering area 120 also can be carborundum or gallium nitride; Described N+ type buffering area 120 is formed at 30 tops, N-type drift region and with respect to the opposite side in described P type tagma 40, and described heavy doping the second conductivity regions 70(P+ type) be formed at the top of described N+ type buffering area 120, described N+ type buffering area 120 is formed at described N-type drift region 30 and heavy doping the second conductivity regions 70(P+ type) between.
Described isolation structure 80 is covered in the surface of described gate region 60 and drift region 30, and be respectively equipped with and expose the described source region 50 of part and with respect to the opposite side tagma 40 of described raceway groove 130, and expose the through hole of described heavy doping the second conductivity regions 70 of part, thereby guarantee between described gate region 60 and described source/emitter 90, described collector electrode 102 and the device surface between source/emitter 90 can bear high voltage, wherein, described isolation structure 80 is single layer structure or laminated construction, described single layer structure wherein or the material of the every one deck in described laminated construction are silica, silicon nitride, silicon oxynitride, phosphorosilicate glass, or semi-insulating polysilicon (Semi-insulating polycrystalline-silicon, SIPOS) any one in, in the present embodiment one, described isolation structure 80 is mono-layer oxidized silicon structure.
Described source/emitter 90 is covered in the isolation structure 80 on described gate region 60 surfaces, and contact by the through hole of the described isolation structure 80 50He tagma, source region 40 described with part, for described 50, tagma, source region 40, realize and being electrically connected to, particularly, in the present embodiment one, described source/emitter 90 is aluminium, and in other embodiments, the material of described source/emitter 90 also can be polysilicon, copper or aluminium copper.
Described collector electrode 102 is formed in described heavy doping the second conductivity regions 70, through hole by described isolation structure 80 contacts with the described heavy doping of part the second conduction type 70th district, and described collector electrode 102 links together by lead-in wire with drain electrode 101, form and realize the drain/collector being electrically connected to, particularly, in the present embodiment one, described collector electrode 102 is aluminium, in other embodiments, the material of described collector electrode 102 is polysilicon, copper or aluminium copper.
Described terminal structure 110 is formed at the top of described drift region 30, and is formed between described tagma 40 and heavy doping the second conductivity regions 70, to reduce surface field, the position of electrical breakdown is shifted under described tagma by surface, improves the high pressure resistant property of device.Wherein, described terminal structure 110 is in order to make the PN junction being produced by low pressure IC technique can bear high pressure design, and described terminal structure 110 is the necessary and basic fundamentals of producing high tension apparatus.Described terminal structure at least comprises adopting ties termination extension (Junction Termination Extension; JTE) the knot termination extension terminal structure of technology, an employing limiting protecting ring (Floating Ring; FR) the field limiting protecting ring terminal structure of technology, employing field plate (Field Plate; FP) the field plate terminal structure of technology, field plate (FP) and limiting protecting ring (FR) composite terminal structure or field plate (FP) and knot termination extension (JTE) composite terminal structure, and respectively this terminal structure technique simple and with IC process compatible.Particularly; in the present embodiment one, adopt a limiting protecting ring terminal structure 110; as shown in Figure 4; its midfield limiting protecting ring terminal structure 110 is illustrated with three the second conduction types (P type) district; and shown in the second conduction type (P type) district in limiting protecting ring number and between distance according to concrete puncture voltage, can be optimized design; be not limited to the second conduction type shown in Fig. 4 (P) district number and between distance, at this, do not repeat one by one.
For the ease of understanding the characteristic of the semiconductor power device described in embodiment mono-, below introduce its relevant operation principle:
Semiconductor power device in the embodiment of the present invention one is the New Type Power Devices of comprehensive IGBT and MOSFET advantage, wherein, gate region 60, source/emitter 90, source region 50, tagma 40, drift region 30, heavy doping the second conductivity regions 70, resilient coating 120, collector electrode 102, isolation structure 80 forms basic transversal I GBT, drain electrode 101, drain region 20, drift region 30, tagma 40, source region 50, gate region 60, source/emitter 90, isolation structure 80 has formed basic VDMOS, and described basic transversal I GBT and basic VDMOS have shared described drift region 30, tagma 40, source region 50, gate region 60, isolation structure 80, source/emitter 90.
The first conduction type in embodiment mono-is N-type, and the second conduction type is P type, and channel type is N raceway groove.When the threshold voltage of described grid 602 voltages higher than described semiconductor power device, and when 101/ collector electrode 102 voltages that drain are greater than the voltage of source/emitter 90, the semiconductor power device forward conduction in the embodiment of the present invention one, form the forward conduction electric current that at least comprises the first forward conduction electric current and the second forward conduction electric current, as shown in Figure 5.Wherein, described the first forward conduction electric current is the forward conduction electric current of basic transversal I GBT, is transverse current, flows to raceway groove, by described heavy doping the second conductivity regions 70 as shown in the dotted line of the attached arrow in Fig. 5; Described the second forward conduction electric current is the forward conduction electric current of basic VDMOS, is longitudinal current, flows to raceway groove, by described drain region 20 as shown in the solid line of the attached arrow in Fig. 5.
It is to be noted, by adjusting the doping content of described heavy doping the second conductivity regions 70 or the method for employing life-span control, to regulate the CURRENT DISTRIBUTION size of described the first forward conduction electric current and the second forward conduction electric current, the first described forward conduction electric current is diminished and be even less than the second forward conduction electric current.Wherein, owing to being also provided with buffering area 120 in the present embodiment one, when adjusting the doping content of described heavy doping the second conductivity regions 70, the doping content of described buffering area 120 is adjusted, also can be reached the effect that regulates forward conduction CURRENT DISTRIBUTION; The method that the described life-span is controlled at least comprises electron irradiation.
Now, described the second forward conduction electric current is taken electric current as the leading factor, and to guarantee that the conducting resistance of device and conducting power loss improve the switching speed (comprising opening speed and turn-off speed) of device when reducing, reason is:
On the one hand, in the present embodiment one, heavy doping the second conductivity regions (P+ type) 70 of basic transversal I GBT is injected into described N-type drift region 30 by hole, the injection in this hole (few son) has greatly reduced the equivalent resistance of described N-type drift region 30, greatly increased conductivity, conductivity is modulated, the little electric current (the first forward conduction electric current) that is basic transversal I GBT is led modulation for electricity, the conducting resistance of the N-type drift region 30 of power device of the present invention is reduced, therefore, the conductive capability of power device of the present invention is improved, reduced conduction voltage drop, reduced conducting power loss,
On the other hand, because described the second forward conduction electric current (the forward conduction electric current of basic VDMOS) is taken electric current as the leading factor, it is much larger than described the first forward conduction electric current (the forward conduction electric current of basic transversal I GBT), therefore, for the switching speed impact of (comprising opening speed and turn-off speed), the impact that the second forward conduction electric current produces much larger than the first forward conduction electric current, in other words, the switching speed of semiconductor power device of the present invention depends primarily on (comprising opening speed and turn-off speed) impact of the second forward conduction electric current in forward conduction electric current, the the first forward conduction electric current producing compared with the basic transversal I GBT of slow switching speed is little on the impact of semiconductor power device switching speed of the present invention, further, owing to producing the basic VDMOS of the second forward conduction electric current, be many sons (electronics) conductions, thereby its switching speed (comprising opening speed and turn-off speed) is very fast, therefore, the switching speed of semiconductor power device of the present invention (comprising opening speed and turn-off speed) is improved significantly compared to conventional I GBT, more than the switching speed of the device of optimal design of the present invention can arrive 100 kHz, device of the present invention can be worked under the switching frequency at high 10 times than conventional I GBT.
The first conduction type in embodiment mono-is N-type, and the second conduction type is P type, and channel type is N raceway groove.When described drain electrode 101/ collector electrode 102 voltages are less than the voltage of source/emitter 90, the semiconductor power device reverse-conducting in the embodiment of the present invention one, as shown in Figure 6, the reverse-conducting diode that described P type tagma 40, N-type drift region 30 and N+ type drain region 20 form, formation is flowed to the reverse-conduction current in N+ type drain region 20 by described P type tagma 40, solve the problem that IGBT of the prior art needs external reverse-conducting diode.
It is to be noted, for the semiconductor power device in other embodiment, the first conduction type is P type, when the second conduction type is N-type, channel type is P raceway groove, the condition of described semiconductor power device forward conduction and reverse-conducting and the flow direction of forward conduction electric current and reverse-conducting are different from the situation of embodiment mono-, but size of current is not affected by it, specific as follows;
When the threshold voltage of described grid voltage lower than described semiconductor power device, and when drain/collector voltage is less than the voltage of source/emitter, described semiconductor power device forward conduction, and the first forward conduction electric current flows to described heavy doping the second conductivity regions (N+) (not shown) by raceway groove, the second forward conduction electric current flows to described drain region (P+) (not shown) by raceway groove;
When drain/collector voltage is greater than the voltage of source/emitter, described semiconductor power device reverse-conducting, the reverse-conducting diode that described N-type tagma, P-type drift region and P+ type drain region form, formation is flowed to the reverse-conduction current (not shown) in N-type tagma by described P+ type drain region, solve the problem that IGBT of the prior art needs external reverse-conducting diode.
Semiconductor power device in the present embodiment one, in conjunction with conventional I GBT and VDMOS, forms the novel semi-conductor power device being comprised of basic transversal I GBT and basic VDMOS with common sparing by dexterously, adjust the doping content of heavy doping the second conductivity regions of the present invention and buffering area or the method for employing life-span control, with the first forward conduction electric current that regulates basic transversal I GBT to produce, be less than the electric current of the second forward conduction electric current of basic VDMOS generation, make the present invention compared to IGBT of the prior art and VDMOS, in the switching speed (comprising opening speed and turn-off speed) that guarantees to improve when the conducting resistance of device and conducting power loss reduce device, combine the advantage that conventional I GBT and VDMOS have, make the bright semiconductor power device of this law there is more wide application prospect, can be used on power supply, solar inverter, motor driving etc. needs the application of high voltagehigh frequency switch.
Embodiment bis-
The present embodiment two adopts essentially identical technical scheme with embodiment mono-, and difference is, the drift region 30 in embodiment mono-is divided into the first drift region 301 and is formed at the second drift region 302 on described the first drift region in the present embodiment two.
As shown in Figure 7, the invention provides a kind of semiconductor power device, described device at least comprises: drain 101, drain region 20, the first drift region 301, the second 40, source region, 302, tagma, drift region 50, gate region 60, heavy doping the second conductivity regions 70, isolation structure 80, source/emitter 90, collector electrode 102, terminal structure 110.Below only to be different from the part of embodiment mono-, elaborate, no longer do one by one and repeat with embodiment mono-same section.
In the present embodiment two, described the first drift region 301 is formed on described drain region 20, and described the second drift region 302 is formed on described the first drift region 301; The doping content of the second described drift region 302 is less than the doping content of the first drift region 302, is light dope the first conduction type; The thickness of the second described drift region 302 is less than the thickness of the first drift region 301.
Particularly, be different from embodiment mono-, in the tagma 40 described in the present embodiment two, heavy doping the second conductivity regions 70 and be formed at the top that terminal structure 110 between the two is all formed at described the second drift region 302.
It is to be noted, in order to prevent that depletion layer arrives heavy doping the second conductivity regions 70 when the blocking voltage, and for controlling the ability of described heavy doping the second conductivity regions 70 injected minority carriers, control the injection efficiency of described heavy doping the second conductivity regions 70, between the second described drift region 302 and heavy doping the second conductivity regions 70, be also provided with buffering area 120, wherein, described resilient coating 120 is heavy doping the first conduction type, simultaneously, the heavy dopant concentration of described buffering area 120 is lower than the heavy dopant concentration in source region 50 heavy dopant concentration and drain region 20, wherein, the doping content in described source region 50 doping contents and drain region 20 is at the same order of magnitude, but, the heavy dopant concentration of described buffering area 120 is higher than the light dope concentration of described the first drift region 301 and the second drift region 302.Particularly, in the present embodiment two, the first conduction type is N-type, and the second conduction type is P type, and described N+ type buffering area 120 is silicon materials, but is not limited to this, and in other embodiments, the material of described N+ type buffering area 120 also can be carborundum or gallium nitride; Described N+ type buffering area 120 is formed at described N-type 302 tops, the second drift region and with respect to the opposite side in described P type tagma 40, and described heavy doping the second conductivity regions 70(P+) be formed at the top of described N+ type buffering area 120, described N+ type buffering area 120 is formed at described N-type the second drift region 302 and heavy doping the second conductivity regions 70(P+ type) between.
In the present embodiment two, the material of described drain region 20, the first drift region 301, the second 40, source region, 302, tagma, drift region 50, heavy doping the second conductivity regions 70, terminal structure 110 is formed by silicon materials, but be not limited to this, in other embodiments, can also realize device of the present invention with materials such as carborundum or gallium nitride.
Similar (referring to the associated description in embodiment mono-) in the operation principle of the described semiconductor power device in the present embodiment two and embodiment mono-, difference is:
Fig. 8 is shown as the forward conduction characteristic comparison diagram of the embodiment of the present invention one and the semiconductor power device of embodiment bis-when puncture voltage is 600V, wherein, curve A is the forward conduction characteristic curve of semiconductor power device when voltage 600V in embodiment mono-, and curve B-D is the forward conduction characteristic curve of semiconductor power device when voltage 600V in embodiment bis-.
It is pointed out that the semiconductor power device that has negative differential resistance region, its performance is mainly reflected in by the impact of negative differential resistance region: on the one hand, between described semiconductor power device and other external circuit components and parts, can produce small signal oscillation; On the other hand, described semiconductor power device can not be in parallel with all the other components and parts.In view of this, in embodiment bis-, drift region 30 is divided into the first drift region 301 and is formed at the second drift region 302 on described the first drift region.
Need to further be pointed out that, by progressively reducing the doping content of described the second drift region 302 or progressively increasing thickness proportion in the second described 302 drift region, drift region 30 (refer to curve B to curve D) in Fig. 8, make described heavy doping the second conductivity regions 70 guarantee normal Injection Current, thereby reduce the negative differential resistance region of device, finally thoroughly eliminate negative differential resistance region (as shown in curve D in Fig. 8), further optimized the performance of semiconductor power device of the present invention.
Semiconductor power device in the present embodiment two, in conjunction with conventional I GBT and VDMOS, forms the novel semi-conductor power device being comprised of basic transversal I GBT and basic VDMOS with common sparing by dexterously, adjust the doping content of heavy doping the second conductivity regions of the present invention and buffering area or the method for employing life-span control, with the first forward conduction electric current that regulates basic transversal I GBT to produce, be less than the electric current of the second forward conduction electric current of basic VDMOS generation, make the present invention compared to IGBT of the prior art and VDMOS, in the switching speed (comprising opening speed and turn-off speed) that guarantees to improve when the conducting resistance of device and conducting power loss reduce device, combine the advantage that conventional I GBT and VDMOS have, make the bright semiconductor power device of this law there is more wide application prospect, can be used on power supply, solar inverter, motor driving etc. needs the application of high voltagehigh frequency switch, by improving the structure of drift region, the negative differential resistance region of further eliminating forward conduction, the perfect bright performance of this law.
In sum, semiconductor power device of the present invention is the novel semi-conductor power device being comprised of basic transversal I GBT and basic VDMOS with common sparing; In the switching speed (comprising opening speed and turn-off speed) that guarantees to improve when the conducting resistance of device and conducting power loss reduce device, combine the advantage that conventional I GBT and VDMOS have, make the bright semiconductor power device of this law there is more wide application prospect, can be used on the application that power supply, solar inverter, motor driving etc. need high voltagehigh frequency switch; By improving the structure of drift region, the negative differential resistance region of further eliminating forward conduction, the perfect bright performance of this law.So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (13)
1. a semiconductor power device, is characterized in that, described device at least comprises:
Drain electrode;
Drain region, is heavy doping the first conduction type, is formed in described drain electrode;
Drift region, is light dope the first conduction type, is formed on described drain region;
Tagma, is the second conduction type, is formed at a side at top, described drift region;
Source region, is heavy doping the first conduction type, be formed at top, described tagma, and the surface, tagma of the side outside described source region is formed with raceway groove;
Gate region, is formed on described raceway groove and drift region, and contacts with tagma with described source region;
Heavy doping the second conductivity regions, is formed at top, described drift region and with respect to the opposite side in described tagma;
Isolation structure, is covered in the surface of described gate region and drift region, and is respectively equipped with the through hole that exposes part described source region and tagma and expose described heavy doping the second conductivity regions of part;
Source/emitter, is covered in the isolation structure on described gate region surface, and contacts with tagma by the through hole of the described isolation structure source region described with part, for described source region, tagma, realizes and being electrically connected to;
Collector electrode, be formed in described heavy doping the second conductivity regions, through hole by described isolation structure contacts with described heavy doping the second conductivity regions of part, and described collector electrode is joined together to form and is realized the drain/collector being electrically connected to by lead-in wire with drain electrode;
Terminal structure, is formed at the top of described drift region, and is formed between described tagma and heavy doping the second conductivity regions, to reduce surface field, the position of electrical breakdown is shifted under described tagma by surface, improves the high pressure resistant property of device.
2. semiconductor power device according to claim 1, it is characterized in that: described drift region comprises the first drift region and be formed at the second drift region on described the first drift region, described tagma, heavy doping the second conductivity regions and be formed at the top that terminal structure between the two is all formed at described the second drift region.
3. semiconductor power device according to claim 2, is characterized in that: the doping content of the second described drift region is less than the doping content of the first drift region.
4. semiconductor power device according to claim 2, is characterized in that: the thickness of the second described drift region is less than the thickness of the first drift region.
5. semiconductor power device according to claim 2, it is characterized in that: between the second described drift region and heavy doping the second conductivity regions, be also provided with buffering area, described buffering area is formed at the second top, drift region and with respect to the opposite side in described tagma, described heavy doping the second conductivity regions is formed at the top of buffering area, wherein, described buffering area is heavy doping the first conduction type.
6. semiconductor power device according to claim 1, it is characterized in that: between described drift region and heavy doping the second conductivity regions, be also provided with buffering area, described buffering area is formed at top, drift region and with respect to the opposite side in described tagma, and described heavy doping the second conductivity regions is formed at the top of buffering area, wherein, described buffering area is heavy doping the first conduction type.
7. according to the semiconductor power device described in claim 5 or 6, it is characterized in that: described buffering area doping content is lower than source region doping content and drain region doping content.
8. semiconductor power device according to claim 1 and 2, is characterized in that: described terminal structure at least comprises knot termination extension terminal structure, a limiting protecting ring terminal structure, field plate terminal structure, field plate and a limiting protecting ring composite terminal structure or field plate and knot termination extension composite terminal structure.
9. semiconductor power device according to claim 1, is characterized in that: described gate region comprises gate dielectric layer and is formed at the grid on described gate dielectric layer.
10. semiconductor power device according to claim 9, is characterized in that: on described grid, be also provided with insulating barrier.
11. semiconductor power devices according to claim 1 and 2, it is characterized in that: described semiconductor power device forward conduction, in described device, form the forward conduction electric current that at least comprises the first forward conduction electric current and the second forward conduction electric current, wherein, the first conduction type is that N-type, the second conduction type are while being P type, described the first forward conduction electric current flows to raceway groove by described heavy doping the second conductivity regions, and described the second forward conduction electric current flows to raceway groove by described drain region; The first conduction type is P type, the second conduction type while being N-type, and described the first forward conduction electric current flows to heavy doping the second conductivity regions by described raceway groove, and described the second forward conduction electric current flows to drain region by described raceway groove.
12. semiconductor power devices according to claim 11, is characterized in that: the first described forward conduction electric current is less than the second forward conduction electric current, to guarantee that the conducting resistance of device and conducting power loss improve the switching speed of device when reducing.
13. semiconductor power devices according to claim 1 and 2, it is characterized in that: described semiconductor power device reverse-conducting, described tagma, ,Ji drain region, drift region form reverse-conducting diode, wherein, the first conduction type is that N-type, the second conduction type form the reverse-conduction current that is flowed to drain region by described tagma while being P type, and the first conduction type is that P type, the second conduction type form the reverse-conduction current that is flowed to tagma by described drain region while being N-type.
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