CN103563067A - 用于减轻半导体管芯中应力的布线层 - Google Patents

用于减轻半导体管芯中应力的布线层 Download PDF

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CN103563067A
CN103563067A CN201280019784.1A CN201280019784A CN103563067A CN 103563067 A CN103563067 A CN 103563067A CN 201280019784 A CN201280019784 A CN 201280019784A CN 103563067 A CN103563067 A CN 103563067A
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pad
ubm
bump pad
bump
trace
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CN103563067B (zh
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罗登·托帕奇奥
加布里埃尔·翁
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ATI Technologies ULC
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ATI Technologies ULC
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Abstract

公开一种用于半导体管芯的布线层。所述布线层包括把集成电路接合焊盘与UBM互连的迹线。所述布线层在介电材料层上形成。所述布线层包括设置在所述UBM下以吸收来自附接到所述UMB的焊料凸块的应力的导电迹线。所述UBM下的迹线保护靠近所述焊料凸块的所述下面的介电材料的部分免受所述应力影响。

Description

用于减轻半导体管芯中应力的布线层
相关申请案
本申请是2009年10月23日提交的美国专利申请序列号12/604,584的部分继续，所述申请的内容在此以引入方式并入本文。
技术领域
本发明大体上涉及半导体方块，且更具体说来涉及用于半导体管芯的布线层设计。
发明背景
现代半导体封装是通过在半导体晶片上形成多个集成电路来制造的。晶片通常被切成小块-切割成单个的块-每个小块称为管芯。每个管芯包括一个表面上的一个或更多个集成电路。这个表面（通常称为“活性表面”）包括称为输入/输出（I/O）焊盘的多个信号接口触点。
管芯通常使用包括适于附接到外部电路板上的焊球的载体基板来封装。载体基板通常包括核心和在核心的任一侧上形成的一个或更多个堆积层。每个堆积层具有在介电材料层上形成的金属化或迹线。载体基板包括用于与管芯的I/O焊盘电互连的接合焊盘。基板上的迹线用以把个别接合焊盘与它们对应的焊球互连。
可使用各种接合技术来在管芯上的I/O焊盘和基板上的接合焊盘之间形成可靠的电连接。两种最流行的技术是引线接合和倒装芯片组装。
在引线接合中，管芯放置在载体基板上，其中它的活性表面背对载体基板。引线然后一端接合到管芯上的I/O焊盘，而另一端接合到基板上的对应的接合焊盘。
然而，在倒装芯片组装中，当附接管芯时，管芯的活性表面朝向载体基板。称为焊料凸块的少量焊料在附接之前沉积到每个I/O焊盘上。然后熔融焊料凸块以把管芯上的每个I/O焊盘与基板上的对应的接合焊盘互连。
管芯上的I/O焊盘可放置在管芯的活性表面上任何位置。例如，在一些方块中，I/O焊盘可分布在整个活性表面上，而在其它方块中，I/O焊盘可限于靠近管芯的外围边界。在任一状况下，管芯上的I/O焊盘通常不与它们最终附接到的基板上的接合焊盘对齐。如在倒装芯片组装期间所需要地，I/O焊盘也可彼此太接近以允许适当的焊料凸块形成。因此，把这些原始I/O焊盘重新分布到更适于焊料凸块形成的新的焊盘位置（称为凸块焊盘）常常是有利的。凸块焊盘然后可与基板上的接合焊盘对齐并使用焊料凸块来附接。为了把原始I/O焊盘重新分布到适于倒装芯片接合的新的凸块焊盘位置，布线层或重新分布层（RDL）通常在硅晶片上形成或者在个别管芯上的活性表面上形成。
布线层通常在薄介电层上形成，在所述薄介电层上形成导电迹线以把每个I/O焊盘与对应的凸块焊盘互连。迹线与管芯的下层被介电材料隔离，除了它们互连的I/O焊盘处。布线层允许I/O驱动器放置在管芯中任何位置，而不需要考虑基板接合焊盘的位置。I/O驱动器因此可自由放置在管芯中，因为重新分布层将使它凸块焊盘上形成的焊料凸块与基板上的接合焊盘对齐。布线层的使用也简化了基板的形成，且常产生较少堆积层，从而降低了成本。
布线层可取决于布线需要而包括多个介电材料层和相关迹线。常在顶部布线层上形成钝化层，以保护金属迹线不暴露于空气。钝化层中的开口暴露凸块焊盘。
凸块下金属化（UBM）通常在暴露的凸块焊盘上形成，以提供低电阻电连接到焊料凸块，从而附接到基板。焊料凸块通常例如通过沉积焊膏来在凸块焊盘的UBM上形成。
在倒装芯片连接期间，重新分布的凸块焊盘上形成的焊料凸块与基板中对应的接合焊盘对齐，然后回流或熔融以形成可靠电和机械触点。
在半导体管芯附接到基板之后，它的焊料凸块在操作期间常经受机械和热应力。每个凸块焊盘有助于吸收否则将影响布线层中下面的介电层的一些应力。为了缓冲来自焊料凸块的所述应力，每个凸块焊盘常制成至少与它对应的UBM一样大（常实质大于它对应的UBM）。
然而，这是不利的，因为较大凸块焊盘减小了可用于在布线层中布线导电迹线的区域，从而导致可潜在危及信号完整性的迹线和凸块焊盘的密集的设置。另外，必须在大凸块焊盘周围布线的迹线可能需要更长，从而增大了它们的电阻和电容。迹线上增大的电阻和电容常导致功率迹线中的电压降和信号迹线较长的传播延迟。另外，较新、较小的方块常需要小得多的凸块焊盘来增大它们布线需要的可用区域，且常使用脆性介电材料。
一种用于减小凸块焊盘尺寸的已知方法是在小凸块焊盘顶部形成的大UBM之间使用聚酰亚胺，以助于减轻可影响管芯的介电层的应力。然而，不幸的是，这增大了封装成本且可能不能与脆性介电层工作良好。
因此，需要允许增大迹线的数量而不会危及信号完整性并保护介电层免受热和机械应力影响的半导体管芯。
发明概要
根据本发明的一个方面，提供一种半导体管芯，包括：在一片半导体晶片的一个表面上形成的集成电路；与所述集成电路互连的多个输入/输出（I/O）焊盘；和布线层。所述布线层包括：在一个表面上形成的介电层；和在所述介电层上形成的多个导电迹线，所述导电迹线中的每个在所述I/O焊盘中的一个I/O焊盘与所述介电层上形成的多个凸块焊盘中的一个凸块焊盘之间延伸。所述半导体管芯也包括多个凸块下金属化（UBM），各自具有用于附接多个焊料凸块的各自的焊料凸块的顶面；和比所述顶面小且与所述凸块焊盘中各自的凸块焊盘物理接触的底部接触表面。所述导电迹线中的至少一些靠近所述凸块焊盘通过而不接触所述凸块焊盘，通过所述UBM中的一个UBM的顶面下面，以机械增强靠近所述UBM中的一个UBM的布线层。
根据本发明的又一方面，提供一种半导体管芯，包括：在一个表面上形成的至少一个集成电路，和连接到所述集成电路的多个输入/输出（I/O）焊盘；包括以下的布线层：在所述管芯的所述表面上形成的介电层，和在所述介电层上形成的多个导电迹线，所述导电迹线中的每个在所述I/O焊盘中的一个I/O焊盘与所述介电层上形成的多个凸块焊盘中的一个凸块焊盘之间延伸；和在所述凸块焊盘上形成的多个焊料凸块，用于把所述集成电路与基板电互连。所述凸块焊盘中的至少一个包括在半径大于或等于在所述每个凸块焊盘上形成的对应的凸块下金属化（UBM）的顶面的平均半径的圆限定区域中。所述导电迹线中的至少一些通过所述圆限定区域而不接触包括的凸块焊盘，以机械增强靠近所述包括的凸块焊盘的所述布线层。
本领域技术人员在结合附图参看本发明的特定实施方案的以下描述之后将显而易见本发明的其它方面和特征。
附图简述
在仅以举例的方式描述本发明的实施方案的附图中，
图1是把I/O焊盘重新分布到凸块焊盘的常规半导体管芯的常规布线层的平面图；
图2是常规半导体管芯的垂直剖面图；
图3是图2的常规半导体管芯的部分的平面图；
图4是本发明的实施方案的示范性半导体管芯的部分的垂直剖面图；
图5是图4示出的示范性半导体管芯的部分的平面图；
图6是图4的示范性半导体管芯的另一剖面图；
图7是示出图5的示范性凸块焊盘和图4的常规凸块焊盘的相对尺寸的图；
图8是图4的半导体管芯的示范性布线层的平面图；
图9是图8的平面图，其中为达与示范性凸块焊盘比较的目的绘出了常规凸块焊盘的外罩；
图10是本发明的实施方案的示范性半导体管芯的部分的垂直剖面图；
图11是图10示出的示范性半导体管芯的部分的平面图；和
图12是图10的半导体的布线层的平面图。
具体实施方式
图1示出常规半导体管芯100的布线层的平面图。管芯100包括形成集成电路的部分的原始I/O焊盘114A、114B、114C（个别或统称为I/O焊盘114），和适于进行倒装芯片焊料凸块形成的重新分布的凸块焊盘104A、104B、104C、104D（个别或统称为凸块焊盘104）。导电迹线122A、122B、122C、122D、122E、122F（个别或统称为导电迹线122）把I/O焊盘114与对应的凸块焊盘104互连。
图2示出常规半导体管芯100的部分的垂直剖面图，所述部分包括导电迹线122、I/O焊盘114和凸块焊盘104，焊料凸块112在凸块焊盘104上形成。I/O焊盘114在包括在一片半导体晶片（例如，硅晶片）上形成的集成电路的管芯100的下金属层116上形成。
凸块焊盘104提供到集成电路的I/O连接点。凸块焊盘104上形成的焊料凸块112用以使用倒装芯片连接技术把管芯100附接到例如载体基板或印刷线路板的基板。
在下金属层116上形成的布线层108包括介电层120和在介电层120上形成的导电迹线122。介电层120把下金属层116与导电迹线122隔离，除了在I/O焊盘114处。导电迹线122中每一个把I/O焊盘114与凸块焊盘104互连。
每个凸块焊盘104上形成的凸块下金属化（UBM）102向每个焊料凸块112提供低电阻附接表面。每个UBM102可具有与焊料凸块112通信的顶面102A和与凸块焊盘104通信的底部接触表面102B。
为了把管芯100与基板互连，焊料凸块112与基板上的接合焊盘对齐且使用热来熔融以与基板形成电和机械接合。
在操作期间，半导体管芯100消耗电压或电流输入形式的电能，并把一些所述能量作为热来消耗。热使管芯100和管芯100附接到的基板以各自的热膨胀系数（CTE）膨胀。管芯100的CTE和基板（管芯100通过焊料凸块112与所述基板互连）的CTE常不同。CTE值的这个不匹配在焊料凸块112和例如UBM102和布线层108中介电材料120的其它附近的结构上产生热应力。热应力以外，靠近焊料凸块112的结构也可经受由基板或管芯100的挠曲和/或振动产生的机械应力。
热和/或机械应力可潜在地损坏布线层108（具体说来，介电材料120）和下层116中使用的其它材料。例如，下层116中可使用极低K（ELK）介电材料（介电常数值K＜3.0）。然而，ELK材料倾向于发脆，且在机械或热应力下可能翘曲、破裂或折断。不必需是ELK的介电材料也可由于暴露于热和机械应力而损坏。
为了减轻应力对布线层108和下层116的介电材料120的影响，凸块焊盘104常制作得比UBM102大。大凸块焊盘有助于吸收否则将影响下面的介电材料的应力。
图3示出了UBM102和凸块焊盘104的表面的相对尺寸，图3示出沿图2的线III-III的常规管芯100的部分的平面图。如示出，常规凸块焊盘104比UBM102大，因此有助于吸收来自对应的焊料凸块（图3中未示出）的机械和热应力，从而防止对介电材料120和下层116造成损坏。
不幸的是，较大凸块焊盘104减小了可用于在布线层108中布线导电迹线122的可用区域。另外，一些迹线需要较长，以在较大焊盘104周围布线。如所述，长迹线产生增大的电阻和电容，这又导致功率迹线的电压降和信号迹线上增大的传播延迟。另外，使用45nm或更慢的过程技术形成的集成电路通常尺寸较小，且常用ELK介电材料来封装。例如凸块焊盘104的大凸块焊盘可能不适于所述设备。
因此，本发明的示范性实施方案可使用适于与ELK介电材料连用的较小尺寸的凸块焊盘。较小的焊盘尺寸可释放空间，从而允许在给定区域中增大功率和接地迹线的密度。相反地，新释放空间允许在平行迹线之间增大间隔，这样可减小串扰。如可理解地，减小的串扰和/或增加的功率和接地迹线有助于改善信号完整性并增大性能。
因此，图4示出本发明的实施方案的示范性半导体管芯200的垂直剖面图。图5示出图4中示范性管芯200的部分的平面图。如所示出，示范性管芯200包括在一片半导体晶片（例如，硅晶片或砷化镓晶片）上形成的集成电路（IC）和与IC互连的I/O焊盘214，I/O焊盘214可例如由铝（Al）或铜（Cu）制成。
管芯200也可包括由一个或更多个介电材料220层制成的布线层208，每个介电材料220层上形成有导电迹线222A、222B、222C（个别或统称为导电迹线222）层。管芯200可包括例如钝化层206的防护盖，以免导电迹线222暴露于空气，从而阻止氧化。导电迹线222可把I/O焊盘214与凸块焊盘204中的对应的凸块焊盘204互连。
可形成多个焊料凸块212，每个焊料凸块212都在一个凸块焊盘204上。焊料凸块212可用以使用倒装芯片附接方法来把管芯200附接到基板。焊料凸块212可与基板上对应的接合焊盘对齐，且被回流以形成电和机械接合。本领域技术人员已知倒装芯片附接方法。
每个导电迹线222可使I/O焊盘214一端连接到对应的凸块焊盘204（因此焊料凸块212）。方便地，凸块焊盘204提供到管芯200上的集成电路的I/O互连。
如可理解地，设计I/O焊盘214和相关I/O驱动器电路的放置而无需考虑凸块焊盘放置可能是有利的，以免干扰其它优化。I/O焊盘204可为区域焊盘、多列焊盘、周边焊盘等。不管I/O焊盘204的位置怎样，布线层208可用以把I/O焊盘214重新分布到凸块焊盘204以使焊料凸块212与基板上各自的接合焊盘对齐。
导电迹线222通常由铜或铝制成，但是也可由例如金、铅、锡、银、铋、锑、锌、镍、锆、镁、铟、碲、镓等的其它金属制成。也可使用上述金属中的一个或更多个的合金。
凸块下金属化（UBM）202可在每个凸块焊盘204上形成以向焊料凸块212提供低电阻安装表面。例如，在一个实施方案中，焊膏可沉积在每个UBM202上以形成每个焊料凸块212。
每个UBM202可具有与对应的焊料凸块212通信的顶面202A，和与下面的各自的凸块焊盘204通信的底部接触表面202B。UBM202在它顶面202A和它底部接触表面202B之间可包括若干子层（未示出），例如，粘合子层、扩散阻挡层子层、焊料吸附子层且可选地氧化阻挡子层。底部接触表面202B与凸块焊盘204物理接触。
UBM202的形成可包括清洗、绝缘氧化物去除和与焊料凸块212形成良好的电和机械连接的沉积冶金。焊料吸附子层向熔融焊料提供易吸附表面，以把焊料凸块212很好地接合到下面的凸块焊盘204。焊料凸块212（如图2的焊料凸块112）可使用热来熔融，以在半导体管芯200和基板或电路板之间形成电和机械互连。
如下文将详细讨论，管芯200的凸块焊盘204比管芯100的凸块焊盘104小。因此，布线层208提供更多的空间或添加的空间来布线导电迹线222，这可使长度变短。较短迹线是有利的，因为这使迹线电阻和电容减小。减小的电阻和电容值又使得功率迹线上的电压降减小且使信号迹线上的信号传播延迟变小。
图6示出沿图5的线VI-VI的半导体管芯200的垂直截面。如图6示出，示范性凸块焊盘204比它对应的UBM202小。示范性凸块焊盘204通过金属迹线222与I/O焊盘214互连。
比较图2与图4（或图3与图5），可观察到，较小凸块焊盘204，允许在与凸块焊盘104占据的区域大约相同的区域中布线多个导电迹线222A、222B和222C（个别或统称为导电迹线222）。图7和图9中进一步描述凸块焊盘104和凸块焊盘204的相对尺寸。
现在，为了减轻可能由于凸块焊盘204的减小的尺寸所产生的应力对布线层208中介电材料的影响，一个或更多个迹线222可用有助于吸收机械和/或热-机械应力的方式来在凸块焊盘204附近布线。
特别说来，在图4-6所述的特定实施方案中，导电迹线222A、222B、222C靠近凸块焊盘204通过以机械增强靠近UBM202的布线层208。围绕凸块焊盘204或靠近凸块焊盘204通过的导电迹线222A、222B的部分可在UBM202的顶面202A下面，但不在与凸块焊盘204物理接触的底部接触表面202B下面。导电迹线222A、222B因此增强了靠近UBM202的布线层208。靠近凸块焊盘204通过的导电迹线222A、222B的部分因此可吸收来自附接到凸块焊盘204的焊料凸块的机械和/或热应力，以保护靠近焊料凸块212的下面的介电材料220。
如图5示出，每个凸块焊盘204可包括在圆限定区域224中，圆限定区域224的半径Rarea不小于顶面UBM202A的平均半径RUBM（即，Rarea≥RUBM，其中RUBM=D2/2）。如下文将详细描述，导电迹线中的至少一些（例如，迹线222A、222B）可通过圆限定区域224而不直接接触其中包括的凸块焊盘，以机械增强靠近包括的凸块焊盘的布线层208。
凸块焊盘204和圆限定区域224中导电迹线222A、222B、222C的部分可视为具有（从应力吸收观点看来）跟常规凸块焊盘104一样大的有效尺寸的“虚拟焊盘”。限定区域224可有效缓冲来自对应的焊料凸块（在限定凸块焊盘204的UBM表面202A上形成）的应力，从而保护下面的介电材料免受应力导致的损坏。当然，在其它实施方案中，圆限定区域224的尺寸可与常规凸块焊盘104相等、大于常规凸块焊盘104或甚至稍微小于常规凸块焊盘104。
为了比较不同形状的焊盘、UBM和限定区域的相对尺寸，给定形状的内切圆的直径可被认为是代表形状的尺寸。
在图2中，UBM102的顶面102A中的内切圆的直径可约为80μm（即，d2≈80μm）。换句话说，UBM顶面102A的内径约为80μm/2=40μm。凸块焊盘104的内切圆的直径可约为92μm（即，d3≈92μm）；且开口110的内切圆的直径（或底部接触表面102B的内切圆的直径，且标记为d1）可约为60μm（即，d1≈60μm）。
然而，在图4中，在一个实施方案中，UBM202的顶面202A的直径（内切圆的直径）（标记为D2）可约为80μm（即，D2≈80μm）。凸块焊盘204的直径（内切圆的直径）可约为50μm（即，在图4中，D3≈50μm），且开口210的直径（内切圆的直径）（在图4中标记为D1）可约为46μm（即，D1≈46μm）。每个导电迹线222的宽度（标记为W1）可约为12μm。如本领域技术人员应理解，以上附图只是示范性的，且在其它实施方案中可使用较大或较小尺寸。
又，UBM表面202A、202B、凸块焊盘204和开口210的形状不必需统一也不必是八边形。相反，UBM202、凸块焊盘204和钝化开口210可采用任何形状且可具有变化的尺寸。它们可例如具有其它多边形形状，例如六边形或长方形。它们也可采用其它形状：它们可为圆形、椭圆形、不规则形状或任何合适尺寸的任意形状。
在示范性布线层208中把导电迹线222A、222B、222C设置在凸块焊盘204周围或围绕凸块焊盘204设置是有利的。除了允许增加在给定区域中信号布线迹线的数量，所述设置创建了呈圆限定区域224形式的应力缓冲区域，所述应力缓冲区域可有效地提供与大得多的常规凸块焊盘104一样多的保护以对抗应力。如可理解，应力被靠近凸块焊盘204（在区域224中）的导电迹线222A、222B、222C的部分吸收，所述应力否则将损坏布线层208的下面的介电材料。
图7示出示范性凸块焊盘204和常规凸块焊盘104以及代表各种应力缓冲区的轮廓的示范性圆限定区域的相对尺寸。区域702对应于较大常规凸块焊盘104和同心设置的较小示范性凸块焊盘204之间的表面区域的差。在常规凸块焊盘104中，没有区域702（形成凸块焊盘104的部分）可用于布线。方便地，区域702的部分可用于在使用凸块焊盘204的示范性实施方案中布线迹线。
然而，相反地，虽然整个区域702有助于吸收例如凸块焊盘104的常规焊盘中的应力，但是在本发明的示范性实施方案中，只有迹线所占据的区域702的部分才吸收应力以增强布线层208。为了增大区域702中的应力吸收，示范性实施方案可增大导电迹线覆盖的区域702的百分比。
在示范性布线层208中，应力缓冲区（应力吸收区域）不必限于区域702。相反，它可能比区域702小或大。因此，应力缓冲区域可由第一圆限定区域224’界定，第一圆限定区域224’包括凸块焊盘204和其中包括的迹线的部分。如图7示出，圆限定区域224’的尺寸可小于凸块焊盘104。然而，比焊盘104大的应力缓冲区可通过使用围绕凸块焊盘204的更多的迹线来形成，以增强布线层208。这通过图7示出的第二圆限定区域224”来举例说明。如可理解地，增大被凸块焊盘和其中包括的导电迹线的部分覆盖的给定圆限定区域（例如，区域224”）的表面区域的比例，向靠近所包括的凸块焊盘的布线层208提供了更大的机械增强。在一些实施方案中，被导电迹线覆盖的区域702的比例可在约30%和100%之间。
图8示出示范性半导体管芯200的示范性布线层208的平面图。布线层208包括集成电路的原始I/O焊盘214A、214B、214C（个别或统称为I/O焊盘214）和适于进行倒装芯片焊料凸块形成的重新分布的示范性凸块焊盘204A、204B、204C、204D（个别或统称为凸块焊盘204）。导电迹线222D、222E、222F、222G、222H、222I、222J、222K、222L（个别或统称为导电迹线222）用以把I/O焊盘与对应的凸块焊盘（未全部示出）互连。
在图1中，在凸块焊盘104A和104D之间只布线了五个信号迹线。然而，在图8中，在凸块焊盘204A和凸块焊盘204D之间可容纳至少十个信号、接地和功率迹线(即，222D、222E、222F、222G、222H、222I、222J、222K、222L和222M）。如可观察到，图8的布线层在凸块焊盘之间包括更多的信号迹线，而不会使隔开相邻迹线的间隔变窄，这样可促进改善的信号密度。
在图8中，布线层208的所述导电图案包括第一导电迹线222A’和第二导电迹线222B’，第一导电迹线222A’把附接第一焊料凸块的第一凸块焊盘204A互连到I/O焊盘214A，第二导电迹线222B’把附接第二焊料凸块的第二凸块焊盘204B互连到第二I/O焊盘214B。I/O焊盘214可具有任何形状且可放置在管芯200上任何位置。
图9也示出示范性半导体管芯200的示范性布线层208的平面图，其中示出常规假定凸块焊盘104A’、104B’、104C’、104D’的轮廓（个别或统称为焊盘轮廓104’）以示出示范性布线层208所达到的相对尺寸和布线密度。
如所示出，导电迹线222B’、222C’的部分（例如，焊盘轮廓104A’中的部分）至少部分围绕凸块焊盘204A或靠近凸块焊盘204A通过。接近凸块焊盘204A的迹线222A’、222B’、222C’的部分因此吸收来自附接到凸块焊盘204A的焊料凸块的应力。所述设置有效地形成“虚拟焊盘”或包围焊盘204A的限定区域（例如，轮廓104A’或其中的内切圆），以保护靠近焊盘204A的介电层免受热和机械应力所造成的潜在损坏。
图8-9也示出另外的焊盘204C和204B，每个都与个别的各自的迹线互连。如所示出，虽然导电迹线222B’、222C’不直接互连凸块焊盘204A，但是导电迹线222B’、222C’的部分有助于保护靠近焊盘204A的介电层。
有利地，制造半导体管芯200不需要昂贵的另外的步骤。例如，一种制造例如管芯200的半导体管芯的方法可包括准备具有包括在活性表面上形成的一组I/O焊盘的至少一个集成电路（IC）的晶片。例如包括介电材料层的布线层208的布线层可在晶片上形成。布线层上面可形成把第一焊盘（例如，凸块焊盘204）与第一I/O焊盘互连的至少一个导电迹线。布线层也可包括第二凸块焊盘、第二I/O焊盘和把凸块焊盘与第二I/O焊盘互连的第二导电迹线。可形成第二导电迹线（例如，迹线222B’），以靠近第一凸块焊盘（例如，图8中的凸块焊盘204A）通过，且所述第二导电迹线也可部分围绕第一凸块焊盘。第二导电迹线因此可缓冲来自附接到第一凸块焊盘的焊料凸块的应力，以保护靠近焊料凸块的下面的介电材料免受应力影响。
也可形成钝化层。所述制造方法还可包括在钝化层上形成开口以暴露凸块焊盘，和在每个凸块焊盘上形成凸块下金属化（UBM）焊盘以安装、沉积焊料凸块或把焊料凸块附接到凸块焊盘上。
所述方法还可包括使用倒装芯片附接把管芯200附接到载体基板上。倒装芯片附接是本领域技术人员已知的，且在例如NewYork:McGrawHill中Harper，CharlesA.的2005年的ElectronicPackagingandInterconnection第四版中讨论，所述文献以引用的方式并入本文。
图10到12示出本发明的另一示范性实施方案的又一半导体管芯300的部分。如所示出，半导体管芯300包括布线层308，布线层308包括多个导电迹线322a、322b......322g（个别或统称为导电迹线322）。布线层308可包括在下金属层304顶部形成的介电质306。UBM302允许通过焊料凸块312（图10）把管芯300附接到基板等。像导电迹线222（图4-9）的每个导电迹线322a、322b、322c......322g可在半导体管芯300的IC上发出I/O焊盘314a、314b......314g（图12），并从IC携带信号、功率等且向IC携带信号、功率等。然而，与图4-9的实施方案中不同，导电迹线322d充当UBM302的凸块焊盘。这样，UBM302可直接从充当或代替UBM302的常规凸块焊盘（如凸块焊盘104）的多个导电迹线中的一个上的接触点延伸。迹线322d可延伸超出UBM302并延伸到另一UBM（未示出），或其它终止点。
特别说来，如图10示出，UBM302可通过延伸穿过介电质306的金属化通孔310来与迹线322电互连。又如示出，一般平行于迹线322d延伸的多个其它迹线322在UBM302下方延伸以向UBM322和布线层308提供足够的结构增强，如参看图11最好地理解。充当凸块焊盘的迹线322d不需要比剩余迹线322大，且不需要在凸块下金属化302下方物理终止，但可替代性地从I/O焊盘314d延伸到相关UBM的接触点，且潜在性地延伸出去。这样，像迹线322d的信号迹线可用以向如UBM302的若干UBM提供信号、功率等。同样，因为迹线322不占据另外的空间，所以新空闲的空间允许迹线322和可能更宽的迹线之间的间隔增大，以减小串扰并增大迹线322携带的功率。如应理解，增强迹线322不需要平行，但或者可在像UBM302的UBM下方延伸，且在几何结构上设置成增强靠近UBM302的介电质306。
有利地，如图8-11示出的迹线222/322的布线图允许增大布线密度，同时仍吸收来自焊料凸块的否则将负面影响用较小方块使用的增大脆性介电材料的一些应力。充当凸块焊盘的迹线322上的较小凸块焊盘204或接触点允许比起常规较大凸块焊盘具有更多信号、功率/接地布线迹线222/322。另外，较小凸块焊盘204/迹线322的电容性将不足以进行信号传输。
功率和接地迹线的有效电阻可通过增大有利地产生更有效功率使用的布线层上的功率/接地迹线的数量来减小。另外，本发明的实施方案的示范性半导体方块允许凸块焊盘形状不需要符合在凸块焊盘上形成的UBM焊盘的形状。
方便地，所述实施方案可避免与在UBM和布线层之间添加聚酰亚胺缓冲相关的成本。
如可理解，图4-5中为了清楚起见只示出了一个介电材料层220和一个对应的导电迹线层222。然而，本领域技术人员应理解，在其它实施方案中，可设置彼此由布线层208中的介电材料层隔离的若干迹线层。
在其它实施方案中，管芯200的布线层208中只有一些凸块焊盘可由靠近凸块焊盘通过的导电迹线围绕。存在不必具有靠近各自的UBM通过的导电迹线的一些其它的凸块焊盘以机械增强布线层208。除了比对应的UBM的上表面小的示范性凸块焊盘204，也可存在比对应的UBM大的其它凸块焊盘（像凸块焊盘104）。
本发明的实施方案可用于各种应用中，包括制造DRAM、SRAM、EEPROM、快闪存储器、图形处理器、通用处理器、DSP和各种标准模拟、数字和混合信号电路封装。
当然，上述实施方案旨在仅为说明性而绝不是限制性的。执行本发明的所述实施方案允许对形式、部件的设置、操作的细节和顺序的许多修改。相反，本发明旨在包括如权利要求书所限定的范围中的所有所述修改。

Claims (22)

1.一种半导体管芯，包括：
i）在一片半导体晶片的一个表面上形成的集成电路；
ii）与所述集成电路互连的多个输入/输出（I/O）焊盘；
iii）包括以下的布线层：在所述一个表面上形成的介电层；和在所述介电层上形成的多个导电迹线，所述导电迹线中的每个从所述I/O焊盘中的一个延伸；
iv）多个凸块下金属化（UBM），各自包括用于附接多个焊料凸块的各自的焊料凸块的顶面；
其中所述导电迹线中的至少一个通过所述UBM中的一个UBM的顶面下面，且在几何结构上设置成机械增强靠近所述UBM中的所述一个UBM的所述布线层。
2.如权利要求1所述的半导体管芯，其中所述布线层包括多个导电迹线层，所述导电迹线层中的每个由至少一个介电层与所述多个导电迹线层中的另一导电迹线层隔开。
3.如权利要求1所述的半导体管芯，其中所述导电迹线中的所述至少一些吸收来自所述焊料凸块中的对应的焊料凸块的应力，所述应力由所述半导体管芯和所述焊料凸块附接到的基板的热膨胀系数的不匹配产生。
4.如权利要求1所述的半导体管芯，其中所述导电迹线中的所述至少一些包括功率迹线、接地迹线和信号迹线中的一个。
5.如权利要求1所述的半导体管芯，其中定义为半径Rarea大于或等于对应的UBM的顶面的平均半径RUBM的圆形区域的包括凸块焊盘的圆限定区域使不包括所述包括的凸块焊盘的它30%到100%的区域被所述导电迹线的部分覆盖。
6.如权利要求1所述的半导体管芯，其中所述凸块焊盘中的每个凸块焊盘内切圆的直径约为50μm。
7.如权利要求6所述的半导体管芯，其中所述UBM中的每个UBM的顶面的内切圆直径约为80μm，且所述UBM中的所述每个UBM的底部接触表面的内切圆直径约为46μm。
8.如权利要求7所述的半导体管芯，其中所述导电迹线中的每个的宽度约为12μm。
9.如权利要求1所述的半导体管芯，其中所述管芯使用倒装芯片连接附接到所述基板。
10.如权利要求1所述的半导体管芯，其中所述封装是以下之一：DRAM、SRAM、EEPROM、快闪存储器、图形处理器、通用处理器和DSP。
11.一种半导体管芯，包括：
i）在一个表面上形成的至少一个集成电路，和连接到所述至少一个集成电路的多个输入输出（I/O）焊盘；
ii）包括以下的布线层：在所述管芯的所述表面上形成的介电层，和在所述介电层上形成的多个导电迹线，所述导电迹线中的每个在所述I/O焊盘中的一个I/O焊盘与所述介电层上形成的多个凸块焊盘中的一个凸块焊盘之间延伸；和
iii）在所述凸块焊盘上形成的多个焊料凸块，用于把所述集成电路与基板电互连；
其中所述凸块焊盘中的至少一个包括在半径大于或等于在所述每个凸块焊盘上形成的对应的凸块下金属化（UBM）的顶面的平均半径的圆限定区域中，所述导电迹线中的至少一些通过所述圆限定区域而不接触包括的凸块焊盘，以机械增强靠近所述包括的凸块焊盘的所述布线层。
12.如权利要求11所述的半导体管芯，其中圆限定区域中包括的所述至少一个凸块焊盘的形状是六角形、八角形和多边形中的一个。
13.如权利要求11所述的半导体管芯，还包括在所述UBM顶部形成的焊料凸块。
14.如权利要求13所述的半导体管芯，其中所述焊料凸块中的一个焊料凸块附接到所述UBM的所述顶面，且比所述顶面小的所述UBM的底部接触表面与所述至少一个凸块焊盘物理通信。
15.一种用于半导体管芯的布线层，所述布线层包括：
i）使用凸块下金属化（UBM）来附接焊料凸块的多个凸块焊盘；
ii）把所述凸块焊盘中的对应的凸块焊盘与在管芯上形成的集成电路的多个输入/输出（I/O）焊盘互连的多个导电迹线；
所述导电迹线中的至少一个靠近所述凸块焊盘中的一个凸块焊盘通过，以机械增强靠近所述UBM中的对应的UBM的所述布线层。
16.如权利要求15所述的布线层，其中所述凸块焊盘中的每个的形状是多边形、圆形和矩形中的一个。
17.如权利要求15所述的布线层，其中所述凸块焊盘中的至少一个形成为相关UBM的所述迹线中的一个迹线上的接触点。
18.如权利要求15所述的布线层，其中所述多个导电迹线中的每个包括以下至少一个：铜、铝、金、铅、锡、银、铋、锑、锌、镍、锆、镁、铟、碲和镓。
19.如权利要求15所述的布线层，还包括介电层，其中所述多个导电迹线在所述介电层上形成。
20.一种半导体管芯，包括如权利要求15所述的布线层。
21.一种制造半导体管芯以使管芯具有与多个输入/输出（I/O）焊盘互连的集成电路（IC）的方法，所述方法包括：
i）在介电层上形成多个导电迹线，所述迹线把多个凸块下金属化（UBM）接触点中的对应的接触点与所述I/O焊盘互连，所述导电迹线中的至少一个靠近所述接触点中的一个接触点通过，以增强靠近所述UBM接触点中的所述接触点的所述介电层；和
ii）把多个所述焊料凸块附接到与所述UBM中的对应的UBM互连的UBM。
22.如权利要求21所述的方法，还包括在所述布线层上形成钝化层。
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