CN103548146A

CN103548146A - Dual active layers for semiconductor devices and methods of manufacturing the same

Info

Publication number: CN103548146A
Application number: CN201280017495.8A
Authority: CN
Inventors: M.马尔斯
Original assignee: University of Arizona
Current assignee: University of Arizona
Priority date: 2011-04-07
Filing date: 2012-04-05
Publication date: 2014-01-29
Also published as: KR20130138328A; SG194073A1; JP2014513425A; EP2695195A2; EP2695195A4; WO2012138903A2; WO2012138903A3

Abstract

Some embodiments include dual active layers for semiconductor devices. Other embodiments of related devices and methods are also disclosed.

Description

Two active layers and manufacture method thereof for semiconductor device

About the research of federal funding or the statement of exploitation

U.S. government has complete license in the present invention, and limited in the situation that, requires reasonable terms that patentee provides according to the clause of Grant/Contract NO W911NF-04-2-0005 of AUS research laboratory (ARL) for other people provide the right of license.

The cross reference of related application

The application requires the interests of U.S. Provisional Application that on April 7th, 2011 is submitted to number 61/472,992.U.S. Provisional Application number 61/472,992 is all combined in this with it by reference.

The part continuation application of the application or the PCT application number PCT/US10/36569 submitting on May 28th, 2010.PCT application number PCT/US10/36569 requires the U.S. Provisional Application submitted on May 29th, 2009 number 61/182,464 and the interests of the U.S. Provisional Application submitted on July 30th, 2009 number 61/230,051.Simultaneously, PCT application number PCT/US10/36569 is the part continuation application of following application: the PCT application number PCT/US09/66114 (a) submitting on November 30th, 2009, it requires the priority of the U.S. Provisional Application submitted on December 2nd, 2008 number 61/119,303; (b) the PCT application number PCT/US09/66111 submitting on November 30th, 2009, it requires the priority of the U.S. Provisional Application submitted on December 2nd, 2008 number 61/119,248; And the priority of the PCT application number PCT/US09/66259 (c) submitting on December 1st, 2009.PCT application number PCT/US09/66259 requires the interests of following application: the U.S. Provisional Application of (i) submitting on December 2nd, 2008 number 61/119,217; (ii) U.S. Provisional Application number 61/182,464; And (iii) U.S. Provisional Application number 61/230,051.

PCT application number PCT/US10/36569, U.S. Provisional Application number 61/182,464, U.S. Provisional Application number 61/230,051, PCT application number PCT/US09/66114, U.S. Provisional Application number 61/119,303, PCT application number PCT/US09/66111, U.S. Provisional Application number 61/119,248, PCT application number PCT/US09/66259 and U.S. Provisional Application number 61/119,217 is all combined in this with it by reference.

Technical field

Present invention relates in general to semiconductor device, and relate more specifically to have semiconductor device and the manufacture method thereof of two active layers.

Background technology

Thin-film transistor is usually used in, for various Display Technique power supplies, comprising liquid crystal display, electrophoretic display device (EPD), organic light emitting diode display etc.Many thin-film transistors use amorphous silicon as active layer, but because low mobility and the low ON/OFF of amorphous silicon may be disadvantageous than using amorphous silicon.Equally, when manufacturing flexible display, the high-temperature process temperature of amorphous silicon may be also disadvantageous.

Therefore, need or potential interests be the system and method for the manufacture of it, these system and methods allow to improve mobility and the ON/OFF ratio of active layer when being permitted diminishbb Temperature Treatment.

Accompanying drawing explanation

For the ease of embodiments of the invention are described further, following accompanying drawing is provided, wherein:

Fig. 1 has shown a kind of example that the method for semiconductor device is provided according to first embodiment;

Fig. 2 has shown the example of the step that a flexible substrate is provided according to this first embodiment;

Fig. 3 has shown the example of a process preparing this flexible substrate according to this first embodiment;

Fig. 4 has shown the top view of an example of this flexible substrate according to this first embodiment;

Fig. 5 has shown in the partial cross section view that the flexible substrate of Fig. 4 is attached to the example of a rear flexible substrate assembly in a protection template according to this first embodiment;

Fig. 6 has shown the partial cross section view of an example of the flexible substrate assembly of Fig. 5 after a carrier substrates is connected to this flexible substrate assembly according to this first embodiment;

Fig. 7 has shown the example of a process of the flexible substrate assembly of processing Fig. 5 according to this first embodiment;

Fig. 8 has shown the cross-sectional view of an example of the flexible substrate assembly of Fig. 5 after this flexible substrate assembly of cutting according to this first embodiment;

Fig. 9 has shown the cross-sectional view of an example of the flexible substrate assembly of Fig. 5 after removing an alignment contact pin according to this first embodiment;

Figure 10 has shown the cross-sectional view of an example of the flexible substrate assembly of Fig. 5 remove a kind of protective material from this flexible substrate assembly after according to this first embodiment;

Figure 11 has shown the example of the step that a plurality of semiconductor elements are provided according to this first embodiment;

Figure 12 has shown the example of the process that one or more the first semiconductor elements are provided according to this first embodiment;

Figure 13 has shown that according to this first embodiment the device of a semiconductor device after a gate metal layer is provided builds the cross-sectional view of an example in district;

Figure 14 has shown that according to this first embodiment the gate contacts of a semiconductor device after this gate metal layer is provided builds the cross-sectional view of an example in district;

Figure 15 has shown that according to this first embodiment the device of the semiconductor device of Figure 13 after an active stack layer is provided builds the cross-sectional view of an example in district;

Figure 16 has shown that according to this first embodiment the gate contacts of the semiconductor device of Figure 14 after this active stack layer is provided builds the cross-sectional view of an example in district;

Figure 17 has shown that according to this first embodiment the device of the semiconductor device of Figure 13 after a mesa passivation floor is provided builds the cross-sectional view of an example in district;

Figure 18 has shown that according to this first embodiment the gate contacts of the semiconductor device of Figure 14 after this mesa passivation floor is provided builds the cross-sectional view of an example in district;

Figure 19 has shown that according to this first embodiment the device of the semiconductor device of Figure 13 after carrying out the etching of one or more rear table top passivation layer builds the cross-sectional view of an example in district;

Figure 20 has shown that according to this first embodiment the gate contacts of the semiconductor device of Figure 14 after carrying out the etching of one or more rear table top passivation layer builds the cross-sectional view of an example in district;

Figure 21 has shown that according to this first embodiment the device of the semiconductor device of Figure 13 after one or more contact elements are provided builds the cross-sectional view of an example in district;

Figure 22 has shown that according to this first embodiment the gate contacts of the semiconductor device of Figure 14 after one or more contact elements are provided builds the cross-sectional view of an example in district;

Figure 23 has shown the example of the process that a kind of the first dielectric material is provided according to this first embodiment;

Figure 24 has shown that according to this first embodiment the device of the semiconductor device of Figure 13 after a kind of base dielectric of etching, a kind of the first dielectric material and a kind of the second dielectric material builds the cross-sectional view of an example in district;

Figure 25 has shown that according to this first embodiment the device of the semiconductor device of Figure 13 after second metal level and an ITO floor are provided builds the cross-sectional view of an example in district;

Figure 26 has shown that according to this first embodiment the device of the semiconductor device of Figure 13 after a silicon nitride layer is provided builds the cross-sectional view of an example in district;

Figure 27 has shown a kind of by the example of the method for flexible substrate complanation according to second embodiment;

Figure 28 has shown according to the cross-sectional view of the semiconductor device of the method for Figure 27 example according to this second embodiment;

Figure 29 has shown the top view of a part for a semiconductor device according to this first embodiment;

Figure 30 has shown a kind of curve chart of spin rate of a substrate of thickness VS of dielectric material;

Figure 31 has shown a kind of illustrative methods of manufacturing semiconductor device according to an embodiment;

Figure 32 has been provided by the cross-sectional view that provides the device of an example semiconductor device after a gate metal layer to build district on this substrate;

Figure 33 has been provided by the cross-sectional view that provides the gate contacts of an example semiconductor device after a gate metal layer to build district on this substrate;

Figure 34 is a flow chart, has shown the step that transistor active layer is provided on this gate metal layer according to the embodiment of Figure 31;

Figure 35 has been provided by the cross-sectional view that provides the device of the semiconductor device of Figure 32 after an etching stopping layer to build an example in district on this transistor active layer;

Figure 36 has been provided by the cross-sectional view that provides the gate contacts of the semiconductor device of Figure 33 after an etching stopping layer to build an example in district on this transistor active layer;

Figure 37 shown on this etching stopping layer and/or above provide the device of the semiconductor device of Figure 32 after a mesa passivation floor to build the cross-sectional view of an example in district;

Figure 38 shown on this etching stopping layer and/or above provide the gate contacts of the semiconductor device of Figure 33 after a mesa passivation floor to build the cross-sectional view of an example in district;

Figure 39 has shown that the device of the semiconductor device of Figure 32 after having carried out the etching of one or more rear table top passivation layer builds the cross-sectional view of an example in district;

Figure 40 has shown that the gate contacts of the semiconductor device of Figure 33 after having carried out the etching of one or more rear table top passivation layer builds the cross-sectional view of an example in district;

Figure 41 shown on this transistor active layer, this first active layer and/or this second active layer, provide a source/drain contact floor after the device of semiconductor device of Figure 32 build the cross-sectional view of an example in district;

Figure 42 shown on this transistor active layer, this first active layer and/or this second active layer, provide a source/drain contact floor after the gate contacts of semiconductor device of Figure 33 build the cross-sectional view of an example in district;

Figure 43 has shown that the device of the semiconductor device of Figure 32 after carrying out one or more additional steps builds the cross-sectional view of an example in district;

Figure 44 has shown that according to an embodiment device of the semiconductor device of Figure 32 after one or more semiconductor elements are provided builds the cross-sectional view of an example in district;

Figure 45 has shown that according to an embodiment who is different from the embodiment of Figure 44 the device of the semiconductor device of Figure 32 after one or more semiconductor elements are provided builds the cross-sectional view of an example in district;

Figure 46 has shown the top view of a part for an example semiconductor device;

Figure 47 according to an embodiment, shown on this gate metal layer and/or above first active layer is provided and on this first active layer and/or above provide the device of the semiconductor device of Figure 32 after second active layer to build the cross-sectional view of an example in district;

Figure 48 is a flow chart, has shown the step that a source/drain contact layer is provided on this transistor active layer, this first active layer and/or this second active layer according to the embodiment of Fig. 1; And

Figure 49 is a flow chart, has shown the step that a gate metal layer is provided on this substrate according to the embodiment of Fig. 1.

Embodiment

For the simplification shown and clear, accompanying drawing has been shown overall make, and the description of well-known feature and technology and details can omit, to avoid making the present invention unnecessarily fuzzy.In addition, the element in accompanying drawing needn't be drawn according to size.For example, the size of some elements in accompanying drawing can be exaggerated with respect to other elements, to help improve the understanding to embodiments of the invention.Same reference numbers in different accompanying drawings represents identical element.

The terms (if any) such as " first " in specification and claim, " second ", " the 3rd ", " the 4th ", for element like region class, do not represent specific sequence or time sequencing.The term that should understand such use is interchangeable so that embodiment described here for example can be by those or the sequential working otherwise described at this that are different from description suitable in the situation that.In addition, term " comprise " and " having " with and any version be intended to cover comprising of nonexcludability, to comprise that step, method, system, object, device or the equipment of series of elements needn't be limited to those elements, but can comprise and clearly not listing or such other intrinsic elements of step, method, system, project, device or equipment.

Term in specification and claim " left side ", " right side ", 'fornt', 'back', " top ", " bottom ", " on ", D score etc. (if any) needn't describe permanent relative position for the object of describing.The term that should understand such use is interchangeable suitable in the situation that, so that embodiment described here for example can be different from those or other direction work of otherwise describing at this of description.

Term " connection " etc. should extensively be understood and refer to electrically, mechanically and/or otherwise by two or more elements or signal connection.Two or more electric components can electrically connect but cannot mechanically or otherwise connect; Two or more mechanical organs can mechanical connections but cannot electrically or otherwise be connected; Two or more electric components can mechanical connections but cannot electrically or otherwise be connected.Connection can be to continue length any time, for example permanent or semipermanent or a moment only.

The connection that relates to any electric signal should extensively be understood and comprise to " electrical connection " etc., no matter other types or the combination of electric signal, data-signal and/or electric signal.The mechanical connection of all types should extensively be understood and comprise to " mechanical connection " etc.

Near word " connection " etc., lack word " removedly ", " removable " etc. and do not mean that problematic connection etc. yes or no is removable.

The detailed description of embodiment example

Some embodiment comprise a kind of electronic installation.In a lot of embodiment, this electronic installation can comprise a transistor.This transistor can comprise a transistor active layer on a gate metal layer, this gate metal layer and a source/drain contact layer on this transistor active layer.This source/drain contact layer can comprise first source/drain contact and second source/drain contact.In identical or different embodiment, this transistor active layer can comprise first active layer on this gate metal layer, and wherein this first active layer comprises at least one first metal oxide.In identical or different embodiment, this transistor active layer can comprise second active layer on this first active layer, and wherein this second active layer comprises at least one second metal oxide.In certain embodiments, this first active layer comprises first conductivity, and this second active layer comprises second conductivity, and this first conductivity is greater than this second conductivity.

Various embodiment comprise a kind of semiconductor device.In a lot of embodiment, this semiconductor device comprises: a source/drain contact layer on a gate metal layer, a gate blocks layer in this gate metal layer, a transistor active layer on this gate blocks layer, an etching stopping layer on this transistor active layer, a mesa passivation layer on this etching stopping layer, this mesa passivation layer and this transistor active layer on the ,Gai barrier layer, a barrier layer on substrate, this substrate.In identical or different embodiment, this transistor active layer comprises first active layer in this gate metal layer, and wherein this first active layer comprises at least one first metal oxide.In identical or different embodiment, this transistor active layer comprises second active layer, this second active layer this first active layer and between this first active layer and this etching stopping layer, wherein this second active layer comprises at least one second metal oxide.In certain embodiments, this first active layer comprises first conductivity, and this second active layer comprises second conductivity, and this first conductivity is greater than this second conductivity.

Further embodiment comprises a kind of method of manufacturing semiconductor device.The method comprises: a substrate is provided; A gate metal layer is provided on this substrate; First active layer is provided on this gate metal layer, and wherein this first active layer comprises at least one first metal oxide and first conductivity; Second active layer is provided on this first active layer, and wherein this second active layer comprises at least one second metal oxide and second conductivity that is less than this first conductivity; And on this second active layer, provide a source/drain contact layer.

Term used herein " bending " refers to around the curvature of the substrate of a central plane, this central plane and end face and bottom surface or the major surfaces in parallel of this substrate.Term used herein " warpage " refers to that the surface of a substrate is with respect to the linear displacement of a z axle, and the surface of this substrate is vertical with bottom surface or the first type surface of this substrate with end face.Term used herein " distortion " refers in the face of a substrate (that is, x-y face, itself and end face and bottom surface or the major surfaces in parallel of this substrate) displacement.For example, distortion can be included in contraction and/or the expansion in the x-y of this substrate plane in the x-y plane of a substrate.

Term " CTE matching materials " refers to the have thermal coefficient of expansion material of (CTE) as used herein, and this thermal coefficient of expansion is different from the CTE of reference material, than few about percent 20(% of the CTE of reference material).Preferably, these CTE less about 10%, 5%, 3% or 1%.As used herein, " polishing " can refer to overlap joint surface of polishing or only overlap this surface.

Forward accompanying drawing to, Fig. 1 has shown a kind of example that the method 100 of semiconductor device is provided according to first embodiment.In identical or different embodiment, method 100 can be considered to be in a kind of method that thin-film transistor is provided in flexible substrate.Method 100 is only exemplary, the embodiment that is not limited to show at this.Method 100 can be applied in not this specifically describe or the many different embodiment or example that describe in.

Method 100 comprises the step 110 that a flexible substrate is provided.Fig. 2 is a flow chart, according to this first embodiment, has shown the step 110 that a flexible substrate is provided.

Step 110 comprises a process 211 supplying with a flexible substrate.Term " flexible substrate " means the free-standing substrate that comprises flexible material as used herein, easily adaptive its shape of this flexible material.In certain embodiments, process 211 can comprise a flexible substrate with low elastic modulus of supply.For example, low elastic modulus can be considered to be less than the modulus of elasticity of about five gigapascals (GPa).

In a lot of examples, this flexible substrate is a plastic.For example, flexible substrate can comprise Polyethylene Naphthalate (PEN), PETG (PET), polyether sulfone (PES), polyimides, Merlon, cyclic olefine copolymer or liquid crystal polymer.

In a lot of examples, this flexible substrate can be included in the coating on one or more sides of this flexible substrate.This coating can improve the marresistance of this flexible substrate and/or contribute to prevent lip-deep degasification or the oligomer crystallization at this substrate.And complanation is carried out in the side of the flexible substrate that this coating can be positioned at it.This coating can also help to reduce distortion.In some instances, this coating is only positioned at the side of this flexible substrate, and this electric device will be manufactured on this side.In other examples, this coating is in the both sides of this flexible substrate.In various embodiments, can before carrying out complanation, provide this flexible substrate.For example, this flexible substrate can be that the Supreme Being people of Du Pont film (DuPont Teijin Films) from Tokyo is with " complanation

q65 " the PEN substrate sold of trade (brand) name.In other embodiments, can after being provided, a flexible substrate carry out complanation to it.For example, method 2700(Figure 27) provide a kind of method of substrate being carried out to complanation.

The thickness of this flexible substrate or plastic can be at approximately 25 microns (μ m) to the scope of approximately 300 μ m.In identical or different embodiment, the thickness of this flexibility or plastic can be at approximately 100 μ m to the scope of approximately 200 μ m.

In some instances, can provide this flexible substrate by cutting a slice plastic with paper knife or ceramic scissors from a volume plastic material.In various examples, cut after this plastic, the thin slice of cutting is blown clean by nitrogen gun.In some embodiment of step 110, the one or both of the process of this cutting and air blowing can be a part for process 212 as described below, rather than a part for process 211.

The step 110 of Fig. 2 proceeds to prepare the process 212 of this flexible substrate.Fig. 3 is a flow chart, has shown the process 212 of preparing this flexible substrate according to this first embodiment.

The process 212 of Fig. 2 can comprise the activity 330 of toasting this flexible substrate.Toast this flexible substrate can help to discharge oligomer and may be afterwards at method 100(Fig. 1) process in other chemicals in this flexible substrate caught on a filter.

In some instances, can use vacuum bakeout process to toast this flexible substrate.For example, temperature in the baking oven that, comprises this flexible substrate can rise to approximately 160 degrees Celsius (° C) to approximately 200 ° of C in about two to three hours.Can to approximately 200 ° of C and at approximately one millitorr (mTorr), to the pressure of approximately 10 millitorrs, toast this flexible substrate one hour at approximately 160 ° of C.Then, the temperature in this baking oven can be reduced to approximately 90 ° of C between approximately 115 ° of C, and this flexible substrate can also be toasted approximately eight hours again.Can also use other bake process.After bake process completes, any residue that can this flexible substrate of wiped clean or baking chemicals out.

Subsequently, the process 212 of Fig. 3 comprises the activity 331 that a protection template is provided.The guidance that this protection template both can be used as this flexible substrate of placement also can be used as the roller of this flexible substrate and various treatment facilities and/or a protective layer between processing mechanism.In some instances, this protection template is a thin slice of polyester film or any inexpensive plastic.

This protection template can be that 50 μ m to 15mm are thick, and is cut into about 0.5m(rice) to the length of about 1.5m.In various embodiments, the part as movable 331, by this protection template folded in half and for example, through roller (, hot-roll lamination machine), folds to help locking this.A part as movable 331, also can be by a trace of carrier substrates on the dorsal part of this screening glass.In addition, this protection template can be toasted approximately five minutes to approximately ten minutes at approximately 90 ° of C to approximately 110 ° of C, to help that this protection template is flattened.

The process 212 of Fig. 3 proceeds a kind of protective material to be applied to the activity 332 at least a portion of a first surface of this flexible substrate.In certain embodiments, a kind of protective material can be applied at least a portion of planar surface of this flexible substrate.In some instances, this protective material is not applied in a part for this flexible substrate.

This protective material has prevented the planar surface of cut and this flexible substrate of adhesive coverage, and has therefore reduced defect.In some instances, blue low adhesive tape (for example,, from semiconductor equipment company (Semiconductor Equipment Corporation), Part No. 18133-7.50) or polyester film can be used as protective material.This protective material is can approximately 25 μ m thick to approximately 100 μ m.For example, this protective material can be thick for approximately 70 μ m.In some instances, by this protective material being rolled onto with roller on the planar surface of this flexible substrate, apply this protective material, to remove the bubble between this protective material and this flexible substrate.

Subsequently, the process 212 of Fig. 3 comprises the activity 333 that this flexible substrate and protective material is cut into wafer shape.Die cut template can be used for this wafer shape die mould in this flexible substrate (if there is complanation side, in this complanation side direction) and/or this protective material.In one embodiment, this die cut template is used in this protective material and this flexible substrate, create a temporary or permanent impression at one time.

If the die mould of this die cut template cuts completely through this flexible substrate, this flexible substrate is scrapped, because this crush-cutting can cause the crack that propagates into whole flexible substrate in a coating in this flexible substrate.After using this die mould that this wafer shape is set off in this flexible substrate and/or this protective material, this flexible substrate and this protective material are cut off each other simultaneously.About one millimeter of the impression outside of making in this die cut template in some instances, is cut this flexible substrate and protective material with ceramic scissors.

In some instances, this flexible substrate comprises the contact pin that this wafer shape from this flexible substrate and this protective material is extended.When this contact pin can be used for advancing in the process 217 at Fig. 2 through a laminating machine, help is alignd this flexible substrate with a carrier substrates.Fig. 4 has shown the top view of a flexible substrate 450 according to first embodiment.Flexible substrate 450 can comprise a main body 452 and contact pin 451.In a lot of examples, main body 452 can have one round-shaped.Although do not show in Fig. 4, be positioned at the contact pin that this protective material on flexible substrate 450 also comprises an analogous shape.In one embodiment, this contact pin is not a part for this die cut template and is cut into this flexible substrate and this protective material by free-hand or free style.

Referring back to Fig. 3, the process 212 of Fig. 3 is proceeded the activity 334 of clean this flexible substrate.In some instances, second of this flexible substrate or non-flattening side (that is a side that, there is no protective material) by dry wipe to remove any oligomer, other chemicals or particle.Afterwards, by nitrogen gun, the complanation with the flexible substrate of protective material is blown side clean.In other examples, both sides are all by dry wipe and/or blow clean.

Then, the process 212 of Fig. 3 comprises the activity 335 that this flexible substrate is alignd with a protection template.In some instances, the flexible substrate that has the contact pin of wafer shape band is alignd with the trace of the carrier substrates that draws or make in this protection template in movable 331.The trace of this carrier substrates is conventionally slightly large than the wafer shape of this flexible substrate.

Subsequently, the process 212 of Fig. 3 comprises the activity 336 that this flexible substrate is connected to this protection template.In certain embodiments, by a part for the contact pin of this flexible substrate is attached in this protection template this flexible substrate is attached in this protection template.For example, a slice two-sided tape can be connected to the contact pin of this flexible substrate this protection template.In some instances, a part for this protective material is peeled off and is removed from this contact pin, and this two-sided tape is connected to the part that the contact pin of this flexible substrate exposes.In some instances, can this part of this protective material be peeled off with tweezers, and can from this protection template, cut off with ceramic scissors.In other examples, in the activity 332 of Fig. 3, this protective material can be applied to this two-sided tape and will be attached to that part of this contact pin, so there is no need to peel off and remove a part for this protective material.

This flexible substrate is connected to after this protective finish, and then this protection template is folded on this flexible substrate.Fig. 5 has shown in the Yi Ge partial cross section view that flexible substrate 450 is attached to a rear flexible substrate assembly 540 in a protection template 555 according to this first embodiment.In this example, adhesive tape 556 is connected to flexible substrate 450 and protection template 555.As previously mentioned, a kind of protective material 553 is connected to flexible substrate 450.

In some instances, only a side of this flexible substrate is attached in this protection template.In other examples, the both sides of this flexible substrate are all attached in this protection template.

Then, the process 212 of Fig. 3 comprises this flexible substrate, this protective material and this protection template is carried out to the activity 337 of lamination.This flexible substrate and this protective material are between two folded parts of this protection template.Can to this flexible substrate, this protective material and this protection template, carry out lamination with hot-roll lamination machine, to remove between this protective material and this protection template and to also have the bubble between this protective material and this flexible substrate.In some instances, this flexible substrate and this protection template (are for example placed on a guide plate guide plate) on and be fed in this hot-roll lamination machine.For example, can first this contact pin of this flexible substrate and this protective material be fed in this laminating machine.At about 120kPa(kPa) to the pressure of about 160kPa and at approximately 90 ° of C, to the temperature of approximately 110 ° of C, this flexible substrate and this protection template are carried out to lamination.Laminate speed can be one meter to two meters approximately per minute approximately per minute.

After this flexible substrate of lamination and protection template, process 212 completes.Referring back to Fig. 2, the process of a carrier substrates 213 that provides is provided the step 110 of Fig. 2.In a lot of embodiment, this carrier substrates can be wafer or the panel of 6,8,12 or 18 inches.This carrier substrates can be the panel that about 370mm is multiplied by 470mm in certain embodiments.

This carrier substrates can comprise a first surface and a second surface relative with this first surface.In some instances, at least one in this first surface and this second surface is polished.To not being connected to subsequently the surface of this flexible substrate, carrying out polishing and improved the ability that vacuum or air spider are processed this carrier substrates.And, to being connected to subsequently the surface of this flexible substrate, carry out the surperficial topological characteristic that this carrier substrates has been removed in polishing, these topological characteristics may cause the coarse of this flexible substrate assembly on z axle after being connected with this flexible substrate.

In various embodiments, this carrier substrates comprises at least one in following content: aluminium oxide (Al ₂o ₃), the material that matches of the CTE of silicon, low CTE glass, steel, sapphire, borosilicic acid barium, sodium-calcium-silicate, alkali silicate or another kind of and this flexible substrate.The CTE of this carrier substrates should match with the CTE of this flexible substrate.Unmatched CTE can produce pressure between this carrier substrates and this flexible substrate.

For example, this carrier substrates can comprise sapphire, and its thickness is between about 0.7mm and about 1.1mm.This carrier substrates can also comprise 96% aluminium oxide, and its thickness is between about 0.7mm and about 1.1mm.In a different embodiment, the thickness of 96% aluminium oxide is approximately 2.0mm.In another example, this carrier substrates can be monocrystalline silicon piece, and its thickness is 0.65mm at least approximately.In another embodiment again, this carrier substrates comprises stainless steel, and its thickness is 0.5mm at least approximately.In some instances, this carrier substrates is slightly larger than this flexible substrate.

Then, the process of a cross-linked binder 214 that provides is provided the step 110 of Fig. 2.In some instances, cross-linked binder is to be less than approximately 2 * 10-4 holder litre speed degasification per second.In some instances, cross-linked binder is thermal curable and/or UV(ultraviolet) photocuring.

In various embodiments, cross-linked binder is a kind of cross-linked acrylic acid adhesive.In identical or different embodiment, this cross-linked binder is a kind of crosslinked pressure sensitive acrylic adhesive or a kind of crosslinked viscoelastic polymer.In some instances, the CTE of this adhesive compares very large with the CTE of this flexible substrate and this carrier substrates.Yet the CTE of this adhesive is inessential, because this adhesive does not produce any pressure (that is, viscoplasticity) between this flexible substrate and carrier substrates, reason is that this adhesive phase compares with the thickness of this flexible substrate and carrier substrates is so thin.

Subsequently, the step 110 of Fig. 2 is included in the process 215 that deposits cross-linked binder on a first surface of this carrier substrates.In a lot of embodiment, can use at least one execution in following methods on a first surface of this carrier substrates, to deposit cross-linked binder: spin coating, spraying, extrusion coated, preforming lamination, slit extrusion coated, silk screen lamination and silk screen printing.

For example, this carrier substrates can be coated with by cross-linked binder.Can this carrier substrates of spin coating and this cross-linked binder cross-linked binder is distributed on a first surface of this carrier substrates.In certain embodiments, by with about 900rpm(revolutions per minute) to 1100rpm with this carrier substrates of cross-linked binder spin coating approximately 20 seconds to approximately 30 seconds and then with about 3400rpm to about this carrier substrates of 3600rpm use cross-linked binder spin coating approximately 10 seconds to 30 seconds, cross-linked binder is spin-coated in this carrier substrates.In a different embodiment, with about 600rpm to about 700rpm spin coating with the carrier substrates of cross-linked binder to be coated with the surface of this carrier substrates, and then with about 3400rpm to about 3600rpm spin coating to control the thickness of cross-linked binder.

Before spin coating, cross-linked binder can be dripped above a geometric center that is coated onto this carrier substrates.In a different embodiment, can in this carrier substrates spin coating, cross-linked binder be dripped and be coated onto above this carrier substrates.

The thickness of the cross-linked binder after deposition step on this carrier substrates can be between approximately 3 μ m and approximately 15 μ m.In identical or different embodiment, the thickness of the cross-linked binder after deposition step on this carrier substrates can be between approximately 10 μ m and approximately 12 μ m.

The step 110 of Fig. 2 proceeds to toast the process 216 of this cross-linked binder.In certain embodiments, can toast cross-linked binder to remove solvent.For example, can under 80 ° of C, cross-linked binder be toasted 30 minutes and then under 130 ° of C, be toasted 15 minutes.

In other examples, cross-linked binder is not baked.For example, if cross-linked binder does not comprise any solvent, baking is unnecessary.And, if cross-linked binder is very glutinous, even can before this adhesive being deposited in this process 215, reduce stickiness to adding solvent in cross-linked binder.

Then, this carrier substrates can be placed in this protection template.As shown in Figure 6, this flexible substrate has been connected to a part (or half) of this protection template, and can will with this carrier substrates of cross-linked binder, be placed on another part (or half) of this protection template.In some instances, this cross-linked binder is at this moment still in liquid form.Therefore,, before the carrier substrates that is coated with cross-linked binder is connected with this flexible substrate, it flatly can be stored approximately eight to approximately 12 hours.

Then, the step 110 of Fig. 2 comprise when two substrates all protection template two halves between time use cross-linked binder this carrier substrates to be connected to a process 217 of this flexible substrate.This second surface of this flexible substrate can be placed on this first surface of this carrier substrates, wherein this adhesive is between this second surface of this flexible substrate and this first surface of this carrier substrates.

In certain embodiments, by this flexible substrate assembly of lamination between the two halves in this protection template, with by the bubble removal between this carrier substrates and this flexible substrate, use cross-linked binder that this carrier substrates is connected to this flexible substrate.First this flexible substrate of lamination relates to aligns this carrier substrates with this flexible substrate, so that while being laminated, this carrier substrates and this flexible substrate are alignd.Then, can be fed to by a hot-roll lamination machine structure of this alignment, this laminating machine can be the laminating machine identical with the activity 337 of Fig. 3.Can 0.4 to 0.6 meter of this flexible substrate assembly of approximate speed lamination per minute.

And in various embodiments, when lamination, this protective material may adhere in this protection template.Avoid this problem, can before movable 337 and/or movable 332 lamination, between this protection template and this protective material, locate a kind of shielding material.This shielding material can be paraffin paper for example.When ，Cong manufacturer place obtains in one embodiment, this shielding material is connected to this protective material at first.

In identical or different embodiment, can in lamination process, between this carrier substrates and flexible substrate, squeeze out some cross-linked binders, and adhere to the first side or the top of this flexible substrate, specifically because the crosslinked adhesive layer of this carrier substrates and covering on it is a bit larger tham this flexible substrate.Yet the anti-problem here of existence of this protective material occurs.The cross-linked binder that squeezes out and adhere to this protective material (rather than this flexible substrate) top is inessential, because this protective material is removed the most at last and abandons.

Fig. 6 has shown and carrier substrates 651 has been connected to the Yi Ge partial cross section view of the rear flexible substrate assembly 540 of flexible substrate assembly 540 according to this first embodiment.In the present embodiment, a cross-linked binder 652 is connected to a surface 661 of carrier substrates 651 on a surface 662 of flexible substrate 450.Protective material 553 is positioned on a surface 656 of flexible substrate 450.Shielding material 654 is between protective material 553 and protection template 555.Protection template 555 is folding so that protection template 555 is also positioned at 663 belows, a surface of carrier substrates 651.Adhesive tape 556 is connected to protection template 555 contact pin 451 of flexible substrate 450.

Referring back to Fig. 2, step 110 proceeds to process the process 218 of this flexible substrate assembly.Fig. 7 is a flow chart, has shown the process 218 of processing this flexible substrate assembly according to this first embodiment.

The process 218 of Fig. 7 comprises the activity 730 of cutting this flexible substrate assembly.In some instances, with ceramic scissors, cut this protection template and through the alignment contact pin of this flexible substrate between this protection template, but also removal completely of this alignment contact pin.After cutting this flexible substrate assembly, can from this shielding material and this carrier substrates, peel off or otherwise remove this protection template with hand.Fig. 8 has shown a cross-sectional view of this flexible substrate assembly at cutting flexible substrate assembly 540 and after removing this protection template according to this first embodiment.More specifically, in Fig. 8, removed protection template 555(Fig. 5 and Fig. 6) and adhesive tape 556(Fig. 5 and Fig. 6 of flexible substrate 450).

Referring again to Fig. 7, the next one activity of process 218 is the activities 731 of this shielding material of removing with hand.In some instances, this flexible substrate assembly is placed on the edge of a desktop, and wherein this shielding material is in the face of this desktop.For example, when removing (, peeling off) this screen from this flexible substrate assembly, this flexible substrate assembly is removed lentamente.Namely, when this flexible substrate assembly is flatly removed from this desktop, by the edge from this desktop, pull down from this shielding material and can remove this screen.In some instances, if this flexible substrate is not correctly alignd with this carrier substrates between two parties or otherwise after removing this screen, this plastic can slip in this carrier substrates.

Subsequently, the process 218 of Fig. 7 comprises the activity 732 of removing this alignment contact pin from this flexible unit.In some instances, can use ceramic scissors from this flexible substrate, to cut this alignment contact pin.This cutting should complete lentamente, because any movement of this flexible substrate in z direction (with respect to this carrier substrates) all may cause that this flexible substrate is from the layering of this carrier substrates.If generation layering, this flexible substrate assembly can be by lamination again.Fig. 9 has shown a cross-sectional view of flexible substrate assembly 540 after removing this alignment contact pin according to this first embodiment.

Then, the process 218 of Fig. 7 comprises the activity 733 of removing this flexible substrate assembly.In some instances, with clean this flexible substrate assembly of ethane.Can and on this protective material, spray ethane application ethane by this flexible substrate assembly of spin coating.Remove after this protective material, with exposed surface and the edge of this carrier substrates of ethane wiped clean.

The step 218 of Fig. 7 proceeds to solidify the activity 734 of this cross-linked binder.In identical or different embodiment, this cross-linked binder is that UV solidifies.For example, this flexible substrate assembly can be exposed to approximately 15 to 25 seconds of UV light and room temperature to solidify this cross-linked binder.In certain embodiments, can be by about 320nm(nanometer) in the UV optical range of about 390nm with intensity be every square centimeter of about 75mW/cm2(milliwatt) this cross-linked binder of UV photocuring.The Dymax2000-EC UV that can manufacture with the Dymax company in Connecticut, USA TWB city solidifies floodlight and solidifies this cross-linked binder.

In various examples, this cross-linked binder is by hot curing in movable 736 bake process.In some instances, the edge of this cross-linked binder is that UV solidifies, and the remainder of this cross-linked binder is by hot curing in movable 736 bake process.

Subsequently, the process 218 of Fig. 7 comprises the activity 735 of removing this protective material from this flexible substrate assembly.In some instances, use tweezers to remove lentamente this protective material.In the process of removing, this protective material is kept to smooth to avoid this flexible substrate from this carrier substrates higher slice as far as possible.In other examples, this protective material can be discharged by UV light.In these examples, in the process that this protective material exposes at UV light, may lose its viscosity.Figure 10 has shown and will from this flexible substrate assembly, remove this protective material cross-sectional view of flexible substrate assembly 540 afterwards according to this first embodiment.

Then, the process 218 of Fig. 7 comprises the activity 736 of toasting this flexible substrate assembly.Toast this flexible substrate assembly and can help to reduce distortion, bending and the warpage in this flexible substrate.In certain embodiments, baking can also be solidified this adhesive.

In some instances, can use vacuum bakeout process to toast this flexible substrate assembly.For example, temperature in the baking oven that, comprises this flexible substrate assembly can rise to approximately 160 ° of C to approximately 190 ° of C in two to three hours.This flexible substrate assembly can be under 180 ° of C and is toasted approximately 50 minutes to 70 minutes to the pressure of about 10mTorr with about 1mTorr.Then, the temperature in this baking oven can be reduced between about 90 ° of C to 115 ° of C, and this flexible substrate assembly can also toast approximately seven hours to approximately nine hours again.Can also use other bake process.After bake process completes, clean these flexible substrate assemblies are also placed in approximately 90 ° of baking ovens under C to 110 ° of C minimum approximately two hours.

Toast after this flexible substrate assembly, process 218 completes, and therefore step 110 also completes.As described herein, what step 110 and similar step can allow one or more electric components in flexible substrate has zero or at least manufacture of minimum distortion (for example, being about the restriction of the sensitivity of the Azores5200 that the Wilmington Ya Suer company (Azores Corporation of Wilmington) of Massachusetts, United States manufactures).In flexible substrate, manufacture remarkable problem of dtmf distortion DTMF that the art methods of electric component suffers and can cause processing wrong, photoetching alignment error and line/layer defects.

Referring back to Fig. 1, method 100 comprises a step 120 that semiconductor element is provided.Figure 11 is a flow chart, has shown the step 120 that semiconductor element is provided according to this first embodiment.

The process 120 of Figure 11 comprises a process 1112 that one or more the first semiconductor elements are provided.Figure 12 is a flow chart, according to this first embodiment, has shown the process of one or more the first semiconductor elements 1112 that provides.

Process 1112 in Figure 12 comprises an activity 1211 that gate metal layer is provided.Figure 13 has shown that according to this first embodiment the device of an example of a semiconductor device 1350 after a gate metal layer is provided builds the cross-sectional view in district.As seen in Figure 29, the cross-sectional view in device structure district is the cross-sectional view in a part for the semiconductor device 1350 of " a " line place acquisition.This device builds the cross-sectional view that cross-sectional view comprises a-Si contact regions 2980 and through hole area 2982.In addition, Figure 14 has shown that according to this first embodiment the gate contacts of an example of semiconductor device 1350 after a gate metal layer is provided builds the cross-sectional view in district.As seen in Figure 29, the cross-sectional view in gate contacts structure district is the cross-sectional view in a part for the semiconductor device 1350 of " b " line place acquisition.This gate contacts builds the cross-sectional view that cross-sectional view comprises gate contacts district 2981.Figure 29 is only exemplary, the embodiment that is not limited to show at this.

For example, with reference to Figure 13 and Figure 14, on flexible substrate assembly 540, be provided with the silicon nitride passivation 1352 that approximately 0.30 μ m is thick.Silicon nitride passivation 1352 can be arranged on flexible substrate 450(Figure 10 of flexible substrate assembly 540) on.In certain embodiments, can before deposited silicon nitride passivation layers 1352, toast flexible substrate 450.

In addition, pattern metal grid 1353 can be arranged on silicon nitride passivation 1352.Pattern metal grid 1353 can comprise molybdenum.In some instances, can on silicon nitride passivation 1352, deposit the molybdenum layer of approximately 0.15 μ m, and then carry out pattern and be etched with and form pattern metal grid 1353.For example, can molybdenum be deposited on silicon nitride passivation 1352 by sputter.In some instances, can use the KDF744 deposition molybdenum by KDF electronics corporation (KDFElectronic, the Inc.) manufacture of New Jersey Luoghlin grace (Rockleigh).In identical or different example, can use the AMAT8330 etched pattern metal gates 1353 by Applied Materials (Applied Material, the Inc.) manufacture of California, USA Santa Clara.

Subsequently, the activity of a movable storehouse 1212 that provides is provided the process 1112 of Figure 12.Figure 15 and Figure 16 have shown the example that semiconductor device 1350 after a movable storehouse is provided according to this first embodiment.

With reference to Figure 15 and Figure 16, can on pattern metal grid layer 1353 and silicon nitride passivation 1352, form a for example silicon nitride gate dielectric 1554.With reference to Figure 15, for example the device at semiconductor device 1350 builds in district, a patterning amorphous silicon (a-Si) layer 1555 can be arranged on silicon nitride gate dielectric 1554, and a patterning silicon nitride inter-metal dielectric (IMD) layer 1556 built-up areas can be arranged on a-Si layer 1555.

In some instances, as shown at Figure 15 and Figure 16, the chemical vapour deposition (CVD) that silicon nitride gate dielectric 1554 can strengthen by plasma (PECVD) is deposited on the semiconductor device 1350 on metal gate layers 1353 and silicon nitride passivation 1352.In identical or different example, silicon nitride gate dielectric 1554 can be thick for approximately 0.30 μ m.

With reference to Figure 15, as example, a-Si layer 1555 can be deposited on silicon nitride gate dielectric 1554 by PECVD.In identical or different example, a-Si layer 1555 can be thick for approximately 0.08 μ m.

As example, silicon nitride IMD layer 1556 can be deposited on a-Si layer 1555 by PECVD equally.In identical or different example, silicon nitride IMD layer 1556 can be thick for approximately 0.10 μ m.

In some instances, the AMAT P5000 that silicon nitride gate dielectric 1554, a-Si layer 1555 and silicon nitride IMD layer 1556 can be used the Applied Materials (Applied Materials, Inc.) of California, USA Santa Clara to manufacture by PECVD deposits.In identical or different example, the temperature that silicon nitride gate dielectric 1554, a-Si layer 1555 and silicon nitride IMD layer 1556 deposit on semiconductor device 1350 is greater than approximately 180 ° of C.For example, to deposit to the temperature on semiconductor device 1350 be from approximately 180 ° of C to approximately 250 ° of C for silicon nitride gate dielectric 1554, a-Si layer 1555 and silicon nitride IMD layer 1556.As an example, the temperature that silicon nitride gate dielectric 1554, a-Si layer 1555 and silicon nitride IMD layer 1556 deposit on semiconductor device 1350 is from approximately 188 ° of C to approximately 193 ° of C.In addition, silicon nitride gate dielectric 1554, a-Si layer 1555, amount of money silicon nitride IMD layer 1556 can complete to the deposition on semiconductor device 1350 under near vacuum.

After silicon nitride gate dielectric 1554, a-Si layer 1555 and silicon nitride IMD layer 1556 deposit on semiconductor device 1350, the layer producing can be etched.For example, can use buffer oxide etch (BOE) etching of silicon nitride of 10:1.In addition, can use AMAT8330 etching a-Si layer 1555.In some instances, etching silicon nitride IMD layer 1556 and a-Si layer 1555 to expose a-Si layer 1555, that is, silicon nitride IMD layer 1556 does not cover a-Si layer 1555 completely.

Then, the activity of a mesa passivation layer 1213 that provides is provided the process 1112 of Figure 12.Figure 17 and Figure 18 have shown the example that semiconductor device 1350 after a mesa passivation layer is provided according to this first embodiment.

With reference to Figure 17, as example, in the device structure district of semiconductor device 1350, mesa passivation layer 1757 is deposited on the semiconductor device 1350 on silicon nitride gate dielectric 1554, a-Si layer 1555 and silicon nitride IMD layer 1556.Mesa passivation layer 1757 can comprise silicon nitride.Mesa passivation layer 1757 can be deposited on a-Si layer 1555, so that the surface of passivation and/or encapsulation a-Si layer 1555, thereby prevent from polluting the surface of a-Si layer 1555 and reduce the surperficial leakage current along a-Si layer 1555.With reference to Figure 18, as example, in the gate contacts structure district of semiconductor device 1350, mesa passivation layer 1757 can be deposited on silicon nitride gate dielectric 1554.

Mesa passivation layer 1757 can be deposited on semiconductor device 1350 by PECVD.As example, mesa passivation layer 1757 can be thick for approximately 0.10 μ m.In identical or different example, can use AMAT P5000 to deposit table top passivation layer 1757 by PECVD.

Subsequently, the process 1112 of Figure 12 comprises that is carried out one or more rear table top passivation layers etched movable 1214.Figure 19 and Figure 20 have shown the cross-sectional view that carries out semiconductor device 1350 after the etching of one or more rear table top passivation layer.For example, Figure 20 has shown the semiconductor device 1350 there is contact gate etch in the gate contacts of semiconductor device 1350 builds district after.In identical or different example, Figure 19 has shown the semiconductor device 1350 there is contact a-Si etching in the device of semiconductor device 1350 builds district after.

The contact gate etch that the gate contacts of semiconductor device 1350 builds district can etch away silicon nitride.For example, contact gate etch can etch away mesa passivation layer 1757 and silicon nitride gate dielectric 1554.In many examples, the metal gate layers 1353 of silicon nitride gate dielectric 1554 belows plays a role as etch stop in etching process.In the Tegal903 that can manufacture in the Tegal company (Tegal Corporation) of California, USA Pei Taluma (Petaluma), carry out the contact gate etch that contact grid builds district.After the gate etch of contact, gate contacts 2091 forms on semiconductor device 1350.Gate contacts 2091 is associated with the gate contacts district 2981 of Figure 29.

The contact a-Si etching that the device of semiconductor device 1350 builds district can etch away silicon nitride.For example, a-Si etching in contact can etch away mesa passivation layer 1757 and silicon nitride IMD layer 1556.Can use these silicon nitride layers of 10:1BOE etching.A-Si layer 1555 under silicon nitride layer 1556 can be used as the etch stop of etching process.After the a-Si etching of contact, a-Si contact 1990 forms on semiconductor device 1350.A-Si contact 1990 is associated with the a-Si contact regions 2980 of Figure 29.In the present embodiment, contact a-Si etching and contact gate etch can be to use the independent etching of independent etching mask.

After movable 1214, the process 1112 of Figure 12 completes.With reference to Figure 11, step 120 proceeds to provide the process 1113 of one or more contact elements.Figure 21 has shown that process 1113 completes the cross-sectional view in the device structure district of an example of semiconductor device 1350 afterwards.In addition, Figure 22 has shown that process 1113 completes the cross-sectional view in the gate contacts structure district of an example of semiconductor device 1350 afterwards.

In the example shown in Figure 21, N+a-Si layer 2159 is arranged on the part of mesa passivation layer 1757, a-Si layer 1555 and silicon nitride IMD layer 1556.As Figure 21 shows, diffusion impervious layer 2158 is arranged on N+a-Si layer 2159, and metal level 2160 is arranged on diffusion impervious layer 2158.Similarly, in the example of Figure 22, N+a-Si layer 2159 is arranged on the part of mesa passivation layer 1757, silicon nitride gate dielectric 1554 and gate metal layer 1353.Equally as shown in figure 22, diffusion impervious layer 2158 is arranged on N+a-Si layer 2159, and metal level 2160 is arranged on diffusion impervious layer 2158.

N+a-Si layer 2159 can arrange by the mode of PECVD.As example, N+a-Si layer 2159 can be thick for approximately 0.05 μ m.In identical or different example, can use AMAT P5000 to deposit N+a-Si layer 2159 by PECVD.

As example, diffusion impervious layer 2158 can comprise tantalum (Ta).In identical or different example, metal level 2160 can comprise aluminium (A1).Diffusion impervious layer 2158 can help prevent the movement from the atom of metal level 2160, such as Al atom, is diffused into N+a-Si layer 2159 and subsequently in a-Si layer 1555.Diffusion impervious layer 2158 and metal level 2160 can be by sputtering sedimentation on N+a-Si layers 2159.In some instances, can use KDF744 deposit and spread barrier layer 2158 and metal level 2160.

Afterwards, N+a-Si layer 2159, diffusion impervious layer 2158 and metal level 2160 have been deposited on semiconductor device 1350, and these three layers are etched.As example, can use these three layers of AMAT8330 etching.In some instances, for all these three layers, use single formula etching N+a-Si layer 2159, diffusion impervious layer 2158 and a metal level 2160.As example, use and to there is about 140sccm(standard cubic centimeter per minute) boron chloride (BCl of flow velocity ₃) and there is the chlorine (Cl of about 10sccm flow velocity ₂) under the pressure of about 20mTorr to N+a-Si layer 2159, diffusion impervious layer 2158 and metal level 2160 etching 1 minute 45 seconds.Then, Cl ₂be increased to 30sccm, and pressure dropped to 10mTorr in 15 minutes.Then, by BCl ₃speed drops to 30sccm, and pressure is increased to 15mTorr.Finally, BCl ₃and Cl ₂flow velocity is zero, and in 60 minutes oxygen (O under the pressure of 50mTorr ₂) be 50sccm.

In various embodiments, step 120 can comprise a process 1198 that base dielectric is provided.Base dielectric can be spin-on dielectric materials (for example, dielectric layer 2461(Figure 24)) uniform outer surface (for example a, wetting layer) is provided.In some instances, base dielectric can comprise silica or silicon nitride.In many examples, can use the process for example, with the process that is used to provide the second dielectric material (, process 1117) as described below similar or identical that base dielectric is provided.In other embodiments, step 120 does not comprise provides base dielectric.

Subsequently, a kind of process of the first dielectric material 1114 that provides is provided step 120.The first dielectric material can be arranged on one or more contact elements of process 1113.In some instances, the first dielectric material can be a kind of organosiloxane base dielectric material, organosiloxane dielectric material and/or siloxy group dielectric material.In various embodiments, the first dielectric material can be organic.Use organosiloxane base dielectric material can allow than the thicker film of use non-organic silicon oxyalkyl dielectric material and more flexible film.In some instances, the first dielectric material can be used as interlayer dielectric.In other examples, the first dielectric material can be as dielectric in layer.

Table 1 has been shown the attribute of an example of the dielectric material that can be used as the first dielectric material in process 1114 according to an embodiment.

Table 1

As used in table 1, film thickness refers to the thickness of desirable dielectric material, has shown other attributes of this dielectric material in table.Transmittance refers to that transmission crosses the percentage of the light of this dielectric material.Complanation refers to the flatness (DOP) of this dielectric material.The opposing of plasma infringement represents can not damage the plasma of this film.Tack means can be coupled at least dielectric material of these materials.Getter action can refer to the outgassing rate except atmospheric pressure or this dielectric material of dielectric material.Moisture absorption can refer to that this dielectric material absorbs the speed of moisture.Drip painting instrument and refer to the equipment that can be used to apply this dielectric material.

Table 2 has been shown the attribute of the second example of a kind of dielectric material that can be used as the first dielectric material in process 1114 according to an embodiment.

Table 2

As used in table 2, etching chemistry composition refers to the etching chemistry composition that can be used for this dielectric material of etching.Etch-rate is the minimum etch-rate of this dielectric material while using etching chemistry composition.Characteristic size refers to element forming with this dielectric material or the minimum dimension of feature.Puncture voltage is the voltage that this dielectric material starts to serve as the per unit length of conductor.Thermal resistance is that this material becomes the unstable front minimum temperature that can bear.

Figure 23 has shown the example that a kind of process of the first dielectric material 1114 is provided.In various embodiments, this first dielectric material can be spin-on dielectric.Correspondingly, in these examples, can this dielectric applications be arrived to semiconductor device by this first dielectric material being spun on this first metal layer and various silicon nitride layer.In various embodiments, can in the available Rite Track8600 of the Rite of Ohio, USA west chester Track company (Rite Track, Inc.), carry out the application of this first dielectric material.

With reference to Figure 23, process 1114 can comprise the activity 2330 with a first set rate spin coating semiconductor device.In some instances, this first predetermined spin coating speed is between about 500rpm and about 2000rpm.In identical or different embodiment, this first set rate is about 1000rpm.

Subsequently, process 1114 can comprise the activity 2331 of dripping this first dielectric material of painting.In some instances, this first dielectric material is dripped to be coated on this substrate, and this substrate is just with this first set rate spin coating.In some instances, can use syringe to drip and be coated with this first dielectric material.If this substrate is the wafer of six inch diameters, about 4mL(milliliter) can drip and be coated onto on semiconductor device.In some instances, dripping the pressure in syringe in the process being coated with can be about 15kPa.In identical or different embodiment, syringe drips and is painted with after this first dielectric material, and syringe is the pressure of the about 1kPa of resorption.The resorption pressure of syringe prevent drip painting process complete after from drip the first dielectric material of additional amount of syringe.For 6 inches of wafers, drip to be coated with approximately 3 seconds of process need.Semiconductor device is with this first set rate spin coating, until activity 2331 completes.

In various embodiments, used one dynamically to drip painting process.Namely, this substrate spin coating when dripping this first dielectric material of painting.In some instances, this first dielectric material drips the center that is coated in this substrate.In other examples, when a painting process starts, syringe is positioned at the center of this substrate and with approximately 30 to approximately 60 millimeters of constant rate of speeds per second, moves to the edge of this substrate from the center of this substrate when this substrate spin coating.In other embodiments, used a static state to drip painting process.Namely, not spin coating in dripping painting process of this substrate.

Then, process 1114 comprises and the speed of this semiconductor device is risen to the activity 2332 of second set rate from this first set rate.In some instances, this second predetermined spin coating speed is between about 2000rpm and about 4000rpm.In identical or different embodiment, this second set rate is about 2600rpm.The first dielectric material that can distribute approximately two microns of thickness with second this semiconductor device of set rate spin coating of about 2600rpm for approximately 30 seconds on the surface of this semiconductor device.The different-thickness of the first dielectric material can be by being used the second different set rates to realize.

Figure 30 is the displaying of the thickness of this first dielectric material to the spin coating speed of this semi-conducting material (that is, speed).

Process 1114 can further comprise the activity 2333 of carrying out edge bead removal.In some instances, during

activity

2331 and 2332, due to the effect of the centrifugal force to this edges of substrate, this first dielectric material outwards flows, and in the upper edge of this semiconductor device, creates ridge (that is, edge bead).When dry, this edge bead can peel off and increase the defect of this semiconductor device and/or damage manufacturing equipment.Correspondingly, this edge bead is removed in movable 2333.In some instances, the equipment being used in movable 2331 and 2332 can comprise an edge bead removal device.In some instances, on this edge bead, spray solvent to remove this edges of substrate the first dielectric material around.In some instances, when with the 3rd this semiconductor device of set rate spin coating, in this edges of substrate inside, for example sprayed solvent on approximately five to approximately six millimeters.In some instances, from this edges of substrate, remove this first dielectric material and also contribute to guarantee when a kind of the second dielectric material (process 1117 Figure 11) is set on this first dielectric material, for the edge of this first dielectric material is covered with a kind of the second dielectric material.

In some instances, can use cyclohexanone, propylene glycol monomethyl ether (PGMEA) or other edge beads to remove solvent.In some instances, this semiconductor device the 3rd set rate with about 1000rpm in edge bead removal process rotates.In some instances, this semiconductor device about 30 seconds with the 3rd set rate spin coating, and solvent is sprayed on this bead edge during this period.

Then, process 1114 is proceeded an activity 2334 that stops this semiconductor device of spin coating.After stopping the spin coating of this semiconductor device, process 1114 completes.

Referring back to Figure 11, step 120 comprises the process 1115 of toasting this semiconductor device.In some instances, toasting this semiconductor device comprises and toasts the process 1114 of this first dielectric material, the process 1112 of the process 1113 of these one or more contact elements, these one or more the first semiconductor elements and the process 110 of this substrate.One of object of baking is from the process of edge bead, to cause the evaporation of solvent.Toast this semiconductor device and can also improve complanation, reduce film defects, and crosslinked this first dielectric material.

In various embodiments, use twice baking sequentially to carry out the baking of this semiconductor device.Can under atmospheric pressure use a hot plate to carry out this bake process.Can be in implementation 1115 in Rite Track8800 for example.

Baking is the baking of approximately 60 seconds under 160 ° of C for the first time.In alternative exemplary, baking can be the baking of approximately 60 seconds under approximately 150 ° of C for the first time.After having toasted for the first time, in some instances, allow this semiconductor device to toast for the second time cooling approximately 30 seconds before.Can allow this semiconductor device at room temperature (and not using coldplate) cooling.In these examples, allow cooling this semiconductor device, for example, because treatment system is used polytetrafluoroethylene (, moral The Moore Co. of EI Du Pont in Delaware, USA Wilmington city (E.I.du Pont de Nemours Company)

material) chuck of coating is processed this semiconductor device.A hot semiconductor device is placed on the chuck of polytetrafluoroethylene coating and may damages chuck.If used other equipment, perhaps cooling procedure can be skipped.

After making this semiconductor device cooling, can on a hot plate, toast for the second time this semiconductor device.In certain embodiments, baking for the second time can continue for approximately 60 seconds at the temperature higher than approximately 160 ° of C, because 160 ° of boiling points that C is PGMEA.For example, if baking is under 160 ° of C for the first time, baking for the second time can continue for approximately 60 seconds under approximately 170 ° of C.If baking is under 150 ° of C for the first time, baking for the second time can continue for approximately 60 seconds under approximately 200 ° of C.After having toasted for the second time, 30 seconds of can be again cooling this semiconductor device.In other embodiments, can carry out other baking orders.

After having toasted, the next process in step 120 is the process 1116 of solidifying this first dielectric material.Solidifying of this first dielectric material can improve the crosslinked of this first dielectric material.In some instances, can be in convection oven, in nitrogen, under atmospheric pressure (that is, approximately atmospheric pressure) be cured.

In various examples, this semiconductor device can be placed in baking oven.Afterwards, the temperature in baking oven can rise to approximately 200 ° of C, and this semiconductor device can be toasted approximately one hour under approximately 200 ° of C.Temperature increase is to the speed of 1 ° of C-2 ° of C approximately per minute, so that the getter action of the first dielectric material of process 1114 is minimized.After having toasted, temperature slow decreasing (for example, 1 ° of C-2 ° of C per minute) is to room temperature.

In another embodiment, can use the baking procedure toasting separately with five times.Baking for the first time can be the baking of approximately ten minutes under approximately 60 ° of C.The lifting time from room temperature to approximately 60 ° of C is approximately ten minutes.After having toasted under approximately 60 ° of C, temperature rose to approximately 160 ° of C in approximately 32 minutes.This semiconductor device is toasted approximately 35 minutes under approximately 160 ° of C.

After 160 ° of C bakings, then the temperature of convection oven was increased to approximately 180 ° of C in approximately ten minutes.This semiconductor device is toasted approximately 20 minutes under approximately 180 ° of C.

After having toasted under 180 ° of C, temperature rose to approximately 200 ° of C in approximately 50 minutes.This semiconductor device is toasted approximately 60 minutes under approximately 200 ° of C.Finally, in this baking procedure, the temperature in baking oven drops to approximately 60 ° of C in about seventy points clock.This semiconductor device is toasted approximately ten minutes under approximately 60 ° of C.After having toasted, before proceeding the step 120 of Figure 11, allow this semiconductor device to be cooled to about room temperature.The baking of this semiconductor device can contribute to make this one or more contact element annealing.

Subsequently, a kind of process of the second dielectric material 1117 that provides is provided step 120.In some instances, provide this second dielectric material to be included in (that is, the first dielectric material of process 1114) this second dielectric material of substrate on this siloxanes dielectric layer.In some instances, this second dielectric material can comprise silicon nitride.In identical or different example, this second dielectric material can comprise silicon oxynitride (SiO _xn _y), silica and/or silicon dioxide (SiO ₂).In some instances, can deposit this second dielectric material by low temperature PECVD process.In some instances, as the part that this second dielectric material is provided, this first dielectric material is covered with to this second dielectric material.In some instances, the edge of this first dielectric material can be covered with this second dielectric material, so that this first dielectric material is not exposed to any follow-up oxygen (O ₂) plasma ashing.Oxygen plasma ashing can make this first dielectric material degraded in some instances.

Can approximately 0.1 μ m deposit this second dielectric material to the thickness of approximately 0.2 μ m.Can deposit this second dielectric material, to protect this first dielectric material to avoid later stage etching.

Next process in step 120 is the process 1118 of a mask that provides on this second dielectric material.In process 1118, the mask of application can be the etching activity for the process 1119 of Figure 11.

In some instances, process 1118 can comprise (a patterning photoresist is applied on the dielectric layer of siloxy group, the first dielectric substance of process 1114) mask of patterning or on organosiloxane based dielectric (that is, the first dielectric substance of process 1114).Similarly, process 1118 can be included on organosiloxane dielectric layer (that is, the first dielectric material of process 1114) patterned mask is provided.

In some instances, mask covers the one or more by not etched part of the first dielectric material and the second dielectric material.Can provide mask with a thickness, to this mask is not worn by erosion in the etching process of the process 1119 of Figure 11.In some instances, mask can have approximately 3.5 μ m or approximately 2.5 μ m to the thickness of approximately 5.0 μ m.

In some instances, mask can comprise photoresist.In some instances, photoresist can be the AZ electronic material MiR900 photoresist of AZ material (AZ Materials) manufacture of Luxembourg capital Luxembourg.In some instances, use Rite Track8800 that photoresist is coated on the first dielectric material.For example, this semiconductor device can steam filling and spin coating have mask (for example, photoresist).Be coated with after this semiconductor device, this semiconductor device toasts approximately 60 seconds under approximately 105 ° of C.

Then, by template, this semiconductor device being snapped to correct position and is exposed to UV(ultraviolet ray) light is to be transferred to this mask by mask image from this template.Expose after mask, under approximately 110 ° of C, this semiconductor device is toasted approximately 90 seconds.Then use 90 seconds puddle development masks with standard development chemicals, to remove the part that is not exposed to UV light of photoresist.

After having developed, the decline that mask is provided on the second dielectric material is on mask, to carry out the reflux course of photoresist.It is after development photoresist, mask to be heated so that photoresist becomes at least semi-liquid-like and mobile process that photoresist refluxes.

In some instances, under approximately 140 ° of C, this semiconductor device is toasted approximately 60 seconds.This photoresist reflux course will reduce the acutance at mask edge, and therefore, while carrying out etching in the process 1119 at Figure 11, the through hole in the first dielectric and the second dielectric will have the side of inclination.In some instances, the side of these inclinations and horizontal plane are into about the angle of 30 degree.

Then, step 120 comprises the process 1119 of etching base dielectric, the first dielectric material and the second dielectric material.Base dielectric, the first dielectric material and the second dielectric material are etched with in base dielectric, the first dielectric material and the second dielectric material and create through hole.

In some instances, use identical etching mask, in identical process, base dielectric, the first dielectric material and the second dielectric material are carried out to etching.In other examples, the etching in first process of the first dielectric material, and the etching in second process of the second dielectric material, and base dielectric etching in the 3rd process.

In these other examples, a mask can be applied to base dielectric; Can etching base dielectric; And before can providing the first dielectric material in the process 1114 of Figure 11, this mask is removed.Subsequently, a mask can be applied to the first dielectric material; Can etching the first dielectric material; And remove this mask before can providing the second dielectric material in the process 1118 of Figure 11.Then, a mask can be applied to the second dielectric material, and can carry out etching to the second dielectric material.In another example, mask that can use procedure 1118 carries out etching to the second dielectric material; Can remove mask; And patterning the second dielectric material can be used for the first dielectric material to carry out patterning as mask.

In a lot of embodiment, base dielectric, the first dielectric material and the second dielectric material have been carried out to plasma etching.In identical or different embodiment, base dielectric, the first dielectric material and the second dielectric material have been carried out to reactive ion etching (RIE).In some instances, use the etchant based on fluorine to carry out etching to base dielectric, the first dielectric material and the second dielectric material.In some instances, etchant can be fluoroform (CHF ₃), sulphur hexafluoride (SF ₆) or other etchants based on fluorine.

For example, in there is no some examples of base dielectric (, process 1198 is skipped), the first material can be foregoing organosiloxane dielectric material, and the second material can be silicon nitride.In these examples, can use sulphur hexafluoride (SF ₆) the first dielectric material and the second dielectric material are carried out to the RIE etching of approximately four minutes.If sulphur hexafluoride is used as etchant, can be in plasma chamber with the sulphur hexafluoride of 1:2 to oxygen (O ₂) ratio carry out etching.

Sulphur hexafluoride is roughly the same (that is, 0.5 μ m approximately per minute) for the etch rate of the first dielectric material and the second dielectric material.Yet the etch rate of the second dielectric material is less times greater than the first dielectric material.In some instances, the pressure in etching process ionic medium fluid chamber is that about 50mTorr is to about 400mTorr.In the Tegal901 that can manufacture in the Tegal of California, USA Pei Taluma company (TegalCorporation), carry out RIE etching.

Can be before the first dielectric material etching the second dielectric material; Can be before base dielectric etching the first dielectric material.In a lot of examples, the metal level of base dielectric below is used as etching stopping layer in etching process.If as etchant, metal level can be aluminium by sulphur hexafluoride.In the present embodiment, metal level cannot be molybdenum or tantalum, because these two kinds of metals of sulphur hexafluoride etching.In different embodiment, if on cover the second dielectric layer etching be a regularly etching, metal level can comprise molybdenum and/or tantalum.

Can not use in some instances buffer oxide etch (BOE) and chlorine based etchant, because they do not carry out etching to it when the first dielectric material includes organic siloxane dielectric material.Figure 24 has shown the cross-sectional view that the device of an example of semiconductor device 1350 after base dielectric 2499, the first dielectric material 2461 and the second dielectric material 2462 etchings is built to district.After process 1119 in Figure 11, semiconductor device 1350 can comprise through hole 2463, as shown in figure 24.Through hole 2463 is associated with the through hole area 2982 of Figure 29.Mask in Figure 24 on not shown the second dielectric layer 2462.

Referring again to Figure 11, the next process in step 120 is to remove the process 1120 of mask.In some instances, for example, by ashing mask at the temperature lower than 110 ° of C (, photoresist), can remove mask.If at 110 ° of temperature more than C ashing mask, in the first dielectric material, can break.Correspondingly, in some instances, the ashing of mask is carried out to the temperature within the scope of approximately 90 ° of C at approximately 70 ° of C.In identical or different example, the ashing of mask is carried out to the temperature within the scope of approximately 84 ° of C at approximately 77 ° of C.

Can under the pressure of about 300mTorr, carry out podzolic process being not more than.Oxygen (O ₂) can in the process of ashing, the data rate stream with about 50sccm cross chamber.In various examples, can in Tegal901, carry out cineration step.After ashing mask, can and make its Rotary drying with this semiconductor device of deionized water rinsing.In some instances, can in high speed dump washer, rinse, and can in spin rinse drying machine, be dried.

In other examples, can use wet destriping photoresist.In certain embodiments, can use the overburden based on 1-METHYLPYRROLIDONE (NMP).

Next process in the step 120 of Figure 21 is to provide the process 1121 of one or more the second semiconductor elements.The example of one or more the second semiconductor elements can comprise second metal level, a tin indium oxide (ITO) layer and a silicon nitride layer.

As example, Figure 25 has shown that the device of the example that second metal level 2564 and a rear semiconductor device 1350 of ITO floor 2565 are provided builds the cross-sectional view in district.The second metal level 2564 can be deposited on the second dielectric material 2462, and in through hole 2463 (Figure 24) at least in part.The second metal level 2564 can comprise molybdenum and can be thick for approximately 0.15 μ m.In some instances, can use KDF744 to pass through sputtering sedimentation the second metal level 2564.

ITO layer 2565 can be deposited on the second metal level 2564.ITO layer 2565 can comprise tin indium oxide and can be thick for approximately 0.05 μ m.In some instances, can use KDF744 to pass through sputtering sedimentation ITO layer.

In some instances, can carry out pattern etched to the second metal level 2564.Then, ITO layer 2565 can be deposited on the second metal level 2564, and then carry out pattern etched.As example, can use AMAT8330 to carry out etching to the second metal level 2564 and ITO layer 2565.

Figure 26 has shown that the device of the example that a rear semiconductor device 350 of silicon nitride layer 2666 is provided builds the cross-sectional view in district.Silicon nitride layer 2666 can be deposited on ITO layer 2565 and can be thick for approximately 0.10 μ m.In some instances, can use AMAT P5000 by PECVD deposited silicon nitride layer 2666.In identical or other examples, can use Tegal901 to carry out etching to silicon nitride layer 2666, wherein ITO layer 2565 is stop-layer.

After process 1121, step 120 has just completed.With reference to Fig. 1, the next step of method 100 is from carrier substrates, to remove the flexible substrate step 130 of (comprising the semiconductor element that is connected to flexible substrate).In some instances, can remove flexible substrate by flexible substrate being peeled off from carrier substrates from carrier substrates with hand.

Turn to another embodiment, Figure 27 has shown a kind of by the example of the method for flexible substrate complanation 2700.In identical or different embodiment, method 2700 can be considered to a kind of method of etching organosiloxane dielectric material.Method 2700 can also be considered to a kind of engraving method of organosiloxane based dielectric or the engraving method of siloxy group dielectric material.Method 2700 is only exemplary, the embodiment that is not limited to show at this.Method 2700 can be applied in not this specifically describe or the many different embodiment or example that describe in.

With reference to Figure 27, method 2700 comprises the step 2711 that a substrate is provided.Step 2711 can be similar or identical with the process 211 of Fig. 2.This substrate can be similar or identical with the substrate 450 of Fig. 4.In further embodiments, step 2711 can be similar or identical with the method 110 of Fig. 1, and this substrate can be similar or identical with substrate 450, and it can be a part for flexible substrate assembly 540.

Method 2700 can proceed to provide a kind of step 2712 of the first dielectric material.In some instances, this first dielectric material 2462 can be similar or identical with the second dielectric material of the process 1117 of Figure 24 and Figure 11.For example, the second dielectric material 2462 can comprise that a thickness is that approximately 0.1 μ m is to the silicon nitride layer of approximately 0.2 μ m.

Next step in method 2700 is to provide a kind of step 2713 of the second dielectric material.This second dielectric material can be similar or identical with the first dielectric material 2461 of Figure 24.Step 2713 can be similar or identical with the process 1114 of Fig. 1.

The step 2714 that method 2700 proceeds to toast this second dielectric material.In some instances, step 2714 can be similar or identical with the process 1115 of Figure 11.

Then, method 2700 comprises the step 2715 of solidifying this second dielectric material.In some instances, step 2715 can be similar or identical with the process 1116 of Figure 11.

In other examples, can use and there is the different baking procedure that in convection oven, five times are toasted separately.Baking for the first time can be the baking of approximately ten minutes under approximately 40 ° of C.The lifting time from room temperature to approximately 40 ° of C is approximately two minutes.After having toasted under 40 ° of C, temperature rose to approximately 160 ° of C in approximately 32 minutes.Then, this flexible substrate is toasted approximately 35 minutes under approximately 160 ° of C.

After 160 ° of C bakings, then the temperature of convection oven was increased to approximately 180 ° of C in approximately ten minutes.This flexible substrate is toasted approximately 20 minutes under approximately 180 ° of C.

After having toasted under 180 ° of C, temperature rose to approximately 230 ° of C in approximately 50 minutes.Alternately, temperature rises to approximately 230 ° of C with 2 ° of C approximately per minute.This flexible substrate is toasted approximately 15 hours under approximately 230 ° of C.

Finally, in this baking procedure, the temperature in baking oven dropped to approximately 60 ° of C in approximately 85 minutes.This flexible substrate is toasted approximately ten minutes under approximately 60 ° of C.After having toasted, before proceeding the step 2700 of Figure 27, allow this flexible substrate to be cooled to be about room temperature.

Method 2700 proceeds to provide a kind of step 2716 of the 3rd dielectric material.In some instances, the 3rd dielectric material can approximately 0.2 μ m to the thickness deposition of approximately 0.4 μ m.In some instances, the 3rd dielectric material can be the thick silicon nitride layer of approximately 0.3 μ m.After having deposited the 3rd dielectric material, can with approximately 180 ° of C, toast this flexible substrate approximately five minutes in position.In some instances, the 3rd dielectric material can be similar or identical with the nitride passivation layer 1352 of Figure 13.

Figure 28 has shown the example that semiconductor device 2850 after the 3rd dielectric material is provided according to this second embodiment.In these examples, the first dielectric material 2871 is arranged on flexible substrate assembly 540.The second dielectric material 2872 is arranged on the first dielectric material 2871, and the 3rd dielectric material 2873 is arranged on the second dielectric material 2872.

Provide after the 3rd dielectric material, method 2700 has just completed.The flexible substrate providing in the step 110 of method 100 is provided resulting semiconductor device (Figure 28 2850).

Return to accompanying drawing, Figure 31 has shown an example manufacturing the method 3100 of semiconductor device according to an embodiment.Method 3100 is only exemplary, the embodiment that is not limited to show at this.Method 3100 can be applied in not this specifically describe or the many different embodiment or example that describe in.Method 3100 can be similar to method 120(Fig. 2).In certain embodiments, can use step, process and/or the activity of shown order manner of execution 3100.In other embodiments, can be with step, process and/or the activity of any suitable order manner of execution 3100.Also in other embodiments, can combine or skipping method 3100 in step, process and/or activity in one or more.

Referring now to Figure 31, method 3100 comprises the step 3101 that a substrate is provided.In certain embodiments, step 3101 can with process 211(Fig. 2) and/or method 110(Fig. 2) similar or identical.This substrate can be similar or identical with the substrate 3208 of showing in Figure 32 and Figure 33.

Now referring back to Figure 31, method 3100 can be included on this substrate and/or top provides the step 3102 on a barrier layer.In certain embodiments, step 3103 is included on this barrier layer gate metal layer is provided.In a lot of embodiment, step 3102 is as described below occur in step 3103 before and/or after step 3101.Barrier layer can be similar or identical with Figure 32 and Figure 33 barrier layer 3209 that show and as described below.

Referring back to Figure 31, method 3100 is included in the step 3103 that a gate metal layer is provided on this substrate now.In a lot of embodiment, step 3103 is as described below occur in step 3104 and/or 3105 before and/or after step 3102.In certain embodiments, step 3103 can be similar or identical with (Figure 12) activity 1211.In various embodiments, this gate metal layer can be similar or identical with Figure 32 and Figure 33 gate metal layer 3202 that show and as described below.Figure 49 is a flow chart, according to an embodiment, has shown the step 3103 that a gate metal layer is provided on this substrate.

In various embodiments, step 3103 can be included on this substrate and/or top deposits the process 4901 of this gate metal layer.Step 3103 can be included on this gate metal layer the process 4902 of deposition and the first photoresist layer that develops.Step 3103 can be included in this first photoresist layer process 4903 by a kind of first this gate metal layer of etchant etching as first etching mask time.

Figure 32 has shown the cross-sectional view that builds district at the device that performs step an example of 3103 rear semiconductor device 3200 according to an embodiment.As seen in Figure 46, the cross-sectional view in bulking block district is the cross-sectional view in a part for the semiconductor device 3200 of " a " line place acquisition.This device builds cross-sectional view and comprises that device builds contact regions 4680 and through hole area 4682.In addition, Figure 33 has shown the cross-sectional view that builds district at the gate contacts that performs step an example of 3103 rear semiconductor device 3200 according to an embodiment.As seen in Figure 46, the cross-sectional view in gate contacts structure district is the cross-sectional view in a part for the semiconductor device 3200 of " b " line place acquisition.This gate contacts builds the cross-sectional view that cross-sectional view comprises gate contacts district 4681.Figure 46 is only exemplary, the embodiment that is not limited to show at this.

In a lot of embodiment, except miscellaneous part, an electronic installation (not shown) comprises one or more semiconductor device 3200.In a lot of embodiment, semiconductor device 3200 comprises a transistor or a thin-film transistor.In identical or different embodiment, this electronic installation can comprise a display, and this display comprises this or these semiconductor device/transistor.In identical or different embodiment, this display can comprise any in liquid crystal display, electrophoretic display device (EPD) or Organic Light Emitting Diode (OLED) display.

In various examples, semiconductor device 3200 can comprise the effective saturated mobility of 18.6cm2/V, and under positive negative gate bias direct current (DC) stress of 10,000 seconds 2.2 volts or lower threshold voltage shift.In other examples, can be with approximately 200 degrees Celsius or lower Temperature Treatment semiconductor device 3200.

For example, with reference to Figure 32 and Figure 33, gate metal layer 3202 can be on substrate 3208 and/or barrier layer 3209.In identical or different embodiment, gate metal layer 3202 can be on barrier layer 3209.

In various embodiments, substrate 3208 can comprise rigid substrate and/or flexible substrate.In certain embodiments, substrate 3208 can with substrate 450(Fig. 4), flexible substrate assembly 540(Fig. 5, Fig. 6, Fig. 8, Fig. 9 or Figure 10) a part or carrier substrates 651(Fig. 6) similar or identical.

In a lot of embodiment, barrier layer 3209 can comprise a kind of the first dielectric material.This first dielectric material can comprise silicon dioxide and/or silicon nitride.In identical or different embodiment, barrier layer 3209 can with passivation layer 1352(Figure 13) similar or identical.In identical or different embodiment, barrier layer 3209 can be more than or equal to approximately 200 nanometer thickness and be less than or equal to approximately 400 nanometer thickness.In a further embodiment, barrier layer 3209 can be approximately 300 nanometer thickness.

In a lot of embodiment, gate metal layer 3202 can comprise one or more in molybdenum, aluminium, tantalum, chromium or tungsten.In identical or different embodiment, gate metal layer 3202 can with pattern metal grid 1353(Figure 13) similar or identical.In identical or different embodiment, gate metal layer 3202 can be more than or equal to approximately 100 nanometer thickness and be less than or equal to approximately 200 nanometer thickness.In a further embodiment, gate metal layer 3202 can be approximately 150 nanometer thickness.

Now referring back to Figure 31, method 3100 can be included on this gate metal layer and/or top provides the step 3104 of a gate blocks layer.In a lot of embodiment, step 3104 is as described below occur in step 3105 before and/or after step 3103.Gate blocks layer can be similar or identical with Figure 35 and Figure 36 gate blocks layer 3510 that show and as described below.

Referring back to Figure 31, method 3100 is included in the step 3105 that a transistor active layer is provided on this gate metal layer now.In a lot of embodiment, step 3105 is as described below occur in step 3106 before and/or after step 3104.Figure 34 is a flow chart, according to an embodiment, has shown the step 3105 that transistor active layer is provided on this gate metal layer.This transistor active layer can be similar or identical with transistor active layer 3505 that show and as described below in Figure 35 and Figure 36, and this active layer can comprise that as Figure 47, show and the first active layer 4706 as described below and the second active layer 4707.In a lot of embodiment, 3511(is not shown with etching stopping layer) similar or identical etching stopping layer can be as on Figure 35 displaying and transistor active layer as described below and/or above.

The step 3105 of Figure 34 is included on this gate metal layer and/or top provides the process 3401 of first active layer.In a lot of embodiment, this first active layer can be similar with the first active layer 4706 as described below.

In certain embodiments, process 3401 can comprise that (a) is at this substrate of vacuum indoor positioning, and (b) a kind of target material of sputter in this vacuum chamber, this target material comprises at least one in indium oxide, zinc oxide, gallium oxide, tin oxide, hafnium oxide or aluminium oxide, and wherein the first feed gas comprises argon gas.In certain embodiments, this first feed gas is except argon gas or replace argon gas can also comprise nitrogen.

The step 3105 of Figure 34 is included on this first active layer and/or top provides the process 3402 of second active layer.In identical or different embodiment, this second active layer can be as described below similar with the second active layer 4707.As for transistor active layer, only comprise the step 3105 of this first active layer, this semiconductor device can not closed.

In certain embodiments, process 3402 can comprise that (a) combines to form a kind of the second feed gas that comprises argon gas and 2 percent (volume) oxygen by oxygen and this first feed gas, and (b) with this second feed gas sputtering target material in this vacuum chamber in this vacuum chamber.In various embodiments, process 3402 can directly occur in after process 3401.For example, can implementation 3402 to make the oxygen providing in process 3402 add simply the first feed gas to, so that process 3401 is directly transformed into process 3402.

In a lot of embodiment, process 3401 and/or process 3402 can occur being more than or equal to approximately 10 millitorrs and being less than or equal under the pressure of approximately 20 millitorrs.In identical or different embodiment, process 3401 and/or process 3402 can occur under the pressure of approximately 16 millitorrs.In identical or different embodiment, process 3401 and/or process 3402 can be more than or equal to approximately 25 degrees Celsius and be less than or equal at the temperature of approximately 39 degrees Celsius and occur.

The step 3105 of Figure 34 can be included on this second active layer and/or this first active layer the process 3403 of deposition and the second photoresist layer that develops.In certain embodiments, this second photoresist layer can be with as above similar or identical with respect to the first photoresist layer described in process 4902.In a lot of embodiment, process 3403 can be included in deposition and the second photoresist layer that develops on an etching stopping layer, this second active layer and/or this first active layer.In a lot of embodiment, this etching stopping layer and etching stopping layer 3511(Figure 35) similar or identical.

The step 3105 of Figure 34 can be included in this second photoresist layer process 3404 with this second active layer of a kind of the second etchant etching and this first active layer as second etching mask time.In a lot of embodiment, process 3404 can comprise when this second photoresist layer is used as to the second etching mask with this this etching stopping layer of the second etchant etching, this second active layer and this first active layer.In a lot of embodiment, can use AMAT8330 implementation 3404.In certain embodiments, this second etchant can comprise dry ecthing agent.In identical or different embodiment, this dry ecthing agent can comprise oxygen, hydrogen chloride and methane.In identical or different embodiment, oxygen, hydrogen chloride and methane can comprise ten of per unit volumes, 100 and 20 parts.In a lot of embodiment, implementation 3404 can with etching ITO layer 2565(Figure 25, as mentioned above) similar or identical.

In certain embodiments, process 3403 and process 3404 can be in the rear execution of process 3401 and can be in the rear repetition of process 3402.In identical or different embodiment, two kinds of situations that this second photoresist and/or this second etchant are carried out respectively for process 3403 and process 3404 can be identical, or wherein one or both can be different.In other embodiments, process 3403 and process 3404 only can be carried out after process 3401 and process 3402 all complete.

Figure 47 has shown an example of

implementation

3401 and 3402 rear semiconductor device 3200.For example, with reference to Figure 47, the first active layer 4706 can be on gate metal layer 3202 and/or the second active layer 4707 can be on the first active layer 4706.In various embodiments, the first active layer 4706 comprises at least one first metal oxide and comprises first conductivity.In identical or different embodiment, the second active layer 4707 comprises at least one second metal oxide and comprises second conductivity.Although not shown in Figure 47, in certain embodiments, the etching stopping layer similar or identical with etching stopping layer 3511 can be on the second active layer 4707 and/or above.

In a lot of examples, oxide and different conductivity can be improved to mobility, ON/OFF current ratio and the stability of the active layer being comprised of amorphous silicon for the first active layer 4706 and/or the second active layer 4707.Its possibility of result is less semiconductor device and the monitor resolution of raising.

In a lot of embodiment, this at least one first metal oxide can comprise one or more in indium oxide, zinc oxide, gallium oxide, tin oxide, hafnium oxide, aluminium oxide, each other be in equal proportions or unequal.For example in certain embodiments, this at least one first metal oxide comprises 60 approximately percent zinc oxide and 40 approximately percent indium oxide.In other examples, this at least one first metal oxide comprises indium oxide, gallium oxide and the zinc oxide that ratio is equal to each other.In various embodiments, this at least one second metal oxide can comprise this at least one first metal oxide.At this, at least one second metal oxide comprises in the identical or different embodiment of this at least one the first metal oxide, this at least one second metal oxide can comprise the component cpd/element of this at least one the first metal oxide, but the ratio of these component cpd/elements that comprise is different, or this at least one second metal oxide not only can comprise the component cpd/element of this at least one the first metal oxide but also can comprise the relative scale of these component cpd/elements.In other embodiments, this at least one second metal oxide can be that at least one first metal oxide is different from this, at least one first metal oxide with respect to this, this at least one second metal oxide comprises at least one different component cpd/element of at least one first metal oxide from this, and/or the different proportion of this at least one the second metal oxide (for example, this at least one first metal oxide comprises that 60 approximately percent zinc oxide and indium oxide and this at least one second metal oxide of 40 approximately percent comprise the indium oxide being in equal proportions each other, gallium oxide, situation with zinc oxide, or vice versa).In other examples, difference can be more delicate, for example this at least one second metal oxide and this at least one first metal oxide comprise zinc oxide and indium oxide, but the zinc oxide of this at least one the second metal oxide and the ratio of indium oxide are about 60:40, and the zinc oxide of this at least one the first metal oxide and the ratio of indium oxide are about 59:41.

In a lot of embodiment, transistor active layer 3505 can be more than or equal to approximately 40 nanometer thickness and be less than or equal to approximately 60 nanometer thickness.In a further embodiment, transistor active layer 3505 can be approximately 50 nanometer thickness.In identical or different embodiment, the first active layer 4706 can be more than or equal to approximately 5 nanometer thickness and be less than or equal to approximately 40 nanometer thickness.In a further embodiment, the first active layer 4706 can be more than or equal to approximately 5 nanometer thickness and be less than or equal to approximately 20 nanometer thickness.Correspondingly, at the first active layer 4706, be in a lot of embodiment of for example 25 nanometer thickness, the second active layer 4707 can be approximately 25 nanometer thickness.At the first active layer 4706, be in the further example of 40 nanometer thickness, the second active layer 4707 can be approximately 10 nanometer thickness.

In a lot of embodiment, the first active layer 4706 comprises first conductivity.For example, this first conductivity is approximately 0.002 ohm-cm.In identical or different embodiment, the second active layer 4707 comprises second conductivity.For example, this second conductivity can be more than or equal to approximately 10 ohm-cms and be less than or equal to approximately 200 ohm-cms.In various embodiments, this first conductivity is greater than this second conductivity.In other embodiments, this first conductivity is less than this second conductivity.

Referring back to Figure 31, method 3100 can be included in the step 3106 that an etching stopping layer is provided on this transistor active layer, this first active layer and/or this second active layer and/or in this transistor active layer, this first active layer and/or this second active layer now.In a lot of embodiment, before step 3106 occurs in step 3107 and/or 3108 and/or after step 3105.Etching stopping layer can be with as similar or identical in the etching stopping layer 3511 of being shown in Figure 35 and Figure 36.Figure 35 and Figure 36 have shown the example that semiconductor device 3200 after an etching stopping layer is provided on this transistor active layer.

For example, with reference to Figure 35 and Figure 36, gate blocks layer 3510 can be on gate metal layer 3202 and/or barrier layer 3209 and/or above, below transistor active layer 3505, and/or between gate metal layer 3202 and transistor active layer 3505.In various embodiments, gate blocks layer 3510 can with gate dielectric 1554(Figure 15) similar or identical.In a lot of embodiment, gate blocks layer 3510 can comprise a kind of the second dielectric material.This second dielectric material can comprise silicon dioxide.Can with silicon nitride or other dielectrics with the nearest side of gate metal layer 3502 on buffered gate barrier layer 3510.In identical or different embodiment, gate metal layer 3510 can be more than or equal to approximately 100 nanometer thickness and be less than or equal to approximately 300 nanometer thickness.

Referring again to Figure 35 and Figure 36, in certain embodiments, transistor active layer 3505 can be on gate metal layer 3202 and/or can be on gate blocks layer 3510 and/or above.As mentioned above, transistor active layer 3505 can comprise first active layer 4706(Figure 47) and second active layer 4707(Figure 47).

Referring again to Figure 35 and Figure 36, in certain embodiments, etching stopping layer 3511 can be on transistor active layer 3505.In identical or different embodiment, etching stopping layer 3511 can be at least a portion of transistor active layer 3505 and/or gate blocks layer 3510 and/or above, at source/drain contact layer 4150(Figure 41 and Figure 42) below, and/or between this part and source/drain contact layer 4150 of transistor active layer 3505.In various embodiments, etching stopping layer 3511 can with IMD layer 1556(Figure 15) similar or identical.In a lot of embodiment, etching stopping layer 3511 can comprise a kind of the 3rd dielectric material.The 3rd dielectric material can comprise silicon dioxide.Can with silicon nitride with the nearest side of source/drain contact layer 4150 on cushion etching stopping layer 3511.In identical or different embodiment, etching stopping layer 3511 can be more than or equal to approximately 50 nanometer thickness and be less than or equal to approximately 200 nanometer thickness.In a further embodiment, etching stopping layer 3511 can be approximately 100 nanometer thickness.

Now referring back to Figure 31, method 3100 can be included on this etching stopping layer and/or top provides the step 3107 of mesa passivation layer.In a lot of embodiment, step 3107 can be similar or identical with (Figure 12) activity 1213.In a lot of embodiment, before step 3107 occurs in step 3108 and/or after step 3106.This mesa passivation layer can be with as similar or identical in the mesa passivation layer 3712 of being shown in Figure 37 and Figure 38.Figure 37 and Figure 38 shown on this etching stopping layer and/or above an example of semiconductor device 3200 after a mesa passivation layer is provided.

For example, with reference to Figure 37 and Figure 38, mesa passivation layer 3712 can be on etching stopping layer 3511 and/or above, below source/drain contact layer 4150 (Figure 41 and Figure 42), and/or between etching stopping layer 3511 and source/drain contact layer 4150.In various embodiments, mesa passivation layer 3712 can with mesa passivation layer 1757(Figure 17) similar or identical.In a lot of embodiment, mesa passivation layer 3712 can comprise a kind of the 4th dielectric material.The 4th dielectric material can comprise silicon dioxide.In identical or different embodiment, mesa passivation layer 3712 can be more than or equal to approximately 50 nanometer thickness and be less than or equal to approximately 200 nanometer thickness.In a further embodiment, mesa passivation layer 3712 can be approximately 100 nanometer thickness.Mesa passivation layer 3712 can be in etching process the sidewall of protective transistor active layer 3505.

In a lot of embodiment, method 3100 can comprise carries out as mentioned above and movable 1214(Figure 12) the similar or identical etched step 3108 of one or more rear table top passivation layer.Figure 39 and Figure 40 have shown the cross-sectional view that carries out semiconductor device 3200 after the etching of one or more rear table top passivation layer.For example, Figure 40 has shown the semiconductor device 3200 there is contact gate etch in the gate contacts of semiconductor device 3200 builds district after.In identical or different example, Figure 39 has shown that device has occurred in the device of semiconductor device 3200 builds district builds contact regions etching semiconductor device 3200 afterwards.After step 3109, can on semiconductor device 3200, form gate contacts 4091.Gate contacts 4091 is associated with the gate contacts district 4681 of Figure 46.After step 3109, can on semiconductor device 3200, form a plurality of devices and build contact 3990.Device builds contact 3990 and is associated with the device structure contact regions 4680 of Figure 46.

Referring back to Figure 31, method 3100 is included in the step 3109 that source/drain contact layer is provided on this transistor active layer, this first active layer and/or this second active layer now.In identical or different embodiment, step 3109 can comprise in the part of this transistor active layer and/or provide this source/drain contact layer on this mesa passivation layer.In certain embodiments, step 3109 can with process 1113(Figure 11) similar or identical, and source/drain contact layer can with source/drain contact layer 4150(Figure 41) similar or identical.Figure 48 is a flow chart, has shown the step 3109 that a source/drain contact layer is provided on this transistor active layer, this first active layer and/or this second active layer according to an embodiment.

With reference to Figure 48, in certain embodiments, step 3109 can be included on this transistor active layer, this first active layer and/or this second active layer and deposit one or more metal levels.In identical or different embodiment, step 3109 can be included in the process 4801 that deposits a first metal layer on this transistor active layer, this first active layer and/or this second active layer.In certain embodiments, process 4801 can be included on this transistor active layer, this first active layer and/or this second active layer and deposit a first metal layer, to form source/drain contact layer.In a further embodiment, process 3109 can be included on this first metal layer and deposit second metal level, with the process 4802 from this first metal layer and this second metal level formation source/drain contact layer.In certain embodiments, this first metal layer comprises that molybdenum and this second metal level comprise aluminium.In certain embodiments, process 3109 can be included on this source/drain contact layer the process 4803 of deposition and the 3rd photoresist layer that develops.In further embodiment, when step 3109 can be included in the 3rd photoresist layer as the 3rd etching mask by a kind of process 4804 of the 3rd this source/drain contact layer of etchant etching.In certain embodiments, can omit process 4802.In a lot of embodiment, the 3rd etchant can be dry ecthing agent.In identical or different embodiment, dry ecthing agent can comprise chlorine and boron chloride and/or chlorine and oxygen.In identical or different embodiment, chlorine and boron chloride can for example, can be used for this second metal level of etching for this first metal layer of etching (, aluminium) and chlorine and oxygen.

Figure 41 has shown that step 3109 completes the cross-sectional view in the device structure district of an example of semiconductor device 3200 afterwards.In addition, Figure 42 has shown that step 3109 completes the cross-sectional view in the gate contacts structure district of an example of semiconductor device 3200 afterwards.

For example, with reference to Figure 41 and Figure 42, source/drain contact layer 4150 can be on transistor active layer 3505.In identical or different embodiment, source/drain contact layer 4150 can be on transistor active layer 3505.Referring back to Figure 31, in various embodiments, source/drain contact layer 4150 can comprise the first source/drain contact 4104 and/or the second source/drain contact 4105.In certain embodiments, the first source/drain contact 4104 can comprise that a transistor drain contact and the second source/drain contact 4105 can comprise a transistor source contact, or vice versa.In identical or different embodiment, source/drain contact layer 4150 can the one or both in mesa passivation layer 3712 and transistor active layer 3505 on and/or above.In various execution modes, source/drain contact layer 4150 can comprise at least one in molybdenum or aluminium.In identical or different embodiment, source/drain contact layer 4150 can be more than or equal to approximately 100 nanometer thickness and be less than or equal to approximately 200 nanometer thickness.In a further embodiment, source/drain contact layer 4150 can be approximately 150 nanometer thickness.

Referring back to Figure 31, method 3100 can comprise Figure 11 with process 1198(now) the similar or identical step 3110 that a kind of base dielectric is provided.In identical or different embodiment, method 3100 can comprise Figure 11 with process 1114() the similar or identical step 3111 that a kind of the 5th dielectric material is provided.In identical or different embodiment, method 3100 can comprise Figure 11 with process 1115() step of similar or identical baking semiconductor device.In identical or different embodiment, method 3100 can comprise Figure 11 with process 1116() the similar or identical step 3112 of solidifying the 5th dielectric material.In identical or different embodiment, method 3100 can comprise Figure 11 with process 1117() the similar or identical step 3113 that a kind of the 6th dielectric material is provided.In identical or different embodiment, method 3100 can comprise Figure 11 with process 1118() similar or identical a kind of step 3114 of mask that provides on the 6th dielectric material.In identical or different embodiment, method 3100 can comprise Figure 11 with process 1119() step 3115 of similar or identical this base dielectric of etching, the 5th dielectric material and the 6th dielectric material.In identical or different embodiment, method 3100 can comprise Figure 11 with process 1120() step 3116 of similar or identical this mask of removal.In identical or different embodiment, method 3100 can comprise Figure 11 with process 1121() the similar or identical step 3117 that one or more semiconductor elements are provided.In various embodiments, can omit the one or more steps in step 3110-3117.

Figure 43 has shown that the device of example of semiconductor device 3200 after execution step 3101-3116 builds the cross-sectional view in district.With reference to Figure 43, dielectric material 4399, the 5th dielectric material 4361 and the 6th dielectric material 4362 are deposited on source/drain contact layer 4150.Dielectric material 4399, the 5th dielectric material 4361 and/or the 6th dielectric material 4362 can be respectively and dielectric material 2499(Figure 24), first dielectric material 2461(Figure 24) and/or second dielectric material 2462(Figure 24) similar.Step 3114(Figure 31), after, semiconductor device 3200 can comprise through hole 4363, these through holes can with through hole 2463(Figure 24) similar or identical, as shown in figure 43.Through hole 4363 is associated with the through hole area 4682 of Figure 46.Mask in Figure 43 on not shown the 6th dielectric layer 4362.

In one embodiment, Figure 44 has shown that the device of an example that performs step 3117 rear semiconductor device 3200 builds the cross-sectional view in district.With reference to Figure 44, the 3rd metal level 4464 and ITO layer 4465 can be arranged on the 6th dielectric material 4362.In identical or different embodiment, the 3rd metal level 4464 can be arranged on the 6th dielectric material 4362, and at least in part at through hole 4363(Figure 43) in.In a lot of embodiment, the 3rd metal level 4464 and ITO layer 4465 can be respectively and second metal level 2564(Figure 25) and ITO layer 2565(Figure 25) similar.

In another different embodiment of the embodiment from Figure 44, Figure 45 has shown that the device of another example that performs step 3117 rear semiconductor device 3200 builds the cross-sectional view in district.With reference to Figure 45, silicon nitride layer 4566 can be arranged on ITO layer 4465.

Although described the present invention with reference to specific embodiment, it should be understood that those skilled in the art can carry out various changes and not depart from the spirit and scope of the present invention.Therefore, the disclosure of the present embodiment is intended to describe scope of the present invention and does not lie in restriction.Should notice that scope of the present invention should only limit to the desired content of claims.For those skilled in the art, to easily be apparent that the semiconductor device of discussing at this and provide the method for semiconductor device to be implemented in various embodiments, and the aforementioned discussion of some embodiment of these embodiment not necessarily shows all may embodiment one and describes completely.On the contrary, the detailed description of accompanying drawing and accompanying drawing self have disclosed at least one preferred embodiment, and can disclose alternate embodiment.For example, except they active layers separately, semiconductor device 1350(is as Figure 13-22, Figure 24-26 and Figure 29) and 3200(Figure 32-33 and Figure 35-47) can be similar or identical each other, and method 120(Figure 11) and 3100(Figure 31) can be similar or identical each other.

Whole elements of mentioning in any concrete right requires are that this privilegium requires the embodiment mentioning necessary.Therefore, the alternative form of one or more mentioned element forms reconstruct and needn't repair.The solution of benefit, other advantages and problem has been described about specific embodiment in addition.Yet can not think that can cause any benefit, advantage or solution generation or the more obvious benefit that becomes, advantage, issue-resolution and any element or a plurality of element is crucial, that require or main feature or the element of any or all of claim, unless clearly stated this type of benefit, advantage, solution or element in this type of claim.

In addition, if by embodiment and/or restriction as follows: this disclosed embodiment and restriction be not under special-purpose principle by masses special use: (1) is not clearly mentioned in the claims; And (2) are or are the element of expressing in claim and/or the potential equivalent of restriction under equivalence principle.

Claims

1. an electronic installation, comprising:

Transistor, this transistor comprises:

Gate metal layer;

Transistor active layer on this gate metal layer; And

Source/drain contact layer on this transistor active layer, this source/drain contact layer comprises the first source/drain contact and the second source/drain contact;

Wherein:

This transistor active layer comprises:

The first active layer on this gate metal layer, this first active layer comprises at least one first metal oxide; And

The second active layer on this first active layer, this second active layer comprises at least one second metal oxide;

This first active layer comprises the first conductivity;

This second active layer comprises the second conductivity; And

This first conductivity is greater than this second conductivity.

2. electronic installation as claimed in claim 1, further comprises:

Substrate;

Wherein:

This gate metal layer is on this substrate;

This substrate comprises in rigid substrate or flexible substrate;

When this substrate comprises this rigid substrate, this rigid substrate comprises silicon; And

When this substrate comprises this flexible substrate, this flexible substrate comprises a kind of in plastics or stainless steel, and these plastics comprise polyethylene naphthalenedicarboxylate.

3. electronic installation as claimed in claim 1 or 2, wherein:

This transistor active layer is in this gate metal layer;

This first source/drain contact is on this transistor active layer; And

This second source/drain contact is on this transistor active layer.

4. electronic installation as claimed any one in claims 1 to 3, further comprises:

Liquid crystal display, electrophoretic display device (EPD) or comprise in this transistorized organic light emitting diode display.

5. the electronic installation as described in any one in claim 1 to 4, wherein:

This at least one first metal oxide comprises at least one in indium oxide, zinc oxide, gallium oxide, tin oxide, hafnium oxide or aluminium oxide.

6. the electronic installation as described in any one in claim 1 to 5, wherein:

This at least one first metal oxide comprises about zinc oxide of 60 percent and about indium oxide of 40 percent.

7. the electronic installation as described in any one in claim 1 to 6, wherein:

This at least one first metal oxide comprises indium oxide, gallium oxide and the zinc oxide that ratio is equal to each other.

8. the electronic installation as described in any one in claim 1 to 7, wherein:

This at least one second metal oxide comprises this at least one first metal oxide.

9. the electronic installation as described in any one in claim 1 to 8, wherein:

This first active layer is more than or equal to approximately 5 nanometer thickness and is less than or equal to approximately 40 nanometer thickness.

10. electronic installation as claimed in any one of claims 1-9 wherein, wherein:

This transistor active layer is more than or equal to approximately 40 nanometer thickness and is less than or equal to approximately 60 nanometer thickness.

11. electronic installations as described in any one in claim 1 to 10, wherein:

This gate metal layer comprises at least one in molybdenum, aluminium, tantalum, chromium or tungsten.

12. electronic installations as described in any one in claim 1 to 11, wherein:

This source/drain contact layer comprises at least one in molybdenum or aluminium; And

This source/drain contact layer is more than or equal to approximately 100 nanometer thickness and is less than or equal to approximately 200 nanometer thickness.

13. electronic installations as described in any one in claim 1 to 12, further comprise:

Barrier layer;

Wherein:

This gate metal layer is on this barrier layer;

This barrier layer comprises a kind of the first dielectric material;

This first dielectric material comprises at least one in silicon dioxide or silicon nitride; And

This barrier layer is more than or equal to approximately 200 nanometer thickness and is less than or equal to approximately 400 nanometer thickness.

14. electronic installations as described in any one in claim 1 to 13, further comprise:

Gate blocks layer between this gate metal layer and this transistor active layer;

Wherein:

This gate blocks layer comprises a kind of the second dielectric material;

This second dielectric material comprises silicon dioxide; And

This gate blocks layer is more than or equal to approximately 100 nanometer thickness and is less than or equal to approximately 300 nanometer thickness.

15. electronic installations as described in any one in claim 1 to 14, further comprise:

Etching stopping layer on this transistor active layer;

Wherein:

This etching stopping layer is in the part of (a) this transistor active layer and (b) between this source contact and this drain contact;

This etching stopping layer comprises a kind of the 3rd dielectric material;

The 3rd dielectric material comprises silicon dioxide; And

This etching stopping layer is more than or equal to approximately 50 nanometer thickness and is less than or equal to approximately 200 nanometer thickness.

16. electronic installations as claimed in claim 15, further comprise:

Mesa passivation layer on this etching stopping layer;

Wherein:

This mesa passivation layer is at (a) this etching stopping layer and (b) between this source/drain contact layer;

This mesa passivation layer comprises a kind of the 4th dielectric material;

The 4th dielectric material comprises silicon dioxide; And

This mesa passivation layer is more than or equal to approximately 50 nanometer thickness and is less than or equal to approximately 200 nanometer thickness.

17. 1 kinds of semiconductor device, comprising:

Substrate;

Barrier layer on this substrate;

Gate metal layer on this barrier layer;

Gate blocks layer in this gate metal layer;

Transistor active layer on this gate blocks layer;

Etching stopping layer on this transistor active layer;

Mesa passivation layer on this etching stopping layer; And

Source/drain contact layer on this mesa passivation layer and this transistor active layer;

Wherein:

This transistor active layer comprises:

The first active layer, this first active layer, in this gate metal layer, comprises at least one first metal oxide; And

The second active layer, this second active layer is on this first active layer and between this first active layer and this etching stopping layer, and this second active layer comprises at least one second metal oxide;

This first active layer comprises the first conductivity;

This second active layer comprises the second conductivity; And

This first conductivity is greater than this second conductivity.

18. semiconductor device as claimed in claim 17, wherein:

19. semiconductor device as described in claim 17 or 18, wherein:

20. semiconductor device as described in any one in claim 17 to 19, wherein:

21. semiconductor device as described in any one in claim 17 to 20, wherein:

22. 1 kinds of methods of manufacturing semiconductor device, the method comprises:

Substrate is provided;

On this substrate, provide gate metal layer;

The first active layer is provided on this gate metal layer, and this first active layer comprises at least one first metal oxide and the first conductivity;

On this first active layer, provide the second active layer, this second active layer comprises at least one second metal oxide and is less than the second conductivity of this first conductivity; And

On this second active layer, provide source/drain contact layer.

23. methods as claimed in claim 22, wherein:

This substrate comprises in rigid substrate or flexible substrate;

24. methods as described in claim 22 or 23, wherein:

On this substrate, provide gate metal layer to comprise:

On this substrate, deposit at least one in molybdenum, aluminium, tantalum, chromium or tungsten;

Deposition and the first photoresist layer that develops on this gate metal layer; And

When this first photoresist layer is used as to the first etching mask, by a kind of this gate metal layer of the first etchant etching.

25. methods as described in any one in claim 22 to 24, wherein:

On this first active layer, provide this second active layer to comprise:

On this first active layer, deposit this at least one second metal oxide;

Deposition and the second photoresist layer that develops on this second active layer; And

When this second photoresist layer is used as to the second etching mask, with this second active layer of a kind of the second etchant etching and this first active layer.

26. methods as described in any one in claim 22 to 25, wherein:

On this second active layer, provide source/drain contact layer to comprise:

On this second active layer, deposit at least one in molybdenum or aluminium;

Deposition and the 3rd photoresist layer that develops on this source/drain contact layer; And

When the 3rd photoresist layer is used as to the 3rd etching mask, with a kind of this source/drain contact layer of the 3rd etchant etching.

27. methods as described in any one in claim 22 to 26, wherein:

On this gate metal layer, provide this first active layer to comprise:

At internal vacuum chamber, this substrate is positioned; And

At a kind of target material of this internal vacuum chamber sputter, this target material comprises at least one in indium oxide, zinc oxide, gallium oxide, tin oxide, hafnium oxide, aluminium oxide, and wherein a kind of the first unstripped gas comprises argon gas.

28. methods as claimed in claim 27, wherein:

On this first active layer, provide this second active layer to comprise:

With oxygen, combine to form a kind of the second unstripped gas with this first unstripped gas, this second group of unstripped gas comprises the oxygen that argon gas and volume are 2 percent; And

With this second unstripped gas of this internal vacuum chamber at this this target material of internal vacuum chamber sputter.

29. methods as described in any one in claim 22 to 28, wherein:

30. methods as described in any one in claim 22 to 29, wherein:

The first active layer is provided on this gate metal layer and on this first active layer, provides the second active layer to be more than or equal to approximately 10 millitorrs and to be less than or equal to the pressure of approximately 20 millitorrs and to be more than or equal to approximately 25 degrees Celsius and be less than or equal to the temperature of approximately 39 degrees Celsius and occur.

31. according to the method described in any one in claim 22 to 30, further comprises:

On this substrate, provide at least one layer material to comprise at least one in following content:

Before being provided on this substrate, this gate metal layer on this substrate, provide ，Gai barrier layer, barrier layer to comprise at least one in silicon dioxide or silicon nitride;

Before this first active layer is provided on this gate metal layer, provide gate blocks layer on this gate metal layer, this gate blocks layer comprises silicon dioxide;

Before this source/drain contact layer is provided on this second active layer, on this second active layer, provide etching stopping layer, this etching stopping layer comprises silicon dioxide; And

Mesa passivation layer is provided on this etching stopping layer, and this mesa passivation layer comprises silicon dioxide.

32. according to the method described in any one in claim 23 to 30, further comprises:

On this substrate, provide this at least one layer material to comprise at least one in following content:

Before this first active layer is provided on this gate metal layer, provide gate blocks layer in this gate metal layer, this gate blocks layer comprises silicon dioxide;

33. methods as described in any one in claim 22 to 32, wherein:

On this substrate, providing this gate metal layer to be included in provides this gate metal layer on this barrier layer;

On this gate metal layer, providing this first active layer to be included in provides this first active layer on this gate blocks layer; And

On this first active layer, providing the second active layer to be included in provides this second active layer on this first active layer.