JP2009224479A - Thin film field-effect transistor and method of manufacturing the same - Google Patents

Thin film field-effect transistor and method of manufacturing the same Download PDF

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JP2009224479A
JP2009224479A JP2008066069A JP2008066069A JP2009224479A JP 2009224479 A JP2009224479 A JP 2009224479A JP 2008066069 A JP2008066069 A JP 2008066069A JP 2008066069 A JP2008066069 A JP 2008066069A JP 2009224479 A JP2009224479 A JP 2009224479A
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thin film
effect transistor
insulating film
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gate insulating
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JP5467728B2 (en
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Masaya Nakayama
昌哉 中山
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Fujifilm Corp
富士フイルム株式会社
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Abstract

An object of the present invention is to provide a TFT having a high field effect mobility, a high ON / OFF ratio, and an improved environmental temperature dependency. And a display device using the same.
A thin film field effect transistor having a gate electrode, a gate insulating film, an active layer made of an amorphous oxide semiconductor, a source electrode, and a drain electrode on a substrate, wherein the dangling bond density of the gate insulating film is 5 A thin film field-effect transistor characterized in that it is × 10 16 cm −3 or less and the hydrogen concentration in the gate insulating film is 1 × 10 19 cm −3 or less.
[Selection figure] None

Description

  The present invention relates to a thin film field effect transistor and a method for manufacturing the same. In particular, the present invention relates to a thin film field effect transistor using an amorphous oxide semiconductor as an active layer and a method for manufacturing the same.

2. Description of the Related Art In recent years, flat and thin image display devices (Flat Panel Displays: FPD) have been put into practical use due to advances in liquid crystal and electroluminescence (EL) technologies. In particular, an organic electroluminescent device using a thin film material that emits light when excited by passing an electric current (hereinafter sometimes referred to as “organic EL device”) can emit light with high luminance at a low voltage. Device thinning, lightening, miniaturization, and power saving are expected in a wide range of fields including mobile phone displays, personal digital assistants (PDAs), computer displays, automobile information displays, TV monitors, or general lighting. ing.
These FPDs are active field-effect thin film transistors (hereinafter referred to as “Thin Film Transistor” or “TFT”) that use an amorphous silicon thin film or a polycrystalline silicon thin film provided on a glass substrate as an active layer. It is driven by a matrix circuit.

On the other hand, in order to further reduce the thickness, weight, and breakage resistance of these FPDs, an attempt has been made to use a lightweight and flexible resin substrate instead of a glass substrate.
However, the manufacture of the transistor using the above-described silicon thin film requires a relatively high temperature thermal process and is generally difficult to form directly on a resin substrate having low heat resistance.
Thus, research and development of thin film transistors using an oxide semiconductor typified by ZnO, which can be formed at a low temperature, as active layers have been actively conducted in recent years. In particular, amorphous oxide semiconductors such as In-Ga-Zn-O-based amorphous oxides can be formed on a resin substrate at room temperature because they can be formed at a low temperature and have high in-plane property uniformity and high mobility. Attention has been focused on as an active layer material of a film-capable transistor, and TFTs using an amorphous oxide semiconductor as an active layer are being actively developed (for example, see Non-Patent Document 1).

TFTs using these amorphous oxide semiconductors for the channel have a problem that hysteresis occurs in TFT characteristics (Id-Vg characteristics) depending on the composition and manufacturing conditions. For example, a field effect transistor having a channel layer of an amorphous oxide film containing In or Zn, wherein the amorphous oxide film contains hydrogen atoms or deuterium atoms of 10 16 cm −3 or more and 10 20 cm −3 or less Thus, it is disclosed that the hysteresis of transistor characteristics is improved (see, for example, Patent Document 1).

In addition, as a gate insulating film of a thin film transistor made of an oxide semiconductor and a manufacturing method thereof, for example, a semiconductor thin film made of an oxide mainly composed of zinc oxide ZnO and a gate insulating film made of a silicon-based insulating film and in contact with the semiconductor thin film A thin film transistor is disclosed, and as a method of manufacturing the thin film transistor, the formation of the semiconductor thin film and the formation of the gate insulating film are performed in a continuous process in a vacuum, and the gate insulating film is inductively coupled plasma enhanced chemical vapor phase. A method of manufacturing a thin film transistor is disclosed which is formed by a growth (ICP-CVD) method or an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method, and the entire manufacturing process is performed under a temperature condition of 200 ° C. or less (for example, , See Patent Document 2).
JP 2007-103918 A JP 2007-73559 A NATURE, Vol. 432 (25 November, 2004), P.M. 488-492

  An object of the present invention is to provide a TFT using an amorphous oxide semiconductor having a low OFF current, a high ON / OFF ratio, and a characteristic change caused by driving, in particular, a small threshold voltage fluctuation. Moreover, it is providing the manufacturing method of the TFT.

The above-described problems of the present invention have been solved by the following means.
<1> A thin film field effect transistor having a gate electrode, a gate insulating film, an active layer made of an amorphous oxide semiconductor, a source electrode, and a drain electrode on a substrate, wherein the dangling bond density of the gate insulating film is 5 ×. 10. The thin film field-effect transistor is characterized by being 10 16 cm −3 or less and a hydrogen concentration in the gate insulating film being 1 × 10 19 cm −3 or less.
<2> The thin film field effect transistor according to <1>, wherein the gate insulating film contains a Si compound as an insulating film material.
<3> The thin film field effect transistor according to <2>, wherein the Si compound is silicon oxide (SiO x ).
<4> The thin-film field effect transistor according to any one of <1> to <3>, wherein a hydrogen concentration in the gate insulating film is less than 10 18 cm −3 .
<5> The thin film electric field according to any one of <1> to <4>, wherein the amorphous oxide semiconductor of the active layer includes at least one selected from the group consisting of In, Ga, Zn, and Sn. Effect transistor.
<6> The thin film field effect transistor according to <5>, wherein the amorphous oxide semiconductor of the active layer contains In.
<7> The thin film field effect transistor according to <6>, wherein the amorphous oxide semiconductor further contains Zn or Ga.
<8> The thin film field effect transistor according to <6>, wherein the amorphous oxide semiconductor further contains Zn and Ga.
<9> The thin film field effect transistor according to any one of <1> to <8>, wherein a resistance layer is provided between the active layer and at least one of the source electrode and the drain electrode.
<10> The method for manufacturing a thin film field effect transistor according to any one of <1> to <9>, wherein a flow rate ratio of oxygen gas to Ar gas (O 2 flow rate / Ar flow rate) is set in the gate insulating film. A method for manufacturing a thin film field effect transistor, characterized by being formed by sputtering in an atmosphere of 10% or more.
<11> The method for producing a thin film field effect transistor according to <10>, wherein the gate insulating film is formed at a temperature of 150 ° C. or lower.

A TFT using an amorphous oxide semiconductor can be formed at room temperature and can be manufactured using a flexible plastic film as a substrate, and thus has attracted attention as a material for an active layer of a film (flexible) TFT. In particular, as disclosed in JP-A Nos. 2006-165529 and 2006-186319, an amorphous oxide semiconductor having a carrier concentration of less than 10 18 / cm 3 is used as an active layer on a polyester film substrate. A TFT having an effective mobility of 10 cm 2 / Vs and an ON / OFF ratio exceeding 10 3 has been reported.

  However, as a result of detailed analysis of the operating characteristics of these TFTs by the present inventors, it has been found that the TFT threshold voltage fluctuates when the TFT is repeatedly driven for a long time. The variation in the threshold voltage of the TFT is a very serious problem to be solved because it causes unevenness in light emission when used in a current value driving type display device such as an organic EL display device.

The present inventors made efforts to solve this problem from all points of view. In general, it was considered a problem of the active layer material, and the improvement of the active layer material was continued. However, the present inventors have unexpectedly discovered that the gate insulating film adjacent to the active layer affects the fluctuation of the threshold voltage. Furthermore, as a result of continual improvement, the present invention has been achieved. In particular, it has been found that by reducing the Si dangling bond density and the hydrogen concentration in the gate insulating film, fluctuations in the threshold voltage can be suppressed while maintaining a low off-current / high ON / OFF ratio. Specifically, by setting the Si dangling bond density in the gate insulating film to 5 × 10 16 cm −3 or less, fluctuation of the threshold voltage is suppressed, and the hydrogen concentration in the gate insulating film is set to 1 × 10 19. By making it less than cm −3 , it is possible to maintain a low off-current and a high ON / OFF ratio. Moreover, the manufacturing method of the gate insulating film was discovered.

Japanese Patent Application Laid-Open No. 2007-103918 discloses that an electron carrier concentration can be controlled by the amount of hydrogen dopant in a TFT using an amorphous oxide film as an active layer, and an electron carrier concentration of about 10 18 / cm 3 is realized. In order to do so, it is disclosed that hysteresis can be improved by adding hydrogen of 10 18 cm −3 or more and 10 20 cm −3 or less. However, although the conditions regarding the channel layer are specified, the involvement of the gate insulating film is not taught at all from the viewpoint of improving the hysteresis.

  According to the present invention, a TFT having a low OFF current, a high ON / OFF ratio, and excellent continuous drive stability is provided. In particular, a thin film field effect transistor useful as a film (flexible) TFT using a flexible substrate is provided. In addition, a display device using these TFTs is provided.

1. Thin film field effect transistor (TFT)
The TFT of the present invention has at least a gate electrode, a gate insulating film, an active layer, a source electrode, and a drain electrode in order, and controls the current flowing through the active layer by applying a voltage to the gate electrode, It is an active element having a function of switching a current between electrodes. As the TFT structure, either a staggered structure or an inverted staggered structure can be formed.
The TFT of the present invention will be described in detail.

1) Gate Insulating Film The gate insulating film in the present invention has a dangling bond density of 5 × 10 16 cm −3 or less and a hydrogen concentration in the gate insulating film of 10 19 cm −3 or less.
The dangling bond density is the density of dangling bonds in the insulating material constituting the gate insulating film. For example, in the case of silicon oxide (SiO 2 ), the density of dangling bonds of Si that is not covalently bonded to oxygen. It is.

The dangling bond density in the present invention is a value obtained by the following measurement.
<Dangling bond density measurement method>
The dangling bond in the gate insulating film can be measured by ESR (electron spin resonance method).
The dangling bond density in the present invention is preferably 5 × 10 16 cm −3 or less, more preferably 3 × 10 16 cm −3 or less.

The hydrogen concentration in the present invention is a value obtained by the following measurement.
<Measurement method of hydrogen concentration>
The hydrogen concentration in the gate insulating film can be measured by SIMS (secondary ion mass spectrometry).
The hydrogen concentration in the gate insulating film in the present invention is preferably 1 × 10 19 cm −3 or less, more preferably less than 1 × 10 −18 cm −3 .

As an insulating material used for the gate insulating film, silicon oxide (SiO x ), silicon nitride (SiN y ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), An insulator such as tantalum oxide (Ta 2 O 5 ) or hafnium oxide (HfO 2 ), or a mixed crystal compound containing at least two of these compounds can be used.
A polymer insulator such as polyimide can also be used as the gate insulating film. A preferred insulating film material is a Si compound. Particularly preferred is silicon oxide (SiO x ). x is generally 1.7 to 2.3.

A method for manufacturing the gate insulating film will be described.
The gate insulating film having a dangling bond density of 5 × 10 16 cm −3 or less and a hydrogen concentration in the gate insulating film of 10 19 cm −3 or less of the present invention has a flow ratio of oxygen gas to Ar gas. It can be obtained by forming by sputtering in an atmosphere where (O 2 flow rate / Ar flow rate) is 10% or more.
Preferably, the O 2 flow rate / Ar flow rate is 10% or more, more preferably 13% or more. When the resin substrate is assumed, the sputtering temperature is preferably 180 ° C. or lower, and more preferably 150 ° C. or lower.
Heat treatment may be performed after the gate insulating film is formed.

  The thickness of the gate insulating film is preferably 10 nm to 10 μm. The gate insulating film needs to be thickened to some extent in order to reduce leakage current and increase voltage resistance. However, increasing the thickness of the gate insulating film results in an increase in the driving voltage of the TFT.

2) Active layer An amorphous oxide semiconductor is used for the active layer used in the present invention. Since an amorphous oxide semiconductor can be formed at a low temperature, it can be formed on a flexible resin substrate such as a plastic. Good amorphous oxide semiconductors that can be manufactured at low temperatures include oxides containing In, oxides containing In and Zn, and oxides containing In, Ga, and Zn. As the composition structure, InGaO 3 (ZnO ) M (m is a natural number of less than 6) is known to be preferable. These are n-type semiconductors whose carriers are electrons. Of course, a p-type oxide semiconductor such as ZnO.Rh 2 O 3 , CuGaO 2 , or SrCu 2 O 2 may be used for the active layer. An oxide semiconductor disclosed in JP-A-2006-165529 can also be used.

  In the present invention, an amorphous oxide semiconductor containing at least one selected from the group consisting of In, Ga, Zn, and Sn is preferable. More preferably, it is an amorphous oxide semiconductor containing In. More preferably, it is an amorphous oxide semiconductor further containing Zn or Ga in addition to In. Most preferably, the amorphous oxide semiconductor further contains Ga and Zn in addition to In.

Specifically, the amorphous oxide semiconductor according to the present invention includes In—Ga—Zn—O, and the composition in the crystalline state is represented by InGaO 3 (ZnO) m (m is a natural number of less than 6). A physical semiconductor is preferred. In particular, InGaZnO 4 is more preferable.

  The carrier concentration of the amorphous oxide semiconductor in the present invention can be adjusted to a desired value by various means.

Examples of the means for adjusting the carrier concentration of the active layer include the following means.
(1) Adjustment by oxygen defect It is known that when an oxygen defect is formed in an oxide semiconductor, the carrier concentration in the active layer increases and the electrical conductivity increases. Therefore, the carrier concentration of the oxide semiconductor can be controlled by adjusting the amount of oxygen defects. Specific methods for controlling the amount of oxygen defects include oxygen partial pressure during film formation, oxygen concentration and treatment time during post-treatment after film formation, and the like. Specific examples of post-treatment include heat treatment at 100 ° C. or higher, oxygen plasma, and UV ozone treatment. Among these methods, a method of controlling the oxygen partial pressure during film formation is preferable from the viewpoint of productivity. JP-A-2006-165529 discloses that the carrier concentration of an oxide semiconductor can be controlled by adjusting the oxygen partial pressure during film formation, and this technique can be used.

(2) Adjustment by composition ratio It is known that the carrier concentration is changed by changing the metal composition ratio of the oxide semiconductor. For example, JP 2006-165529 discloses that, in InGaZn 1-X Mg X O 4 , the carrier concentration decreases as the Mg ratio increases. In addition, in the oxide system of (In 2 O 3 ) 1-X (ZnO) X , it is reported that when the Zn / In ratio is 10% or more, the carrier concentration decreases as the Zn ratio increases ( “New development of transparent conductive film II”, CMC Publishing, P.34-35). As specific methods for changing these composition ratios, for example, in a film formation method by sputtering, targets having different composition ratios are used. Alternatively, it is possible to change the composition ratio of the film by co-sputtering with a multi-source target and individually adjusting the sputtering rate.

(3) Adjustment by impurities It is possible to reduce the carrier concentration by adding elements such as Li, Na, Mn, Ni, Pd, Cu, Cd, C, N, and P to the oxide semiconductor as impurities. This is disclosed in Japanese Patent Laid-Open No. 2006-165529. As a method for adding an impurity, an oxide semiconductor and an impurity element are co-evaporated, an ion of the impurity element is added to the formed oxide semiconductor film by an ion doping method, or the like.
As means for adjusting the carrier concentration, the above methods (1) to (3) may be used alone or in combination.

<Method for forming active layer>
As a method for forming the active layer, a vapor phase film forming method is preferably used. Among vapor deposition methods, sputtering and pulsed laser deposition (PLD) are suitable. Furthermore, the sputtering method is preferable from the viewpoint of mass productivity.

  For example, the film is formed by controlling the degree of vacuum and the oxygen flow rate by RF magnetron sputtering deposition using a polycrystalline sintered body of an oxide semiconductor as a target. The carrier concentration can be reduced as the oxygen flow rate increases.

  The formed film can be confirmed to be an amorphous film by a known X-ray diffraction method. The composition ratio can be determined by an RBS (Rutherford backscattering) analysis method.

<Thickness of active layer>
The thickness of the active layer in the present invention is preferably from 1 nm to 1000 nm, more preferably from 2.5 nm to 500 nm, still more preferably from 5 nm to 100 nm.

By using the active layer having the above-described structure, transistor characteristics with a high mobility of 1 cm 2 / (V · sec) or more and an on / off ratio of 10 4 or more can be realized.

3) Resistive layer A preferred embodiment of the present invention is a structure having a resistive layer between the active layer and at least one of the source electrode and the drain electrode. In the present invention, the electric resistance of the resistance layer is provided to be smaller than the electric conductivity of the active layer. Preferably, the ratio of the electrical conductivity of the active layer to the electrical conductivity of the resistive layer (the electrical conductivity of the active layer / the electrical conductivity of the resistive layer) is preferably 10 1 or more and 10 10 or less, more preferably 10 2 or more. 10 8 or less. A preferable range of the electric conductivity of the active layer is 10 −4 Scm −1 or more and less than 10 2 Scm −2 . More preferably, it is 10 −1 Scm −1 or more and less than 10 2 Scm −2 . A preferable range of the electric conductivity of the resistance layer is 10 −1 Scm −1 or less. More preferably, it is 10 −9 Scm −1 or more and 10 −3 Scm −2 or less.

  Preferably, the resistance layer is thicker than the active layer. More preferably, the thickness of the active layer / the thickness of the resistance layer is more than 1 and 100 or less, more preferably more than 1 and 10 or less. In the case of this embodiment using a resistance layer, the thickness of the active layer is preferably 1 nm to 100 nm, more preferably 2.5 nm to 30 nm. The thickness of the resistance layer is preferably 50 nm or more and 200 nm or less, more preferably 10 nm or more and 100 nm or less.

By using the active layer and the resistance layer, the mobility and the ON / OFF ratio are improved as compared with the configuration of only the active layer, and the fluctuation of the threshold voltage can be suppressed by driving.
The electrical conductivity of the active layer and the resistance layer can be obtained by preparing a physical property measurement sample in which only the active layer is formed on a substrate, and calculating from the measured sheet resistance and film thickness of the sample. Here, when the sheet resistance is ρ (Ω / □) and the film thickness is d (cm), the electrical conductivity σ (Scm −1 ) is calculated as σ = 1 / (ρ * d).

The resistance layer used in the present invention is not particularly defined as satisfying the above electric conductivity, but it is preferable to use an amorphous oxide semiconductor like the active layer. Since an amorphous oxide semiconductor can be formed at a low temperature, it can be formed on a flexible resin substrate such as a plastic. For example, Al 2 O 3 , Ga 2 O 3 , ZrO 2 , Y 2 O 3 , Ta 2 O 3 , MgO, HfO 3 or the like can be used. In particular, like the active layer, an amorphous oxide semiconductor containing at least one selected from the group consisting of In, Ga, Zn, and Sn is preferable. More preferably, it is an amorphous oxide semiconductor containing Ga. More preferably, the amorphous oxide semiconductor further contains In or Zn in addition to Ga. Most preferably, the amorphous oxide semiconductor further contains In and Zn in addition to Ga.

<Adjustment of electric conductivity of resistance layer>
As a method for adjusting the electric conductivity of the resistance layer, it is possible to adjust the carrier concentration of the oxide semiconductor constituting the resistance layer. As the means for adjusting the carrier concentration of the resistance layer, the same method as the means for adjusting the carrier concentration of the active layer described above can be used.

<Method for forming resistance layer>
As a method for forming the resistance layer, a vapor phase film forming method is preferably used. Among vapor deposition methods, sputtering and pulsed laser deposition (PLD) are suitable. Furthermore, the sputtering method is preferable from the viewpoint of mass productivity.
For example, the film is formed by controlling the degree of vacuum and the oxygen flow rate by RF magnetron sputtering deposition using a polycrystalline sintered body of an oxide semiconductor as a target. The greater the oxygen flow rate, the smaller the electrical conductivity.

4) Gate electrode Examples of the gate electrode in the present invention include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al-Nd and APC, tin oxide, zinc oxide, indium oxide, Preferable examples include metal oxide conductive films such as indium tin oxide (ITO) and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof.
The thickness of the gate electrode is preferably 10 nm or more and 1000 nm or less.

  The electrode film formation method is not particularly limited, and may be a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a CVD method, a plasma CVD method, or the like. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from among chemical methods. For example, when ITO is selected, it can be performed according to a direct current or high frequency sputtering method, a vacuum deposition method, an ion plating method, or the like. When an organic conductive compound is selected as the material for the gate electrode, it can be performed according to a wet film forming method.

5) Source electrode and drain electrode Examples of the source electrode and drain electrode material in the present invention include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al-Nd and APC, tin oxide, Preferred examples include metal oxide conductive films such as zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof. It is done.
The thickness of the source electrode and the drain electrode is preferably 10 nm or more and 1000 nm or less.

  The electrode film formation method is not particularly limited, and may be a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a CVD method, a plasma CVD method, or the like. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from among chemical methods. For example, when ITO is selected, it can be performed according to a direct current or high frequency sputtering method, a vacuum deposition method, an ion plating method, or the like. Further, when an organic conductive compound is selected as a material for the source electrode and the drain electrode, it can be performed according to a wet film forming method.

6) Substrate The substrate used in the present invention is not particularly limited. For example, YSZ (zirconia stabilized yttrium), inorganic materials such as glass, polyethylene terephthalate, polybutylene terephthalate, polyethylene naphthalate Synthetic resins such as polyester such as polyester, polystyrene, polycarbonate, polyethersulfone, polyarylate, allyl diglycol carbonate, polyimide, polycycloolefin, norbornene resin, poly (chlorotrifluoroethylene), etc. Organic materials, and the like. In the case of the organic material, it is preferable that the organic material is excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like.

  In the present invention, a flexible substrate is particularly preferably used. The material used for the flexible substrate is preferably an organic plastic film having a high transmittance. For example, polyesters such as polyethylene terephthalate, polybutylene phthalate, and polyethylene naphthalate, polystyrene, polycarbonate, polyethersulfone, polyarylate, polyimide, polycyclo Plastic films such as olefin, norbornene resin, and poly (chlorotrifluoroethylene) can be used. In addition, if the insulating property is insufficient for the film-like plastic substrate, the insulating layer, the gas barrier layer for preventing the transmission of moisture and oxygen, the flatness of the film-like plastic substrate and the adhesion with the electrode and active layer It is also preferable to provide an undercoat layer or the like for improvement.

  Here, the thickness of the flexible substrate is preferably 50 μm or more and 500 μm or less. This is because it is difficult for the substrate itself to maintain sufficient flatness when the thickness of the flexible substrate is less than 50 μm. Further, when the thickness of the flexible substrate is more than 500 μm, it is difficult to bend the substrate itself freely, that is, the flexibility of the substrate itself is poor.

7) Structure Next, the structure of the TFT in the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic diagram illustrating an example of a TFT having an inverted stagger structure. When the substrate 1 is a flexible substrate such as a plastic film, an insulating layer 6 is disposed on at least one surface of the substrate 1, and a gate electrode 2, a gate insulating film 3, and an active layer 4 are laminated thereon. The source electrode 5-1 and the drain electrode 5-2 are provided on the surface.

  FIG. 2 is a schematic view showing an example of a TFT according to another embodiment of the present invention. The active layer 41 and the resistance layer 42 are stacked. It is preferable that the resistance layer 42 has a lower electrical conductivity than the active layer 41 because the mobility of the TFT, the ON / OFF ratio, and the threshold voltage variation due to driving are improved. The electric conductivity of the active layer and the resistance layer can be performed by adjusting the carrier concentration of the active layer. For example, the electrical conductivity can be adjusted by adjusting the oxygen concentration.

8) Protective insulating film If necessary, a protective insulating film may be provided on the TFT. The protective insulating film has a purpose of protecting the semiconductor layer of the active layer or the resistance layer from deterioration due to the atmosphere, and a purpose of insulating an electronic device manufactured over the TFT.

Specific examples thereof include MgO, SiO, SiO 2 , Al 2 O 3 , GeO, NiO, CaO, BaO, Fe 2 O 3 , Y 2 O 3 , or metal oxides such as TiO 2 , SiN x , SiN x. Metal nitride such as O y , metal fluoride such as MgF 2 , LiF, AlF 3 , or CaF 2 , polyethylene, polypropylene, polymethyl methacrylate, polyimide, polyurea, polytetrafluoroethylene, polychlorotrifluoroethylene, polydichloro Difluoroethylene, a copolymer of chlorotrifluoroethylene and dichlorodifluoroethylene, a copolymer obtained by copolymerizing a monomer mixture containing tetrafluoroethylene and at least one comonomer, and a cyclic structure in the copolymer main chain Fluorine-containing copolymer having water absorption of 1% or more And moisture-proof substances having a water absorption rate of 0.1% or less.

  The method for forming the protective insulating film is not particularly limited. For example, a vacuum deposition method, a sputtering method, a reactive sputtering method, an MBE (molecular beam epitaxy) method, a cluster ion beam method, an ion plating method, a plasma polymerization method ( High-frequency excitation ion plating method), plasma CVD method, laser CVD method, thermal CVD method, gas source CVD method, coating method, printing method, or transfer method can be applied.

9) Post-treatment If necessary, heat treatment may be performed as a post-treatment of the TFT. The heat treatment is performed at a temperature of 100 ° C. or higher in the air or in a nitrogen atmosphere. The heat treatment may be performed after the semiconductor layer is formed or at the end of the TFT manufacturing process. By performing the heat treatment, there are effects such as suppression of in-plane variation in TFT characteristics and improvement in driving stability.

2. Display Device The field effect thin film transistor of the present invention is preferably used for an image display device using liquid crystal or an EL element, in particular, a flat panel display (FPD). More preferably, it is used for a flexible display device using a flexible substrate such as an organic plastic film as the substrate. In particular, the field effect thin film transistor of the present invention is most preferably used for a display device using an organic EL element and a flexible organic EL display device because of its high mobility.
FIG. 3 is a schematic diagram of an equivalent circuit of an active matrix driving type organic EL display device using the TFT element of the present invention. The circuit of the organic EL display device in the present invention is not particularly limited to that shown in FIG. 3, and a conventionally known circuit can be applied as it is.

(application)
The field effect thin film transistor of the present invention can be used as an image display device using a liquid crystal or an EL element, particularly as an FPD switching element or driving element. In particular, it is suitable for use as a switching element and a driving element of a flexible FPD device. Further, the display device using the field effect thin film transistor of the present invention is applied in a wide range of fields including a mobile phone display, a personal digital assistant (PDA), a computer display, an automobile information display, a TV monitor, or general lighting. The
In addition to the display device, the field effect thin film transistor of the present invention can be widely applied to IC cards, ID tags, etc. by forming the field effect thin film transistor of the present invention on a flexible substrate such as an organic plastic film. Is possible.

  Hereinafter, the thin film field effect transistor of the present invention will be described with reference to examples, but the present invention is not limited to these examples.

Example 1
1. Fabrication of TFT element An alkali-free glass substrate (Corning, product number Eagle 2000) was used as the substrate.

<Gate electrode>
An Mo thin film (thickness 40 nm) was formed as a gate electrode by RF magnetron sputtering (conditions: film formation temperature 27 ° C., sputtering gas Ar = 12 sccm, RF power 380 W, film formation pressure 0.36 Pa). The gate electrode Mo was patterned by using a shadow mask during sputtering.

<Gate insulation film>
Next, the following gate insulating film was formed on the gate electrode.
Gate insulating film: SiO x by RF magnetron sputtering vacuum deposition method (conditions: target polycrystalline sintered body SiO 2 , film forming temperature 54 ° C., sputtering gas Ar / O 2 (Ar = 12 sccm, O 2 gas flow rate is shown in Table 1) The film was formed to 200 nm with an RF power of 400 W and a film formation pressure of Table 1), and a gate insulating film was provided. The gate insulating film SiO x was patterned by using a shadow mask during sputtering.

<Active layer>
On this, the following active layer A was provided. The active layer was patterned by using a shadow mask during sputtering.
Active layer A: conditions of Ar flow rate 97 sccm, O 2 flow rate 1.7 sccm, RF power 200 W, film forming pressure 0.38 Pa by RF magnetron sputtering vacuum deposition using a polycrystalline sintered body having a composition of InGaZnO 4 as a target. The film was formed to a thickness of 50 nm.

Next, indium tin oxide (ITO) as a source electrode and a drain electrode is formed on the active layer A by RF magnetron sputtering vacuum deposition so as to have a thickness of 40 nm under conditions of an Ar flow rate of 12 sccm, an RF power of 40 W, and a deposition pressure of 0.36 Pa. Film formation was performed. The source electrode and the drain electrode were patterned by using a shadow mask at the time of sputtering.
Thus, TFT elements 1 to 4 of the present invention and comparative TFT elements 1 to 3 were produced. The TFT sizes of the fabricated TFT elements are all channel length (L) = 200 μm and channel width (W) = 1000 μm.

2. Performance Evaluation 1) Measurement of dangling bond density and hydrogen concentration of gate insulating film Si dangling bond density in the gate insulating film SiOx was measured by ESR measurement, and hydrogen concentration in the gate insulating film SiOx was measured by SIMS.

2) Evaluation of TFT performance For each of the obtained TFT elements, TFT transfer characteristics were measured at a saturation region drain voltage (Vd) = 10 V (gate voltage (Vg): −10 V ≦ Vg ≦ 15 V), and the TFT performance was measured. Evaluated. The measurement of TFT transfer characteristics was performed using a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies). Each parameter and its definition in the present invention are as follows.
TFT threshold voltage (Vth): a gate voltage when the drain current value is W / L × 10 nA. Here, since the TFT size is W / L = 1000/200 = 5, the gate voltage when the drain current value is 50 nA was used.
OFF current (Ioff): A drain current value at a gate voltage 5 V lower than the threshold voltage. The unit is [A].
ON current (Ion): drain current at a gate voltage 5 V higher than the threshold voltage.

Threshold voltage shift amount (Vth shift): As an electrical stress on each TFT element, gate voltage Vg = 10 V and drain voltage Vd = 0 V (drain current = 0 A) are applied for 1000 seconds, and the amount of fluctuation in TFT threshold voltage before and after that (Vth shift). The unit is [V].
The Vth shift indicates the degree of characteristic change due to driving, and is preferably smaller.

The TFT characteristics obtained from the above measurement results are shown in Table 1.
From the results shown in Table 1, the TFT of the present invention has an Si dangling bond density of 5 × 10 −16 cm −3 or less, and the threshold shift of the element of the present invention is improved over that of the comparative example, and the threshold shift is less than 10V. I was able to improve.

Example 2
In the TFT element of Example 1, a TFT element was fabricated in the same manner as in Example 1 except that the following active layer B and resistance layer were used instead of the active layer A.
On the gate insulating film, the following active layer B and resistance layer were arranged in order.
Active layer B: conditions of Ar flow rate 97 sccm, O 2 flow rate 0.8 sccm, RF power 200 W, film forming pressure 0.38 Pa by RF magnetron sputtering vacuum deposition using a polycrystalline sintered body having a composition of InGaZnO 4 as a target. The film was formed to a thickness of 10 nm.
Resistance layer: A polycrystalline sintered body having a composition of InGaZnO 4 is used as a target by an RF magnetron sputtering vacuum deposition method under the conditions of an Ar flow rate of 97 sccm, an O 2 flow rate of 2.0 sccm, an RF power of 200 W, and a deposition pressure of 0.38 Pa. Film formation was performed to a thickness of 40 nm.

  In addition, samples for measuring physical properties in which an active layer B and a resistance layer were formed on a glass substrate were prepared, and electric conductivity and carrier concentration were measured by the following methods. The measurement methods of electrical conductivity and carrier concentration were determined by the following methods.

-Measuring method of electrical conductivity-
The electrical conductivity of the sample for measuring physical properties was calculated from the measured sheet resistance and film thickness of the sample. Here, when the sheet resistance is ρ (Ω / □) and the film thickness is d (cm), the electrical conductivity σ (Scm −1 ) is calculated as σ = 1 / (ρ * d).

In this example, (manufactured by Mitsubishi Chemical Corporation) Loresta -GP in sheet resistance 10 7 Ω / □ of less than area of the sample for measuring physical properties, high tester -UP (manufactured by Mitsubishi Chemical Corporation in sheet resistance 10 7 Ω / □ or more regions ) In an environment of 20 ° C. A stylus type surface shape measuring device DekTak-6M (manufactured by ULVAC) was used for measuring the film thickness of the sample for measuring physical properties.

-Carrier concentration measurement by Hall effect measurement method-
The carrier concentration of the sample for measuring physical properties was measured by performing Hall effect measurement using ResiTest 8300 type (manufactured by Toyo Technica Co., Ltd.). Hall effect measurement was performed in an environment of 20 ° C. By measuring the Hall effect, not only the carrier concentration but also the hole mobility of the carrier can be obtained.

As a result, the active layer B had higher electrical conductivity than the resistance layer as described below.
<Active layer B> Electrical conductivity: 2.0 × 10 1 Scm −1 , carrier concentration: 8.9 × 10 18 cm −3 .
<Resistance layer> Electrical conductivity: 2.0 × 10 −6 Scm −1 , carrier concentration: 1.6 × 10 12 cm −3 .

The performance of the obtained device was evaluated in the same manner as in Example 1. The obtained results are shown in Table 2.
From the results shown in Table 2, the threshold shift of the device of the present invention was improved as compared with the device of the comparative example as in Example 1, and the threshold shift was improved to less than 5 V by adopting a configuration in which a resistance layer was inserted. .

Example 3
In the TFT element of Example 1, a film with a barrier having an insulating layer having the following barrier function on both sides of a polyethylene naphthalate film (thickness: 100 μm) was used instead of the alkali-free glass substrate, and the others were the same as in Example 1. Thus, a TFT element was produced.

Insulating layer: SiON was deposited to a thickness of 500 nm. For the deposition of SiON, an RF magnetron sputtering deposition method (sputtering conditions: target Si 3 N 4 , RF power 400 W, gas flow rate Ar / O 2 = 12/3 sccm, film forming pressure 0.45 Pa) was used.

The performance of the obtained device was evaluated in the same manner as in Example 1. The obtained results are shown in Table 3.
As a result, the threshold shift of the device of the present invention was improved as compared with the device of the comparative example as in Example 1.

Example 4
1. Fabrication of TFT Element In the TFT element in Example 1, the gate insulating film SiOx was formed to 200 nm by ICP-CVD using SiH 4 + N 2 O gas instead of sputtering. Other than that, in the same manner as in Example 1, comparative TFT elements 30 were produced.

2. Performance Evaluation The TFT performance of the obtained device was evaluated in the same manner as in Example 1 together with the device 1 of the present invention in Example 1. The results obtained are shown in Table 4.

As a result, the comparative TFT element 30 showed a high value in which the hydrogen concentration exceeded 10 21 cm −3 .
Further, the TFT performance of the comparative TFT element 30 is not preferable because the threshold shift is about the same as that of the element of the present invention, but the threshold voltage becomes negative and a normally-on state is obtained, and the OFF current increases from the element of the present invention. This is due to the high hydrogen concentration. The increase in the hydrogen concentration is an unavoidable phenomenon that occurs with the film formation method of forming the gate insulating film SiOx by ICP-CVD.

Example 5
1. Production of organic EL display device (production of organic EL element part)
1) Formation of lower electrode A film with a barrier having an insulating layer having the following barrier function on both sides of a polyethylene naphthalate film was used for the substrate. Indium tin oxide (hereinafter abbreviated as ITO) was deposited on the substrate to a thickness of 150 nm to form an anode.

2) Formation of organic layer After washing, a hole injection layer, a hole transport layer, a light emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer were sequentially provided.

The configuration of each layer is as follows. Each layer was provided by resistance heating vacuum deposition.
Hole injection layer: 4,4 ′, 4 ″ -tris (2-naphthylphenylamino) triphenylamine (abbreviated as 2-TNATA) and 2,3,5,6-tetrafluoro-7,7,8, A layer containing 1% by mass of 8-tetracyanoquinodimethane (abbreviated as F4-TCNQ) with respect to 2-TNATA, a thickness of 160 nm.
Hole transport layer: N, N′-dinaphthyl-N, N′-diphenyl- [1,1′-biphenyl] -4,4′-diamine (abbreviated as α-NPD), thickness 10 nm.
Light-emitting layer: a layer containing 13% by mass of 1,3-bis (carbazol-9-yl) benzone (abbreviated as mCP) and platinum complex Pt-1 with respect to mCP, thickness 60 nm.
Hole blocking layer: bis- (2-methyl-8-quinonylphenolate) aluminum (abbreviated as BAlq), thickness 40 nm.
Electron transport layer: Tris (8-hydroxyquinoninate) aluminum (abbreviated as Alq3), thickness 10 nm.
Electron injection layer: LiF, thickness 1 nm.

3) Upper electrode It patterned by the shadow mask so that element size might be set to 2 mm x 2 mm, and Al was vapor-deposited in thickness of 100 nm, and it was set as the cathode.

(Protective insulating film)
A 500 nm SiON film was formed on the upper electrode as a protective insulating film by an ion plating method.

  The structures of the compounds used in the examples are shown below.

(Driving test)
An equivalent circuit was configured by combining the obtained organic EL element and the TFTs produced in Examples 1 to 3, and driving tests were performed under various conditions.
As a result, when the TFT of the present invention was used, stable light emission was obtained even when continuously driven for a long time.

It is a schematic diagram which shows the TFT element structure used for this invention. It is a schematic diagram which shows the TFT element structure of another aspect used for this invention. It is a schematic diagram of an equivalent circuit of an active matrix driving type organic EL display device using the TFT element of the present invention.

Explanation of symbols

1: Substrate 2: Gate electrode 3: Gate insulating film 4: Active layer 41: Active layer 42: Resistance layer 5-1: Source electrode 5-2: Drain electrode 6: Insulating layer 200: Switching TFT
300: Organic EL element 400: Signal electrode line 500: Scan electrode line 600: Capacitor 700: Drive TFT
800: Common wire

Claims (11)

  1. A thin film field effect transistor having a gate electrode, a gate insulating film, an active layer made of an amorphous oxide semiconductor, a source electrode, and a drain electrode on a substrate, wherein the dangling bond density of the gate insulating film is 5 × 10 16 cm. −3 or less, and the hydrogen concentration in the gate insulating film is 1 × 10 19 cm −3 or less.
  2.   2. The thin film field effect transistor according to claim 1, wherein the gate insulating film contains a Si compound as an insulating film material.
  3. The thin film field-effect transistor according to claim 2, wherein the Si compound is silicon oxide (SiO x ).
  4. 4. The thin film field effect transistor according to claim 1, wherein a hydrogen concentration in the gate insulating film is less than 1 × 10 18 cm −3 .
  5.   The thin film field effect according to any one of claims 1 to 4, wherein the amorphous oxide semiconductor of the active layer contains at least one selected from the group consisting of In, Ga, Zn, and Sn. Type transistor.
  6.   6. The thin film field effect transistor according to claim 5, wherein the amorphous oxide semiconductor of the active layer contains In.
  7.   The thin film field effect transistor according to claim 6, wherein the amorphous oxide semiconductor further contains Zn or Ga.
  8.   The thin film field effect transistor according to claim 6, wherein the amorphous oxide semiconductor further contains Zn and Ga.
  9.   The thin film field effect transistor according to claim 1, further comprising a resistance layer between the active layer and at least one of the source electrode and the drain electrode.
  10. 10. The method of manufacturing a thin film field effect transistor according to claim 1, wherein a flow rate ratio of oxygen gas to Ar gas (O 2 flow rate / Ar flow rate) is 10 in the gate insulating film. A method for manufacturing a thin film field effect transistor, characterized by being formed by sputtering under an atmosphere of at least%.
  11.   The method of manufacturing a thin film field effect transistor according to claim 10, wherein the gate insulating film is formed at a temperature of 150 ° C. or lower.
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