JP2014513425A - Double active layer for semiconductor device and method of manufacturing the same - Google Patents

Abstract

  Some embodiments include a dual active layer for a semiconductor device. Other embodiments of related devices and methods are also disclosed.

Description

US Federally Assisted Research and Development The US government has a paid-up license in the present invention and is authorized / contract number W911NF-04-2 by the Army Research Lab (ARL). -Have the right to request a license from the patentee to others in a limited situation, based on reasonable conditions provided by the conditions of 0005.

This application claims the benefit of US Provisional Patent Application No. 61 / 472,992, filed Apr. 7, 2011. US Provisional Patent Application No. 61 / 472,992 is hereby incorporated by reference in its entirety.

  This application is a continuation-in-part of the international application PCT / US10 / 36569, filed on May 28, 2010. International application PCT / US10 / 36569 includes US provisional patent application 61 / 182,464 filed May 29, 2009 and US provisional patent filed July 30, 2009. Claim the benefit of application 61 / 230,051. On the other hand, the international application PCT / US10 / 36569 is filed as follows: (a) US Provisional Patent Application No. 61 / 119,303 filed on December 2, 2008, claiming priority International application PCT / US09 / 66114 filed on 30th; (b) 2009 claims US priority 61 / 119,248 filed on 2nd December 2008 International application PCT / US09 / 66111 filed on November 30, 2009; and (c) a partial continuation application of international application PCT / US09 / 66259 filed on December 1, 2009. is there. International application PCT / US09 / 66259 includes: (i) US Provisional Patent Application No. 61 / 119,217, filed December 2, 2008; (ii) US Provisional Patent Application No. 61/182. , 464; and (iii) US Provisional Patent Application 61 / 230,051.

  International application PCT / US10 / 36569, US provisional patent application 61 / 182,464, US provisional patent application 61 / 230,051, international application PCT / US09 / 66114, US provisional patent application 61 / 119,303, international application PCT / US09 / 66111, US provisional patent application 61 / 119,248, international application PCT / US09 / 66259, And US Provisional Patent Application No. 61 / 119,217 are hereby incorporated by reference in their entirety.

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a double active layer and a method for manufacturing the same.

  Thin film transistors are commonly used to power a wide variety of display technologies such as liquid crystal displays, electrophoretic displays, organic light emitting diode displays, and the like. Many thin film transistors use amorphous silicon as the active layer, but the use of amorphous silicon can be inconvenient due to the low mobility and low on / off ratio of amorphous silicon. . Similarly, the high processing temperature of amorphous silicon can be inconvenient when manufacturing flexible displays.

  Therefore, a system and a method for manufacturing the same that can be processed at a low temperature while improving the mobility and on / off ratio of the active layer may be required or beneficial.

  In order to facilitate further description of the embodiments, the following drawings are provided.

2 shows an example of a semiconductor device providing method according to the first embodiment. An example of the provision procedure of the flexible substrate by 1st Embodiment is shown. An example of the manufacturing method of the flexible substrate by 1st Embodiment is shown. The top view of an example of the flexible substrate by a 1st embodiment is shown. FIG. 5 shows a partial cross-sectional view of an example flexible substrate assembly after the flexible substrate of FIG. 4 is attached to a protective template according to the first embodiment. FIG. 6 illustrates a partial cross-sectional view of the example flexible substrate assembly of FIG. 5 after bonding the carrier substrate to the flexible substrate assembly according to the first embodiment. 6 shows an example of a method for processing the flexible substrate assembly of FIG. 5 according to the first embodiment. FIG. 6 shows a cross-sectional view of the example flexible substrate assembly of FIG. 5 after cutting the flexible substrate assembly according to the first embodiment. FIG. 6 shows a cross-sectional view of the example flexible substrate assembly of FIG. 5 after removing the alignment tabs according to the first embodiment. FIG. 6 illustrates a cross-sectional view of the example flexible substrate assembly of FIG. 5 after removing protective material from the flexible substrate assembly according to the first embodiment. An example of the provision procedure of the semiconductor element by 1st Embodiment is shown. 2 shows an example of a method for providing one or more first semiconductor elements according to the first embodiment. FIG. 4 shows a cross-sectional view of an example of a device construction region of a semiconductor device after provision of a gate metal layer according to the first embodiment. 2 shows a cross-sectional view of an example of a gate contact construction region of a semiconductor device after provision of a gate metal layer according to the first embodiment. FIG. FIG. 14 shows a cross-sectional view of an example of a device construction region of the semiconductor device of FIG. 13 after providing an active stack layer according to the first embodiment. FIG. 15 shows a cross-sectional view of an example of a gate contact construction region of the semiconductor device of FIG. 14 after provision of an active stack layer according to the first embodiment. FIG. 14 shows a cross-sectional view of an example of a device construction region of the semiconductor device of FIG. 13 after providing a mesa passivation layer according to the first embodiment. FIG. 15 shows a cross-sectional view of an example of a gate contact construction region of the semiconductor device of FIG. 14 after provision of a mesa passivation layer according to the first embodiment. FIG. 14 shows a cross-sectional view of an example of a device construction region of the semiconductor device of FIG. 13 after post-etching one or more mesa passivation layers according to the first embodiment. FIG. 15 illustrates a cross-sectional view of an example gate contact building region of the semiconductor device of FIG. 14 after post-etching one or more mesa passivation layers according to the first embodiment. FIG. 14 shows a cross-sectional view of an example of a device construction region of the semiconductor device of FIG. 13 after provision of one or more contact elements according to the first embodiment. FIG. 15 shows a cross-sectional view of an example of a gate contact building region of the semiconductor device of FIG. 14 after providing one or more contact elements according to the first embodiment. An example of a method for providing a first dielectric material according to the first embodiment will be described. FIG. 14 illustrates a cross-sectional view of an example of a device build region of the semiconductor device of FIG. 13 after etching the base dielectric material, the first dielectric material, and the second dielectric material, according to the first embodiment. FIG. 14 shows a cross-sectional view of an example of a device construction region of the semiconductor device of FIG. 13 after providing a second metal layer and an ITO layer according to the first embodiment. FIG. 14 shows a cross-sectional view of an example of a device building region of the semiconductor device of FIG. 13 after providing a silicon nitride layer according to the first embodiment. An example of the flattening method of a flexible substrate by a 2nd embodiment is shown. FIG. 28 shows a cross-sectional view of an example of a semiconductor device according to the method of FIG. 27 according to a second embodiment. 1 shows a top view of a portion of a semiconductor device according to a first embodiment. FIG. Figure 5 shows a graph of dielectric material thickness versus substrate spin rate. 2 illustrates an exemplary method of manufacturing a semiconductor device according to one embodiment. FIG. 3 shows a cross-sectional view of a device build region of a typical semiconductor device after providing a gate metal layer over the substrate. FIG. 3 shows a cross-sectional view of a gate contact build region of a representative semiconductor device after providing a gate metal layer over the substrate. FIG. 32 is a flowchart illustrating a procedure for providing a transistor active layer above a gate metal layer according to the embodiment of FIG. FIG. 33 illustrates a cross-sectional view of an example device build region of the semiconductor device of FIG. 32 after providing an etch stop layer above the transistor active layer. FIG. 34 illustrates a cross-sectional view of an example gate contact build region of the semiconductor device of FIG. 33 after providing an etch stop layer above the transistor active layer. FIG. 33 illustrates a cross-sectional view of an example device build region of the semiconductor device of FIG. 32 after providing a mesa passivation layer above and / or above the etch stop layer. FIG. 34 illustrates a cross-sectional view of an example gate contact build region of the semiconductor device of FIG. 33 after providing a mesa passivation layer above and / or above the etch stop layer. FIG. 33 illustrates a cross-sectional view of an example device build region of the semiconductor device of FIG. 32 after post-etching of one or more mesa passivation layers. FIG. 34 illustrates a cross-sectional view of an example of a gate contact construction region of the semiconductor device of FIG. 33 after post-etching one or more mesa passivation layers. FIG. 33 illustrates a cross-sectional view of an example of a device building region of the semiconductor device of FIG. 32 after providing a source / drain contact layer over the transistor active layer, the first active layer, and / or the second active layer. FIG. 34 illustrates a cross-sectional view of an example gate contact build region of the semiconductor device of FIG. 33 after providing source / drain contact layers over the transistor active layer, the first active layer, and / or the second active layer. FIG. 33 illustrates a cross-sectional view of an example device construction region of the semiconductor device of FIG. 32 after performing one or more additional procedures. FIG. 33 illustrates a cross-sectional view of an example device building region of the semiconductor device of FIG. 32 after provision of one or more semiconductor elements, according to one embodiment. FIG. 36 illustrates a cross-sectional view of an example device build region of the semiconductor device of FIG. 32 after provision of one or more semiconductor elements, according to an embodiment different from the embodiment of FIG. FIG. 3 shows a top view of a portion of a representative semiconductor device. The semiconductor of FIG. 32 after providing a first active layer above and / or above the gate metal layer and a second active layer above and / or above the first active layer, according to one embodiment. Sectional drawing of an example of the device construction area | region of a device is shown. 2 is a flowchart illustrating a procedure for providing a source / drain contact layer over a transistor active layer, a first active layer, and / or a second active layer according to the embodiment of FIG. 2 is a flowchart illustrating a procedure for providing a gate metal layer according to the embodiment of FIG. 1 above a substrate;

  For simplicity and clarity of illustration, the drawings illustrate general methods of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessary ambiguity of the present invention. is there. Moreover, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help better understand the embodiments of the present invention. The same reference numbers in different drawings represent the same element.

  Where there are terms "first", "second", "third", "fourth", etc. in the description and claims, they are used to distinguish similar elements and are not necessarily specified It is not used to represent an order or time series. The terms used in this manner are appropriate so that the embodiments described herein can be operated in an order other than that described herein, for example, and those described elsewhere herein. It should be understood that it can be exchanged under circumstances. Furthermore, the terms “comprising” and “having”, and variations thereof, are intended to cover non-exclusive inclusions, and thus a process, method, system, article, device, or apparatus that includes a series of elements. Is not limited to those elements, and includes other elements that are not specifically listed or inherent in such processes, methods, systems, articles, devices, or apparatus. It's okay.

  In the detailed description and claims, the terms “left”, “right”, “front”, “rear”, “top”, “bottom”, “upper”, “lower”, etc. It is used for purposes and does not necessarily represent an invariant relative position. Terms used in this manner allow the embodiments of the invention described herein to operate in other directions than, for example, those shown herein and those described elsewhere herein. As such, it should be understood that it can be exchanged under appropriate circumstances.

  The terms “coupled”, “coupled”, “couples”, “coupled” and the like are to be understood broadly and two or more elements or signals may be electrically connected. Means to be connected by mechanical, mechanical and / or other methods. Two or more electrical elements may be electrically coupled, but not mechanically or otherwise; two or more mechanical elements may be mechanically coupled, but electrical and other The method may not be coupled; two or more electrical elements may be mechanically coupled, but not electrically and otherwise. The bond can exist for any length of time, for example it can be permanent or semi-permanent, or it can be very short.

  “Electrical coupling” and the like is to be understood broadly and includes coupling that includes any signal, whether output signals, digital signals, and / or other types of electrical signals or combinations of electrical signals. . “Mechanical coupling” and the like are to be understood broadly and include all kinds of mechanical coupling.

  The absence of a word such as “removable” or “removable” near a word such as “combined” does not mean that the problematic bond or the like is removable or not possible. .

  Some embodiments include an electronic device. In many embodiments, the electronic device can include a transistor. The transistor can include a gate metal layer, a transistor active layer over the gate metal layer, and a source / drain contact layer over the transistor active layer. The source / drain contact layer can include a first source / drain contact and a second source / drain contact. In the same or different embodiments, the transistor active layer can include a first active layer over the gate metal layer, and the first active layer includes at least one first metal oxide. In the same or different embodiments, the transistor active layer can include a second active layer over the first active layer, and the second active layer includes at least one second metal oxide. In some embodiments, the first active layer has a first conductivity, the second active layer has a second conductivity, and the first conductivity is higher than the second conductivity. .

  Various embodiments include a semiconductor device. In many embodiments, a semiconductor device includes a substrate, a barrier layer on the substrate, a gate metal layer on the barrier layer, a gate barrier layer on the gate metal layer, a transistor active layer on the gate barrier layer, on a transistor active layer. An etch stop layer, a mesa passivation layer on the etch stop layer, and a source / drain contact layer on the mesa passivation layer and the transistor active layer. In the same or different embodiments, the transistor active layer includes a first active layer on the gate metal layer, and the first active layer includes at least one first metal oxide. In the same or different embodiments, the transistor active layer includes a second active layer on the first active layer and between the first active layer and the etch stop layer, the second active layer comprising at least One type of second metal oxide is included. In some embodiments, the first active layer has a first conductivity, the second active layer has a second conductivity, and the first conductivity is higher than the second conductivity. .

  A further embodiment includes a method of manufacturing a semiconductor device. The method includes: providing a substrate; providing a gate metal layer above the substrate; providing a first active layer above the gate metal layer, wherein the first active layer is at least Including a first type of metal oxide and having a first conductivity; providing a second active layer above the first active layer, wherein the second active layer comprises: Providing at least one second metal oxide and having a second conductivity lower than the first conductivity; and providing a source / drain contact layer above the second active layer. Including.

  As used herein, the term “bowing” means the curvature of the substrate relative to the top and bottom surfaces of the substrate, ie, the median plane parallel to both major surfaces. As used herein, the term “warping” means the linear displacement of the substrate surface relative to the z-axis perpendicular to the top and bottom surfaces of the substrate, ie, both major surfaces. As used herein, the term “distortion” refers to the displacement of a substrate in the plane (ie, the top and bottom surfaces of the substrate, ie, the xy plane parallel to both major surfaces). . For example, the strain can include contraction in the xy plane of the substrate and / or expansion in the xy plane of the substrate.

  As used herein, the term “CTE matching material” means a material having a CTE that is less than about 20 percent (%) in difference from the coefficient of thermal expansion (CTE) of the reference material. Preferably, the CTE difference is less than about 10%, less than 5%, less than 3%, or less than 1%. As used herein, “polishing” can mean surface lapping and polishing, or surface lapping only.

  Referring to the drawings, FIG. 1 shows an example of a method 100 for providing a semiconductor device according to a first embodiment. In the same or different embodiments, method 100 can be viewed as a method of providing a thin film transistor on a flexible substrate. The method 100 is merely exemplary and is not limited to the embodiments provided herein. The method 100 can be used in many different embodiments or examples that are not specifically shown or described herein.

  The method 100 includes a procedure 110 for providing a flexible substrate. FIG. 2 is a flowchart illustrating a procedure 110 for providing a flexible substrate according to the first embodiment.

  Procedure 110 includes a process 211 for providing a flexible substrate. As used herein, the term “flexible substrate” means a free-standing substrate that includes a flexible material that easily conforms to its shape. In some embodiments, the process 211 can include providing a flexible substrate. For example, a low modulus can be considered to be a modulus of less than about 5 gigapascals (GPa).

  In many instances, the flexible substrate is a plastic substrate. For example, examples of the flexible substrate include polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyethersulfone (PES), polyimide, polycarbonate, cyclic olefin copolymer, and liquid crystal polymer.

  In many instances, the flexible substrate can include a coating on one or more sides of the flexible substrate. This coating can improve the scratch resistance of the flexible substrate and / or help prevent outgassing or oligomer crystallization on the substrate surface. Furthermore, the coating can planarize the surface of the flexible substrate on which the coating is disposed. The coating can also help reduce distortion. In some examples, the coating is only placed on the surface of the flexible substrate on which the electrical device is manufactured. In another example, the coating is on both sides of the flexible substrate. In various embodiments, the flexible substrate can be provided pre-planarized. For example, the flexible substrate may be a PEN substrate sold under the trade name “planarized Teonex® Q65” by DuPont Teijin Films in Tokyo, Japan. In another embodiment, the flexible substrate can be planarized after provision. For example, method 2700 (FIG. 27) illustrates a method for planarizing a substrate.

  The thickness of the flexible substrate or plastic substrate may be in the range of about 25 micrometers (μm) to about 300 μm. In the same or different embodiments, the thickness of the flexible substrate or plastic substrate may be in the range of about 100 μm to about 200 μm.

  In one example, the flexible substrate can be obtained by cutting a sheet of plastic substrate from a roll of plastic material using a paper cutter or ceramic scissors. In various examples, after cutting the plastic substrate, the cut sheet is blow cleaned with a nitrogen gun. In some embodiments of procedure 110, either or both of the cutting and blowing processes can be part of process 212, described below, instead of being part of process 211.

  The procedure 110 of FIG. 2 continues with a process 212 of preparing a flexible substrate. FIG. 3 is a flowchart illustrating a process 212 for preparing a flexible substrate according to the first embodiment.

  The process 212 of FIG. 2 may include an operation 330 of baking the flexible substrate. Baking the flexible substrate can facilitate the release of oligomers and other chemicals in the flexible substrate that may later leach out during method 100 (FIG. 1).

  In some examples, the flexible substrate can be baked using a vacuum baking process. For example, the temperature in the oven with the flexible substrate can be raised to about 160 ° C. (° C.) to about 200 ° C. over about 2-3 hours. The flexible substrate can be baked at about 160 ° C. to about 200 ° C. and a pressure of about 1 millitorr (mTorr) to about 10 mTorr for 1 hour. The temperature in the oven can then be lowered to between 90 ° C. and about 115 ° C., and the flexible substrate can be baked for an additional about 8 hours. Other baking processes can also be used. After completion of the baking process, any residue or chemicals generated by the baking can be wiped away to clean the flexible substrate.

  Subsequently, the process 212 of FIG. 3 includes an operation 331 of providing a protection template. The protective template can function both as a guide for placement of the flexible substrate, as a protective layer between the flexible substrate and the rollers and / or handling mechanisms of various processing equipment. In one example, the protective template is a mylar or any inexpensive plastic sheet.

  The protective template may be 50 μm to 15 mm thick and can be cut to a length of about 0.5 m (meters) to about 1.5 m. In various embodiments, as part of operation 331, the protective template is folded in half and fold fixing is facilitated by passing through a roller (eg, a hot roll laminator). As part of the operation 331, line tracing of the carrier substrate can be performed on the back side of the protective sheet. In addition, baking the protective template at about 90 ° C. to about 110 ° C. for about 5 minutes to about 10 minutes can facilitate planarization of the protective template.

  Process 212 of FIG. 3 continues with operation 332 of attaching a protective material to at least a portion of the first surface of the flexible substrate. In certain embodiments, the protective material is attached over at least a portion of the planarized surface of the flexible substrate. In some examples, the protective material is not attached to a portion of the flexible substrate.

  The protective material prevents scratching and adhesion of the planarized surface of the flexible substrate, thus reducing defects. In some examples, blue low tack tape (eg, manufactured by Semiconductor Equipment Corporation, part number 18133-7.50) or mylar can be used as a protective material. The protective material may be about 25 μm to about 100 μm thick. For example, the protective material may be about 70 μm thick. In one example, the protective material is rolled by rolling the protective material onto the planarized surface of the flexible substrate using a roller to remove air bubbles between the protective material and the flexible substrate. Is attached.

  Subsequently, the process 212 of FIG. 3 includes an act 333 of cutting the flexible substrate and protective material into the shape of a wafer. A punch template can be used to press the wafer shape onto a flexible substrate (with a planarized surface facing up, if present) and / or a protective material. In one embodiment, a stamped template is used to form a temporary or permanent impression on the protective material and the flexible substrate simultaneously.

  If the stamping template press cuts completely through the flexible substrate, the stamping may cause the coating on the flexible substrate to crack and spread throughout the flexible substrate. The flexible substrate is discarded. After forming a wafer-shaped profile in the flexible substrate and / or protective material using a press, the flexible substrate and protective material are simultaneously cut from one another. In one example, the flexible substrate and protective material are cut with ceramic scissors about 1 millimeter outside the indentation formed by the stamped template.

  In one example, the flexible substrate includes a tab extending from the wafer shape in the flexible substrate and protective material. The tab can be used to help align the flexible substrate with respect to the carrier substrate as it passes through the laminator in process 217 of FIG. FIG. 4 shows a top view of the flexible substrate 450 according to the first embodiment. The flexible substrate 450 can include a body 452 and a tab 451. In many examples, the body 452 can have a circular shape. Although not shown in FIG. 4, a protective material including similarly shaped tabs is placed over the flexible substrate 450. In one embodiment, the tab is not part of the stamping template and is freehanded or freely cut into the flexible substrate and protective material.

  Referring again to FIG. 3, the process 212 of FIG. 3 continues to operation 334 where the flexible substrate is cleaned. In some examples, the second or non-planar surface (ie, the surface without the protective material) of the flexible substrate is wiped away to remove oligomers, other chemicals, or particles. Thereafter, the flattened surface having the protective material of the flexible substrate is blow-cleaned with a nitrogen gun. In another example, double-sided wiping and / or blow cleaning is performed.

  Next, the process 212 of FIG. 3 includes an act 335 of aligning the flexible substrate and the protective template. In one example, a flexible substrate having a tab with a wafer shape is aligned with a line trace drawn on a carrier substrate at operation 331 or formed on a protective template. The line trace of the carrier substrate is usually slightly larger than the wafer shape of the flexible substrate.

  Subsequently, process 212 of FIG. 3 includes an act 336 of bonding the flexible substrate to the protective template. In some embodiments, the flexible substrate is attached to the protective template by attaching a portion of the tab of the flexible substrate to the protective template. For example, a double-sided tape can bond a flexible substrate tab to a protective template. In one example, a portion of the protective material is peeled away and removed from the tab, and a double-sided tape is bonded to the exposed portion of the tab of the flexible substrate. In some examples, a portion of the protective material can be peeled off using tweezers and cut from the protective template using ceramic scissors. In another example, in operation 332 of FIG. 3, the protective material is attached to a portion of the tab, and a double-sided tape is attached to that portion, eliminating the need to peel and remove a portion of the protective material.

  After bonding the flexible substrate to the protective coating, the protective template is then covered over the flexible substrate. FIG. 5 shows a partial cross-sectional view of the flexible substrate assembly 540 after the flexible substrate 450 is attached to the protective template 555 according to the first embodiment. In this example, tape 556 is bonded to flexible substrate 450 and protective template 555. As described above, the protective material 553 is bonded to the flexible substrate 450.

  In some examples, only one side of the flexible substrate is attached to the protective template. In another example, both sides of the flexible substrate are attached to a protective template.

  Next, the process 212 of FIG. 3 includes an act 337 of laminating a flexible substrate, a protective material, and a protective template. The flexible substrate and the protective material are placed between each half of the folded protective template. The flexible substrate, the protective material, and the protective template may be stacked using a hot roll laminator to remove bubbles between the protective material and the protective template and between the protective material and the flexible substrate. it can. In one example, the flexible substrate and protective template are placed over a guide sheet (eg, Lexan® guide sheet) and fed into a hot roll laminator. As an example, a flexible substrate and a tab of protective material can be initially fed into the laminator. The flexible substrate and the protective template are laminated at a pressure of about 120 kPa (kilopascal) to about 160 kPa and a temperature of about 90 ° C. to about 110 ° C. The lamination speed can be from about 1 meter / minute to about 2 meters / minute.

  After lamination of the flexible substrate and the protective template, process 212 is complete. Referring again to FIG. 2, the procedure 110 of FIG. 2 includes a process 213 for applying a carrier substrate. In many embodiments, the carrier substrate may be a 6, 8, 12, or 18 inch wafer or panel. In some embodiments, the carrier substrate may be a panel of about 370 mm × 470 mm.

  The carrier substrate can include a first surface and a second surface opposite the first surface. In some examples, at least one of the first surface and the second surface is polished. Polishing the surface that is not subsequently bonded to the flexible substrate improves the function of the vacuum chuck or air chuck for handling the carrier substrate. Also, the topological features of the carrier substrate surface that can cause roughness of the flexible substrate assembly in the z-axis after being bonded to the flexible substrate by polishing the surface that will later be bonded to the flexible substrate. Removed.

In various embodiments, the carrier substrate is alumina (Al ₂ O ₃ ), silicon, low CTE glass, steel, sapphire, barium borosilicate, soda lime silicate, alkali silicate, or flexible substrate and CTE. Including at least one of the other materials in alignment. The CTE of the carrier substrate should be aligned with the CTE of the flexible substrate. If the CTEs are not aligned, stress may occur between the carrier substrate and the flexible substrate.

  For example, the carrier substrate can include sapphire having a thickness between about 0.7 mm and about 1.1 mm. The carrier substrate can also include 96% alumina having a thickness between about 0.7 mm and about 1.1 mm. In a different embodiment, the 96% alumina thickness is about 2.0 mm. In another example, the carrier substrate may be a single crystal silicon wafer having a thickness of at least about 0.65 mm. In yet another embodiment, the carrier substrate can comprise stainless steel having a thickness of at least about 0.5 mm. In some examples, the carrier substrate is slightly larger than the flexible substrate.

  Next, the procedure 110 of FIG. 2 includes a process 214 of providing a crosslinkable adhesive. In one example, the crosslinkable adhesive releases gas at a rate of less than about 2 × 10 −4 Torr · liter / second. In some examples, the crosslinkable adhesive is thermosetting and / or UV (ultraviolet) light curable.

  In various embodiments, the crosslinkable adhesive is a crosslinkable acrylic adhesive. In the same or different embodiments, the crosslinkable adhesive is a crosslinkable pressure sensitive acrylic adhesive or a crosslinkable viscoelastic polymer. In one example, the CTE of the adhesive is very large compared to the CTE of the flexible substrate and the carrier substrate. However, since the adhesive layer is thin compared to the thickness of the flexible substrate and the carrier substrate, the adhesive does not cause stress (that is, viscoelasticity) between the flexible substrate and the carrier substrate. The CTE of the adhesive is not important.

  Subsequently, the procedure 110 of FIG. 2 includes a process 215 of depositing a crosslinkable adhesive over the first surface of the carrier substrate. In many embodiments, the deposition of the crosslinkable adhesive on the first surface of the carrier substrate includes spin coating, spray coating, extrusion coating, preform lamination, slot die coating, screen lamination, and screen printing. This can be done using at least one method.

  For example, the carrier substrate can be coated with a crosslinkable adhesive. The carrier substrate and the crosslinkable adhesive can be rotated to disperse the crosslinkable adhesive above the first surface of the carrier substrate. In some embodiments, the carrier substrate having a crosslinkable adhesive is rotated from about 900 rpm (rev / min) to 1100 rpm for about 20 seconds to about 30 seconds, and then the carrier substrate having a crosslinkable adhesive is about 3400 rpm to about The crosslinkable adhesive is spin-coated on the carrier substrate by rotating at 3600 rpm for about 10 seconds to 30 seconds. In a different embodiment, a carrier substrate having a crosslinkable adhesive is coated at the surface of the carrier substrate by rotating at about 600 rpm to about 700 rpm, and then rotated at about 3400 rpm to about 3600 rpm to form a crosslinkable adhesive. The thickness of the agent is adjusted.

  Prior to spin coating, the crosslinkable adhesive can be delivered over or above the geometric center of the carrier substrate. In a different embodiment, the crosslinkable adhesive can be supplied on or above the carrier substrate while the carrier substrate is rotating.

  The thickness of the crosslinkable adhesive on the carrier substrate after the deposition procedure may be between about 3 μm and about 15 μm. In the same or different embodiments, the thickness of the crosslinkable adhesive on the carrier substrate after the deposition procedure may be between about 10 μm and about 12 μm.

  The procedure 110 of FIG. 2 continues with the process 216 of baking the crosslinkable adhesive. In certain embodiments, the crosslinkable adhesive can be baked to remove the solvent. For example, the crosslinkable adhesive can be baked at 80 ° C. for 30 minutes and then at 130 ° C. for 15 minutes.

  In another example, the crosslinkable adhesive is not baked. For example, if the crosslinkable adhesive does not contain any solvent, baking is not necessary. Further, if the crosslinkable adhesive is very viscous, additional solvent can be added to the crosslinkable adhesive to reduce the viscosity before depositing the adhesive in process 215.

  The carrier substrate can then be placed on the protective template. As shown in FIG. 6, the flexible substrate is already bonded to a part (or half) of the protective template, and the carrier substrate with the crosslinkable adhesive is placed over another part (or half) of the protective template. Can be arranged. In some instances, at this point, the crosslinkable adhesive is still in a liquid state. Thus, the carrier substrate coated with the crosslinkable adhesive can be stored horizontally for about 8 to about 12 hours before bonding to the flexible substrate.

  Next, the procedure 110 of FIG. 2 includes a process 217 of placing both substrates between half of the protective template while using a crosslinkable adhesive to bond the carrier substrate to the flexible substrate. The second surface of the flexible substrate can be disposed above the first surface of the carrier substrate, and the adhesive is between the second surface of the flexible substrate and the first surface of the carrier substrate. Arranged between.

  In one example, a crosslinkable adhesive is used by laminating the flexible substrate assembly between half of the protective template to remove air bubbles between the carrier substrate and the flexible substrate. A carrier substrate is bonded to the flexible substrate. In the stacking of the flexible substrate, the carrier substrate and the flexible substrate are first aligned, and when stacked, the carrier substrate and the flexible substrate are aligned. The aligned structure can then be passed through a hot roll laminator, which may be the same as the laminator in operation 337 of FIG. The flexible substrate assembly can be laminated at a speed of about 0.4 to 0.6 meters / minute.

  In various embodiments, the protective material may stick to the protective template during lamination. To avoid this problem, a shielding material can be placed between the protective template and the protective material prior to the lamination of operation 337 and / or operation 332. The shielding material may be wax paper, for example. In one embodiment, the shielding material is attached to the protective material from the beginning when obtained from the manufacturer.

  In the same or different embodiments, during lamination, some crosslinkable adhesive is extruded from between the carrier substrate and the flexible substrate, in particular the carrier substrate and the overlying crosslinkable adhesive layer are flexible. Some crosslinkable adhesives may adhere to the first or top surface of the flexible substrate because it is slightly larger than the flexible substrate. However, the presence of the protective material prevents this problem from occurring. Since the protective material is eventually removed and discarded, the crosslinkable adhesive that is extruded (instead of the flexible substrate) and adheres to the top surface of the protective material is not critical.

  FIG. 6 shows a partial cross-sectional view of the flexible substrate assembly 540 after the carrier substrate 651 according to the first embodiment is bonded to the flexible substrate assembly 540. In this embodiment, the crosslinkable adhesive 652 bonds the surface 661 of the carrier substrate 651 to the surface 662 of the flexible substrate 450. A protective material 553 is disposed above the surface of the flexible substrate 450 surface 656. A shielding material 654 is disposed between the protective material 553 and the protective template 555. The protective template 555 is folded so that the protective template 555 is also placed under the surface 663 of the carrier substrate 651. Tape 556 bonds protective template 555 to tab 451 of flexible substrate 450.

  Referring again to FIG. 2, the procedure 110 continues with a process 218 for processing the flexible substrate assembly. FIG. 7 is a flowchart illustrating a process 218 for processing a flexible substrate assembly according to the first embodiment.

  Process 218 of FIG. 7 includes an operation 730 of cutting the flexible substrate assembly. In one example, ceramic scissors are used to cut the protective template and cut to the alignment tabs of the flexible substrate positioned between the protective templates, but do not remove the entire alignment tab. After cutting the flexible substrate assembly, the protective template can be peeled off or otherwise removed from the shielding material and the carrier substrate by hand. FIG. 8 shows a cross-sectional view of the flexible substrate assembly 540 after cutting the flexible substrate assembly and removing the protective template, according to the first embodiment. In particular, in FIG. 8, the protective template 555 (FIGS. 5 and 6) and the tape 556 (FIGS. 5 and 6) of the flexible substrate 450 are removed.

  Referring again to FIG. 7, the next operation in process 218 is operation 731 to remove the shielding material by hand. In one example, the flexible substrate assembly is placed on the table so that the shielding material faces the table. The shielding layer is removed (eg, peeled) from the flexible substrate assembly while slowly pulling the flexible substrate assembly away from the table. That is, the shielding layer can be removed by pulling downward from the end of the table while moving the flexible substrate assembly from the table in the horizontal direction. In some examples, after removing the shielding layer, if the flexible substrate is not on the proper center of the carrier substrate, or if no other alignment has been performed, the plastic substrate can be slid to align with the carrier substrate. Can be aligned.

  Subsequently, the process 218 of FIG. 7 includes an operation 732 of removing the alignment tab from the flexible assembly. In one example, the alignment tab can be cut from the flexible substrate using ceramic scissors. As the flexible substrate moves in the z-axis direction (relative to the carrier substrate), this cutting should be done slowly as the flexible substrate can delaminate from the carrier substrate. If delamination occurs, the flexible substrate assembly can be re-laminated. FIG. 9 shows a cross-sectional view of the flexible substrate assembly 540 after the alignment tab has been removed, according to the first embodiment.

  Next, the process 218 of FIG. 7 includes an operation 733 of cleaning the flexible substrate assembly. In some examples, the flexible substrate assembly is cleaned with hexane. Hexane can be applied by rotating the flexible substrate assembly and spraying hexane onto the protective material. After the protective material is cleaned, the exposed surface and / or edges of the carrier substrate are wiped clean using hexane.

Procedure 218 of FIG. 7 continues to operation 734 where the crosslinkable adhesive is cured. In the same or different embodiments, the crosslinkable adhesive is UV cured. For example, the flexible substrate assembly can be exposed to UV light for about 15-25 seconds at room temperature to cure the crosslinkable adhesive. In some embodiments, the crosslinkable adhesive can be cured with UV light having an intensity of about 75 mW / cm ² (milliwatts per square centimeter) in the UV light range of about 320 nm (nanometers) to about 390 nm. . Dymax 2000-EC UV Curing Flood Lamp manufactured by Dymax Corporation of Torrington, Connecticut can be used to cure the crosslinkable adhesive.

  In various examples, the crosslinkable adhesive is thermally cured during baking at operation 736. In one example, the end of the crosslinkable adhesive is UV cured and the remaining portion of the crosslinkable adhesive is heat cured during the bake of operation 736.

  Subsequently, the process 218 of FIG. 7 includes an act 735 of removing protective material from the flexible substrate assembly. In certain instances, the protective material can be slowly removed using tweezers. During the removal process, the protective material is kept as flat as possible to prevent delamination of the flexible substrate from the carrier substrate. In another example, the protective material can be removable by UV light. In these examples, the tackiness of the protective material is lost during UV light. FIG. 10 shows a cross-sectional view of the flexible substrate assembly 540 after the protective material has been removed from the flexible substrate assembly according to the first embodiment.

  Next, the process 218 of FIG. 7 includes an operation 736 of baking the flexible substrate assembly. Baking the flexible substrate assembly can be useful in reducing distortion, warpage, and deflection of the flexible substrate. In some embodiments, the adhesive can be cured by baking.

  In some examples, the flexible substrate assembly can be baked using a vacuum baking process. For example, the temperature in the oven containing the flexible substrate assembly can be raised to about 160 ° C. to about 190 ° C. in a few hours. The flexible substrate assembly may be baked at 180 ° C. and a pressure of about 1 mTorr to about 10 mTorr for about 50 to 70 minutes. The temperature in the oven can then be lowered to between about 90 ° C. and 115 ° C., and the flexible substrate assembly can be baked for an additional about 7 hours to about 9 hours. Another baking process can be used. After completion of the bake process, the flexible substrate assembly is cleaned and placed in an oven at about 90 ° C. to 110 ° C. for a minimum of about 2 hours.

  After baking the flexible substrate assembly, process 218 is complete, and thus procedure 110 is also complete. A flexible substrate having no distortion or at least minimal distortion (eg, approximately the detection limit of the Azores 5200 manufactured by Azores Corporation of Wilmington, Massachusetts) by procedures 110 as described herein, and similar procedures. One or more electrical components can be manufactured on top. Prior art methods of manufacturing electrical components on a flexible substrate create significant distortion problems that can result in handling errors, photolithography alignment errors, and line / layer defects.

  Referring again to FIG. 1, the method 100 includes a procedure 120 for providing a semiconductor device. FIG. 11 is a flowchart showing a procedure 120 for providing the semiconductor device according to the first embodiment.

  The procedure 120 of FIG. 11 includes a process 1112 that provides one or more first semiconductor devices. FIG. 12 is a flowchart illustrating a process 1112 for providing one or more first semiconductor devices according to the first embodiment.

  Process 1112 of FIG. 12 includes an operation 1211 that provides a gate metal layer. FIG. 13 shows a cross-sectional view of an example device building region of a semiconductor device 1350 after providing a gate metal layer according to the first embodiment. As can be seen in FIG. 29, the cross-sectional view of the device construction region is a cross-sectional view of a portion of the semiconductor device 1350 at line “a”. The device construction cross-sectional view includes cross-sectional views of the a-Si contact region 2980 and the via region 2982. Further, FIG. 14 shows a cross-sectional view of an example gate contact construction region of a semiconductor device 1350 after provision of a gate metal layer according to the first embodiment. As can be seen in FIG. 29, a cross-sectional view of the gate contact build region is a cross-sectional view of a portion of the semiconductor device 1350 at line “b”. The gate contact construction sectional view includes a sectional view of the gate contact region 2981. FIG. 29 is merely an example and is not limited to the embodiments provided herein.

  Referring to FIGS. 13 and 14, for example, a silicon nitride passivation layer 1352 having a thickness of about 0.30 μm is provided over the flexible substrate assembly 540. A silicon nitride passivation layer 1352 can be provided over the flexible substrate 450 (FIG. 10) of the flexible substrate assembly 540. In some embodiments, the flexible substrate 450 can be baked prior to depositing the silicon nitride passivation layer 1352.

  Further, a patterned metal gate 1353 can be provided above the silicon nitride passivation layer 1352. The patterned metal gate 1353 can include molybdenum. In one example, an approximately 0.15 μm layer of molybdenum can be deposited over the silicon nitride passivation layer 1352 and then a pattern etch can be performed to form a patterned metal gate 1353. For example, molybdenum can be deposited over the silicon nitride passivation layer 1352 by sputtering. In one example, molybdenum can be obtained from Rockefright, New Jersey, KDF Electronic, Inc. It can be deposited using manufactured KDF 744. In the same or different examples, a patterned metal gate 1353 is available from Applied Materials, Inc. of Santa Clara, California. Etching can be performed using manufactured AMAT 8330.

  Subsequently, the process 1112 of FIG. 12 includes an operation 1212 that provides an active stack. 15 and 16 show an example of a semiconductor device 1350 after provision of an active stack according to the first embodiment.

  With reference to FIGS. 15 and 16, a silicon nitride gate dielectric 1554 can be formed, for example, over the patterned metal gate layer 1353 and the silicon nitride passivation layer 1352. Referring to FIG. 15, a patterned amorphous silicon (a-Si) layer 1555 can be provided over a silicon nitride gate dielectric 1554, for example, in a device building region of a semiconductor device 1350, and patterned. A silicon nitride intermetal dielectric (IMD) layer 1556 may be provided over the a-Si layer 1555.

  In one example, as shown in FIGS. 15 and 16, silicon nitride gate dielectric 1554 is deposited over metal gate layer 1353 and silicon nitride passivation layer 1352 of semiconductor device 1350 by plasma enhanced chemical vapor deposition (PECVD). Can be deposited on. In the same or different examples, the silicon nitride gate dielectric 1554 may be about 0.30 μm thick.

  Referring to FIG. 15, by way of example, an a-Si layer 1555 can be deposited over silicon nitride gate dielectric 1554 by PECVD. In the same or different examples, the a-Si layer 1555 may be about 0.08 μm thick.

  As an example, a silicon nitride IMD layer 1556 can be deposited over the a-Si layer 1555 by PECVD. In the same or different examples, the silicon nitride IMD layer 1556 may be about 0.10 μm thick.

  In one example, silicon nitride gate dielectric 1554, a-Si layer 1555, and silicon nitride IMD layer 1556 are all from Applied Materials, Inc. of Santa Clara, California. It can be deposited by PECVD using manufactured AMAT P5000. In the same or different examples, the temperature at which the silicon nitride gate dielectric 1554, a-Si layer 1555, and silicon nitride IMD layer 1556 are deposited on the semiconductor device 1350 is greater than about 180 degrees Celsius. For example, the temperature at which the silicon nitride gate dielectric 1554, a-Si layer 1555, and silicon nitride IMD layer 1556 are deposited on the semiconductor device 1350 is between about 180 degrees Celsius and about 250 degrees Celsius. As an example, the temperature at which the silicon nitride gate dielectric 1554, a-Si layer 1555, and silicon nitride IMD layer 1556 are deposited on the semiconductor device 1350 is between about 188 ° C. and about 193 ° C. Further, the deposition of the silicon nitride gate dielectric 1554, the a-Si layer 1555, and the silicon nitride IMD layer 1556 on the semiconductor device 1350 can be performed in a substantially vacuum.

  After the silicon nitride gate dielectric 1554, a-Si layer 1555, and silicon nitride IMD layer 1556 are deposited over the semiconductor device 1350, the resulting layer can be etched. For example, silicon nitride can be etched using a 10: 1 buffered oxide etch (BOE). Further, the a-Si layer 1555 can be etched using AMAT 8330. In one example, the silicon nitride IMD layer 1556 and the a-Si layer 1555 are etched to expose the a-Si layer 1555, ie, the a-Si layer 1555 is completely covered by the silicon nitride IMD layer 1556. I will not be broken.

  Next, the process 1112 of FIG. 12 includes an operation 1213 of providing a mesa passivation layer. 17 and 18 show an example of a semiconductor device 1350 after providing a mesa passivation layer according to the first embodiment.

  Referring to FIG. 17, as an example, in the device construction region of semiconductor device 1350, mesa passivation layer 1757 is located above silicon nitride gate dielectric 1554, a-Si layer 1555, and silicon nitride IMD layer 1556 of semiconductor device 1350. It is deposited on. Mesa passivation layer 1757 can include silicon nitride. The mesa passivation layer 1757 is deposited over the a-Si layer 1555 to deactivate and / or encapsulate the surface of the a-Si layer 1555, thereby preventing contamination of the surface of the a-Si layer 1555, Leakage current along the surface of the a-Si layer 1555 can be reduced. Referring to FIG. 18, by way of example, a mesa passivation layer 1757 can be deposited over a silicon nitride gate dielectric 1554 in the gate contact build region of the semiconductor device 1350.

  A mesa passivation layer 1757 can be deposited over the semiconductor device 1350 by PECVD. As an example, the mesa passivation layer 1757 may be about 0.10 μm thick. In the same or different examples, the mesa passivation layer 1757 can be deposited by PECVD using AMAT P5000.

  Subsequently, the process 1112 of FIG. 12 includes an operation 1214 for post-etching one or more mesa passivation layers. 19 and 20 illustrate a cross-sectional view of the semiconductor device 1350 after post-etching one or more mesa passivation layers. For example, FIG. 20 shows the semiconductor device 1350 after contact gate etching has been performed in the gate contact build area of the semiconductor device 1350. In the same or different examples, FIG. 19 shows the semiconductor device 1350 after performing contact a-Si etching in the device construction area of the semiconductor device 1350.

  Silicon nitride can be etched away by contact gate etching of the gate contact build area of the semiconductor device 1350. For example, the mesa passivation layer 1757 and the silicon nitride gate dielectric 1554 can be etched away by contact gate etching. In many instances, the metal gate layer 1353 underlying the silicon nitride gate dielectric 1554 functions as an etch stop layer for the etching process. Contact gate etching in the contact gate build area can be performed in Tegal 903 manufactured by Tegal Corporation of Petaluma, California. After contact gate etching, a gate contact 2091 is formed on the semiconductor device 1350. Gate contact 2091 corresponds to gate contact region 2981 in FIG.

  Silicon nitride can be etched away by contact a-Si etching in the device construction area of the semiconductor device 1350. For example, the mesa passivation layer 1757 and the silicon nitride IMD layer 1556 can be etched away by contact a-Si etching. The silicon nitride layer can be etched using 10: 1 BOE. The a-Si layer 1555 under the silicon nitride layer 1556 can function as an etch stop layer for the etching process. After contact a-Si etching, an a-Si contact 1990 is formed on the semiconductor device 1350. The a-Si contact 1990 corresponds to the a-Si contact region 2980 in FIG. In this embodiment, the contact a-Si etch and the contact gate etch can be etched separately using separate etch masks.

  After operation 1214, process 1112 of FIG. 12 is complete. Referring to FIG. 11, the procedure 120 continues with a process 1113 that provides one or more contact elements. FIG. 21 shows a cross-sectional view of an example device construction area of semiconductor device 1350 after process 1113 is completed. Further, FIG. 22 shows a cross-sectional view of an example gate contact building area of a semiconductor device 1350 after process 1113 is completed.

  In the example shown in FIG. 21, an N + a-Si layer 2159 is provided over a portion of the mesa passivation layer 1757, the a-Si layer 1555, and the silicon nitride IMD layer 1556. A diffusion barrier 2158 is provided above the N + a-Si layer 2159 and a metal layer 2160 is provided above the diffusion barrier 2158, as shown in FIG. Similarly, in the example of FIG. 22, an N + a-Si layer 2159 is provided over a portion of the mesa passivation layer 1757, the silicon nitride gate dielectric 1554, and the gate metal layer 1353. Also, as shown in FIG. 22, a diffusion barrier 2158 is provided above the N + a−Si layer 2159 and a metal layer 2160 is provided above the diffusion barrier 2158.

  The N + a-Si layer 2159 can be provided by PECVD. As an example, the N + a-Si layer 2159 may be about 0.05 μm thick. In the same or different examples, the N + a-Si layer 2159 can be deposited by PECVD using AMAT P5000.

  As an example, the diffusion barrier 2158 can include tantalum (Ta). In the same or different examples, the metal layer 2160 can include aluminum (Al). The diffusion barrier 2158 can be useful for preventing migration of atoms from the metal layer 2160, for example, preventing diffusion of Al atoms into the N + a-Si layer 2159, and subsequently the a-Si layer 1555. Diffusion barrier 2158 and metal layer 2160 can be deposited over N + a-Si layer 2159 by sputtering. In one example, diffusion barrier 2158 and metal layer 2160 can be deposited using KDF 744.

After the N + a-Si layer 2159, the diffusion barrier 2158, and the metal layer 2160 are deposited on the semiconductor device 1350, these three layers are etched. As an example, the three layers can be etched using AMAT 8330. In one example, N + a-Si layer 2159, diffusion barrier 2158, and metal layer 2160 are etched using one recipe for all three layers. As an example, the N + a-Si layer 2159, the diffusion barrier 2158, and the metal layer 2160 include boron trichloride (BCl ₃ ) with a flow rate of about 140 sccm (standard cubic centimeters / minute) and chlorine gas (Cl ₂ ) with a flow rate of about 10 sccm. Is etched at a pressure of about 20 mTorr for 1 minute 45 seconds. The pressure is then reduced to 10 mTorr for 15 minutes while increasing Cl ₂ to 30 sccm. Next, the flow rate of BCl ₃ is increased to 30 sccm and the pressure is increased to 15 mTorr. Finally, the flow rate of BCl ₃ and Cl ₂ is set to 0, and oxygen (O ₂ ) is supplied for 60 minutes at 50 sccm and 50 mTorr pressure.

  In various embodiments, the procedure 120 can include a process 1198 that provides a base dielectric material. The base dielectric material can provide a uniform surface (eg, a wetting layer) in the case of a spin-on dielectric material (eg, dielectric layer 2461 (FIG. 24)). In some examples, the base dielectric material can include silicon oxide or silicon nitride. In many instances, the base dielectric material can be obtained using a process similar or identical to the process used to obtain the second dielectric material as described below (ie, process 1117). In another embodiment, procedure 120 does not include providing a base dielectric material.

  Subsequently, the procedure 120 includes a process 1114 for providing a first dielectric material. The first dielectric material can be provided over one or more contact elements of process 1113. In certain examples, the first dielectric material may be an organosiloxane-based dielectric material, an organosiloxane dielectric material, and / or a siloxane-based dielectric material. In various embodiments, the first dielectric material can be an organic material. By using the organosiloxane dielectric material, it is possible to obtain a thicker film and a more flexible film than the non-organosiloxane dielectric material. In some examples, the first dielectric material can be used as an interlayer dielectric. In another example, the first dielectric material can be used as an in-layer dielectric.

  Table 1 illustrates exemplary properties of a dielectric material that can be used as the first dielectric material in process 1114 according to one embodiment.

  When used in Table 1, film thickness means the desired thickness of the dielectric material exhibiting other properties in the table. Transmittance means the percentage of light that passes through the dielectric material. Planarization means the degree of planarization (DOP) of the dielectric material. Resistance to plasma-induced damage indicates a plasma that does not damage this film. Adhesive means that the dielectric material can be bonded to at least these other materials. Outgassing can mean the outgassing pressure of the dielectric material, or the rate at which the dielectric material releases gas. Moisture absorption can mean the rate at which the dielectric material absorbs moisture. A supply device refers to a device that can be used to apply a dielectric material.

  Table 2 illustrates properties of a second example of a dielectric material that can be used as the first dielectric material in process 1114 according to one embodiment.

  As used in Table 2, etch chemistry refers to etch chemistry that can be used to etch dielectric materials. The etch rate is the minimum etch rate of the dielectric material using that etch chemistry. Feature size refers to the minimum size of an element or feature formed using a dielectric material. The breakdown voltage is a voltage per unit length at which the dielectric material starts to function as a conductor. Heat resistance is the lowest temperature that a material can withstand before becoming unstable.

  FIG. 23 illustrates an example of a process 1114 for providing a first dielectric material. In various embodiments, the first dielectric material may be a spin-on dielectric. Thus, in these examples, the dielectric can be applied to the semiconductor device by spin coating a first dielectric material over the first metal layer and the various silicon nitride layers. In various embodiments, the application of the first dielectric material is performed by Rite Track, Inc. of West Chester, Ohio. It can be done in the more available Rite Track 8600.

  Referring to FIG. 23, process 1114 can include an operation 2330 of rotating a semiconductor device at a first predetermined speed. In some examples, the first predetermined spin speed is between about 500 rpm and about 2000 rpm. In the same or different embodiments, the first predetermined speed is about 1000 rpm.

  Subsequently, the process 1114 can include an act 2331 of supplying a first dielectric material. In one example, the first dielectric material is supplied above the substrate while rotating the substrate at a first predetermined speed. In some examples, the first dielectric material can be supplied using a syringe. If the substrate is a 6 inch diameter wafer, about 4 mL (milliliter) can be supplied above the semiconductor device. In one example, the pressure at the syringe tip during delivery may be about 15 kPa. In the same or different embodiments, after supplying the first dielectric material by syringe, the syringe has a suction back pressure of about 1 kPa. The suction back pressure of the syringe prevents a further amount of the first dielectric material from dripping out of the syringe after the delivery process is complete. For 6 inch wafers, the supply process takes about 3 seconds. The semiconductor device is rotated at a first predetermined speed until operation 2331 is completed.

In various embodiments, a dynamic delivery method is used. That is, the first dielectric material is supplied while rotating the substrate. In some examples, the first dielectric material is provided in the center of the substrate. In another example, at the beginning of the dispensing process, the syringe is placed above the center of the substrate and rotated while moving from the center of the substrate to the edge of the substrate at a constant speed of about 30 to about 60 millimeters / second. Let In another embodiment, a static delivery method is used. That is, the substrate is not rotated during the supply process.

  Next, the process 1114 includes an operation 2332 that increases the speed of the semiconductor device from a first predetermined speed to a second predetermined speed. In some examples, the second predetermined spin speed is between about 2000 rpm and about 4000 rpm. In the same or different embodiments, the second predetermined speed is about 2600 rpm. By rotating the semiconductor device at a second predetermined speed of about 2600 rpm for about 30 seconds, the first dielectric material can be dispersed to a thickness of about 2 μm on the surface of the semiconductor device. Different thicknesses of the first dielectric material can be realized by using different second predetermined speeds.

  FIG. 30 shows the thickness of the first dielectric material versus the semiconductor material spin speed (ie, speed).

  Process 1114 may further include an operation 2333 that performs edge bead removal. In one example, during operations 2331 and 2332, the first dielectric material flows outward due to centrifugal forces toward the edge of the substrate, forming a ridge (ie, an edge bead) at the edge of the top surface of the semiconductor device. Is done. As the edge beads dry, they can flake off, increasing semiconductor device defects and / or damaging the manufacturing location. Accordingly, the edge bead is removed at operation 2333. In one example, the apparatus used for operations 2331 and 2332 can include an edge bead removal device. In one example, the edge bead is sprayed with a solvent to remove the first dielectric material around the edge of the substrate. In one example, the solvent is sprayed about 5 to about 6 millimeters inside the substrate edge while rotating the semiconductor device at a third predetermined speed. In some examples, removing the first dielectric material from the edge of the substrate is provided when providing the second dielectric material above the first dielectric material (process 1117 of FIG. 11). The second dielectric material also serves to cover the end of the first dielectric material.

  In some examples, cyclohexanone, propylene glycol monomethyl ether acetate (PGMEA), or other edge bead removal solvent can be used. In one example, the semiconductor device is rotated at a third predetermined speed of about 1000 rpm during the edge bead removal process. In one example, the semiconductor device is rotated at a third predetermined speed for about 30 seconds, at which time the bead edge is sprayed with solvent.

  Subsequently, process 1114 continues to operation 2334 where the rotation of the semiconductor device is stopped. After stopping the rotation of the semiconductor device, the process 1114 is complete.

  Referring again to FIG. 11, the procedure 120 includes a process 1115 for baking the semiconductor device. In one example, the baking of the semiconductor device is performed on the first dielectric material of process 1114, one or more contact elements of process 1113, one or more first semiconductor elements of process 1112, and the substrate of procedure 110. Includes bake. One purpose of the bake is to evaporate the solvent in the edge bead process. The baking of the semiconductor device can also increase the degree of planarization, reduce film defects, and crosslink the first dielectric material.

  In various embodiments, the semiconductor device is baked using two successive bake. The bake process can be performed at atmospheric pressure using a hot plate. Process 1115 can be performed, for example, in Rite Track 8800.

  The first bake is a bake at about 160 ° C. for about 60 seconds. In another example, the first bake may be a bake at about 150 ° C. for about 60 seconds. After completion of the first bake, in one example, the semiconductor device is cooled for about 30 seconds and then a second bake is performed. The semiconductor device can be cooled at room temperature (without using a cooling plate). In these examples, the semiconductor device is cooled because the handling system handles polytetrafluoroethylene (eg, Teflon from EI du Pont de Nemours and Company in Wilmington, Delaware). This is because a chuck coated with (trademark) material) is used. Placing a hot semiconductor device over a polytetrafluoroethylene coated chuck can damage the chuck. If other devices are used, the cooling process can optionally be omitted.

  After cooling the semiconductor device, the semiconductor device can be baked on the hot plate for a second time. In some embodiments, the second bake may be about 60 seconds above about 160 ° C. because 160 ° C. is the boiling point of PGMEA. For example, if the first bake is performed at 160 ° C., the second bake can be performed at about 170 ° C. for about 60 seconds. If the first bake is performed at 150 ° C., the second bake can be performed at about 200 ° C. for about 60 seconds. After the end of the second bake tail, the semiconductor device can be cooled again for 30 seconds. In another embodiment, a different order of baking can be performed.

  After the bake is complete, the next process in step 120 is a process 1116 of curing the first dielectric material. Curing of the first dielectric material can improve cross-linking of the first dielectric material. In one example, curing can be performed in a convection oven at atmospheric pressure (ie, approximately 1 atmosphere) in a nitrogen atmosphere.

  In various examples, the semiconductor device can be placed in an oven. Thereafter, the temperature in the oven can be raised to about 200 ° C. and the semiconductor device can be baked at about 200 ° C. for about 1 hour. To minimize outgassing of the first dielectric material of process 1114, the temperature is increased at a rate of about 1-2 ° C./min. After the bake is complete, the temperature is slowly decreased (eg, 1-2 ° C./min) to room temperature.

  In another embodiment, a bake procedure with 5 separate bake can be used. The first bake may be a bake at about 60 ° C. for about 10 minutes. The temperature rise time from room temperature to about 60 ° C. is about 10 minutes. After baking at about 60 ° C., the temperature is raised to about 160 ° C. in about 32 minutes. The semiconductor device is baked at about 160 ° C. for about 35 minutes.

  Next, after baking at 160 ° C., the temperature of the convection oven is increased to about 180 ° C. in about 10 minutes. The semiconductor device is baked at about 180 ° C. for about 20 minutes.

  After baking at 180 ° C., the temperature is raised to about 200 ° C. in about 50 minutes. The semiconductor device is baked at about 200 ° C. for about 60 minutes. Finally, during this baking procedure, the temperature in the oven is reduced to about 60 ° C. in about 70 minutes. The semiconductor device is baked at about 60 ° C. for about 10 minutes. After the bake is completed, the semiconductor device is cooled to approximately room temperature before proceeding with the procedure 120 of FIG. Semiconductor device baking can facilitate annealing of one or more contact elements.

Subsequently, the procedure 120 includes a process 1117 of providing a second dielectric material. In some examples, providing the second dielectric material includes depositing a second dielectric material over the organosiloxane dielectric layer (ie, the first dielectric material of process 1114). be able to. In some examples, the second dielectric material can include silicon nitride. In the same or different examples, the second dielectric material can include silicon oxynitride (SiO _x N _y ), silicon oxide, and / or silicon dioxide (SiO ₂ ). In some examples, the second dielectric material can be deposited using a low temperature PECVD process. In some examples, as part of providing the second dielectric material, the first dielectric material is covered with the second dielectric material. In one example, the end of the first dielectric material can be covered with a second dielectric material so that the first dielectric material is not exposed to subsequent oxygen (O ₂ ) plasma ashing. In some examples, the first dielectric material may be degraded by oxygen plasma ashing.

  The second dielectric material can be deposited with a thickness of about 0.1 μm to about 0.2 μm. A second dielectric material can be deposited to protect the first dielectric material from subsequent etching.

  The next process in procedure 120 is a process 1118 that provides a mask over the second dielectric material. The mask used in process 1118 may be an etching mask for the etching operation of process 1119 of FIG.

  In one example, process 1118 includes applying a patterned photoresist over a siloxane-based dielectric layer (ie, the first dielectric material of process 1114), or an organosiloxane-based dielectric (ie, Patterning the mask over the first dielectric material of process 1114). Similarly, process 1118 can include providing a patterned mask over the organosiloxane dielectric layer (ie, the first dielectric material of process 1114).

  In certain examples, the mask covers one or more portions of the first dielectric material and the second dielectric material that are not to be etched. A mask having a thickness that is not etched through the mask during the etching process of process 1119 of FIG. 11 may be provided. In some examples, the mask can have a thickness of about 3.5 μm or about 2.5 μm to about 5.0 μm.

  In some examples, the mask includes a photoresist. In one example, the photoresist may be AZ Electronic Materials MiR 900 Photoistist manufactured by AZ Materials, Luxemburg, Luxemburg. In one example, the photoresist is coated over the second dielectric material using Rite Track 8800. For example, a semiconductor device can be vapor primed and a mask (eg, photoresist) spin coated. After coating the semiconductor device, the semiconductor device is baked at about 105 ° C. for about 60 seconds.

  Next, the semiconductor device is aligned with the template and is exposed to UV (ultraviolet) light to transfer the mask image from the template to the mask. After exposure of the mask, the semiconductor device is baked at about 110 ° C. for about 90 seconds. The mask is then developed using a paddle of about 90 seconds with a standard developing compound to remove portions of the photoresist not exposed to UV light.

  After development is complete, a photo-registry flow process is performed on the mask for the remainder of the provision of the mask over the second dielectric material. Photoregistry flow is a process in which a mask is heated after development of the photoresist to cause the photoresist to flow into at least a semi-fluid.

  In one example, the semiconductor device is baked at about 140 ° C. for about 60 seconds. This photo-registry flow process reduces the sharpness of the mask edge so that, in the case of the process 1119 etch of FIG. 11, the sides of the vias in the first dielectric and the second dielectric have slopes. In one example, the magnitude of the inclination is about 30 degrees from the horizontal.

  Next, the procedure 120 includes a process 1119 for etching the base dielectric material, the first dielectric material, and the second dielectric material. Etching the base dielectric material, the first dielectric material, and the second dielectric material to form vias in the base dielectric material, the first dielectric material, and the second dielectric material. .

  In some examples, the base dielectric material, the first dielectric material, and the second dielectric material are etched in the same process using the same etch mask. In another example, the first dielectric material is etched in a first process, the second dielectric is etched in a second process, and the base dielectric is etched in a third process.

  In these other examples, the mask can be attached to the base dielectric material; the base dielectric material can be etched; before the first dielectric material is provided in process 1114 of FIG. Can be removed. Subsequently, a mask can be attached to the first dielectric material; the first dielectric material can be etched; before providing the second dielectric material in process 1118 of FIG. Can be removed. A mask can then be attached to the second dielectric material and the second dielectric material can be etched. In another example, the mask of process 1118 can be used to etch the second dielectric material; the mask can be removed; the patterned second dielectric material can be It can be used as a mask for patterning dielectric materials.

In many embodiments, the base dielectric material, the first dielectric material, and the second dielectric material are plasma etched. In the same of different embodiments, the base dielectric material, the first dielectric material, and the second dielectric material are reactive ion etched (RIE). In one example, the base dielectric material, the first dielectric material, and the second dielectric material are etched with a fluorine-based etchant. In some examples, the etchant may be trifluoromethane (CHF ₃ ), sulfur hexafluoride (SF ₆ ), or other fluorine-based etchant.

In some examples where the base dielectric material is not present (ie, process 1198 is omitted), the first material may be the organosiloxane dielectric material described above and the second material is silicon nitride. Good. In these examples, the first dielectric material and the second dielectric material can be RIE etched using sulfur hexafluoride (SF ₆ ) for about 4 minutes. If sulfur hexafluoride is used as the etchant, the etching can be performed in a 1: 2 sulfur hexafluoride to oxygen (O ₂ ) plasma chamber.

  The etch rates of the first dielectric material and the second dielectric material with sulfur hexafluoride are approximately the same (ie, about 0.5 μm / min). However, the etch rate of the second dielectric material is slightly faster than the first dielectric material. In one example, the pressure in the plasma chamber during etching is between about 50 mTorr and about 400 mTorr. RIE etching can be performed in Tegal 901 manufactured by Tegal Corporation of Petaluma, California.

  The second dielectric material can be etched before the first dielectric material; the first dielectric material can be etched before the base dielectric material. In many instances, the metal layer underlying the base dielectric material functions as an etch stop layer for the etching process. If sulfur hexafluoride is used as the etchant, the metal layer may be aluminum. In this embodiment, the metal layer cannot be molybdenum and tantalum because sulfur hexafluoride etches these two metals. In a different embodiment, the metal layer can comprise molybdenum and / or tantalum when the etching of the overlying second dielectric layer is a time lag etch.

  In some examples, buffered oxide etch (BOE) and chlorinated etchants cannot be used because if the first dielectric material includes an organosiloxane dielectric material, it will not be etched by them. FIG. 24 illustrates a cross-sectional view of an example device building region of a semiconductor device 1350 after etching etch-based dielectric material 2499, first dielectric material 2461, and second dielectric material 2462. FIG. After process 1119 of FIG. 11, semiconductor device 1350 can include via 2463 as shown in FIG. A via 2463 corresponds to the via region 2982 in FIG. The mask over the second dielectric layer 2462 is not shown in FIG.

  Referring again to FIG. 11, the next process in step 120 is a process 1120 for removing the mask. In one example, the mask is removed by ashing the mask (eg, photoresist) at a temperature below 110 ° C. If the mask is ashed at a temperature above 110 ° C., the first dielectric material may crack. Thus, in one example, mask ashing is performed at a temperature in the range of about 70 ° C to about 90 ° C. In the same or different examples, mask ashing is performed at a temperature in the range of about 77 ° C to about 84 ° C.

Ashing can be performed at a pressure of about 300 mTorr or less. During the ashing process, oxygen (O ₂ ) can be flowed into the chamber at a rate of about 50 sccm. In various examples, the ashing procedure can be performed in Tegal 901. After ashing the mask, the semiconductor device can be washed with deionized water and spin dried. In one example, the cleaning can be performed in a quick dump rinser and the drying can be performed in a spin rinse dryer.

  In another example, a wet strip can be used to remove the photoresist. In some embodiments, an N-methylpyrrolidinone (NMP) based stripper can be used.

  21 is a process 1121 that provides one or more second semiconductor elements. Examples of one or more second semiconductor elements can include a second metal layer, an indium tin oxide (ITO) layer, and a silicon nitride layer.

  As an example, FIG. 25 shows a cross-sectional view of an example device building region of a semiconductor device 1350 after providing a second metal layer 2564 and an ITO layer 2565. A second metal layer 2564 can be deposited over the second dielectric material 2462 and in at least a portion of the via 2463 (FIG. 24). The second metal layer 2564 can include molybdenum and can be about 0.15 μm thick. In one example, the second metal layer 2564 can be deposited by sputtering using KDF 744.

  An ITO layer 2565 can be deposited over the second metal layer 2564. The ITO layer 2565 can include indium tin oxide and can be about 0.05 μm thick. In one example, the ITO layer can be deposited by sputtering using KDF 744.

  In one example, the second metal layer 2564 is pattern etched. An ITO layer 2565 can then be deposited over the second metal layer 2564 and then pattern etched. As an example, the second metal layer 2564 and the ITO layer 2565 can be etched using AMAT 8330.

  FIG. 26 shows a cross-sectional view of an example device build region of a semiconductor device 350 after providing a silicon nitride layer 2666. FIG. The silicon nitride layer 2666 can transfer similar to the ITO layer 2565 and can be about 0.10 μm thick. In one example, the silicon nitride layer 2666 can be deposited by PECVD using AMAT P5000. In the same or another example, silicon nitride layer 2666 can be etched using Tegal 901 and ITO layer 2565 as a stop layer.

  After process 1121, procedure 120 is complete. Referring to FIG. 1, the next procedure of method 100 is a procedure 130 of removing a flexible substrate including a semiconductor element bonded to a flexible substrate from a carrier substrate. In one example, the flexible substrate can be removed from the carrier substrate by manually peeling the flexible substrate from the carrier substrate.

  Referring to another embodiment, FIG. 27 shows an example of a method 2700 for planarizing a flexible substrate. In the same or different embodiments, method 2700 can be viewed as a method of etching an organosiloxane dielectric material. Method 2700 can also be viewed as a method of etching an organosiloxane-based dielectric or a method of etching a siloxane-based dielectric material. The method 2700 is merely an example and is not limited to the embodiments provided herein. The method 2700 can be used in many different embodiments or examples that are not explicitly shown or described herein.

  Referring to FIG. 27, method 2700 includes procedure 2711. Procedure 2711 may be similar or identical to process 211 of FIG. The substrate may be similar or identical to the substrate 450 of FIG. In yet another embodiment, the procedure 2711 may be similar or identical to the method 110 of FIG. 1 and the substrate is similar or similar to the substrate 450 that may be part of the flexible substrate assembly 540. It may be the same.

  The method 2700 may continue to procedure 2712 for providing a first dielectric material. In some examples, the first dielectric material may be similar or identical to the second dielectric material 2462 of FIG. 24 and the process 1117 of FIG. For example, the second dielectric material 2462 can include a silicon nitride layer having a thickness of about 0.1 μm to about 0.2 μm.

  The next procedure in method 2700 is a procedure 2713 of providing a second dielectric material. The second dielectric material may be similar or identical to the first dielectric material 2461 of FIG. Procedure 2713 may be similar or identical to process 1114 of FIG.

  The method 2700 continues to procedure 2714 in which the second dielectric material is baked. In some examples, procedure 2714 may be similar or identical to process 1115 of FIG.

  Subsequently, the method 2700 includes a procedure 2715 for curing the second dielectric material. In some examples, procedure 2715 may be similar or identical to process 1116 of FIG.

  In another example, a different baking procedure with 5 separate bakes in a convection oven can be used. The first bake may be a bake at about 40 ° C. for about 10 minutes. The temperature rise time from room temperature to about 40 ° C. is about 2 minutes. After baking at 40 ° C., the temperature is increased to about 160 ° C. in about 32 minutes. Next, the flexible substrate is baked at about 160 ° C. for about 35 minutes.

  Next, after baking at 160 ° C., the temperature of the convection oven is increased to about 180 ° C. in about 10 minutes. The flexible substrate is baked at about 180 ° C. for about 20 minutes.

  After baking at 180 ° C., the temperature is increased to about 230 ° C. in about 50 minutes. Alternatively, the temperature is increased to about 230 ° C. at about 2 ° C./min. The flexible substrate is baked at about 230 ° C. for about 15 hours.

  Finally, during this baking procedure, the oven temperature is reduced to about 60 ° C. in about 85 minutes. The flexible substrate is baked at about 60 ° C. for about 10 minutes. After the bake is complete, the flexible substrate is cooled to approximately room temperature before proceeding with the method 2700 of FIG.

  The method 2700 continues at procedure 2716 with providing a third dielectric material. In some examples, the third dielectric material can be deposited with a thickness of about 0.2 μm to about 0.4 μm. In one example, the third dielectric material may be a silicon nitride layer having a thickness of about 0.3 μm. After deposition of the third dielectric material, the flexible substrate can be baked in situ at about 180 ° C. for about 5 minutes. In some examples, the third dielectric material may be similar or identical to the nitride passivation layer 1352 of FIG.

  FIG. 28 shows an example of a semiconductor device 2850 after providing a third dielectric material according to the second embodiment. In these examples, a first dielectric material 2871 is provided over the flexible substrate assembly 540. A second dielectric material 2872 is provided above the first dielectric material 2871 and a third dielectric material 2873 is provided above the second dielectric material 2872.

  After providing the third dielectric layer, method 2700 is complete. The resulting semiconductor device (2850 in FIG. 28) can be used as a flexible substrate provided in procedure 110 of method 100.

  Returning to the drawing, FIG. 31 shows an example of a semiconductor device manufacturing method 3100 according to one embodiment. The method 3100 is merely an example and is not limited to the embodiments provided herein. The method 3100 can be used in many different embodiments or examples that are not explicitly shown or described herein. The method 3100 may be similar to the method 120 (FIG. 2). In certain embodiments, the procedures, processes, and / or operations of method 3100 can be performed in the order described. In other embodiments, the procedures, processes, and / or operations of method 3100 can be performed in any other suitable order. In yet another embodiment, one or more procedures, processes, and / or operations of method 3100 may be combined or omitted.

  Referring now to FIG. 31, method 3100 includes a procedure 3101 for providing a substrate. In some embodiments, procedure 3101 may be similar or identical to process 211 (FIG. 2) and / or method 110 (FIG. 2). The substrate may be similar or identical to the substrate 3208 as shown in FIGS.

  Referring again to FIG. 31, the method 3100 may include a procedure 3102 that provides a barrier layer over and / or over the substrate. In some embodiments, procedure 3103 includes providing a gate metal layer over the barrier layer. In many embodiments, procedure 3102 is performed before procedure 3103 and / or after procedure 3101 as described below. The barrier layer may be similar or identical to the barrier layer 3209 as shown in FIGS. 32 and 33 and described below.

  Referring also to FIG. 31, the method 3100 includes a procedure 3103 for providing a gate metal layer over the substrate. In many embodiments, procedure 3103 is performed before procedures 3104 and / or 3105 and / or after procedure 3102 as described below. In some embodiments, procedure 3103 may be similar or identical to operation 1211 (FIG. 12). In various embodiments, the gate metal layer may be similar or identical to the gate metal layer 3202 as shown in FIGS. 32 and 33 and described below. FIG. 49 is a flowchart illustrating a procedure 3103 for providing a gate metal layer over a substrate according to one embodiment.

  In various embodiments, the procedure 3103 can include a process 4901 of depositing a gate metal layer over and / or over the substrate. Procedure 3103 can include a process 4902 of depositing and developing a first photoresist layer over the gate metal layer. Procedure 3103 can include a process 4903 of etching the gate metal layer with a first etchant while using the first photoresist layer as a first etch mask.

  FIG. 32 illustrates a cross-sectional view of an example device construction region of a semiconductor device 3200 after performing step 3103 according to one embodiment. As can be seen in FIG. 46, the cross-sectional view of the device build region is a cross-sectional view of a portion of the semiconductor device 3200 at line “a”. The device construction cross section includes a device construction contact region 4680 and a via region 4682. Further, FIG. 33 illustrates a cross-sectional view of an example gate contact construction region of a semiconductor device 3200 after performing procedure 3103 according to one embodiment. As can be seen in FIG. 46, a cross-sectional view of the gate contact build region is a cross-sectional view of a portion of semiconductor device 3200 at line “b”. The gate contact construction sectional view includes a sectional view of the gate contact region 4681. FIG. 46 is merely an example, and is not limited to the embodiments provided herein.

  In many embodiments, an electronic device (not shown) includes one or more semiconductor devices 3200, among other components. In many embodiments, the semiconductor device 3200 includes a transistor or thin film transistor. In the same or different embodiments, the electronic device can include a display, and the display includes a semiconductor device / transistor. In the same or different embodiments, the display can include either a liquid crystal display, an electrophoretic display, or an organic light emitting diode (OLED) display.

  In various examples, the semiconductor device 3200 includes an effective saturation mobility of 18.6 cm 2 / V · s and a threshold voltage shift of 2.2 volts or less under 10,000 seconds of positive and negative gate bias direct current (DC) stress. Can have. In another example, the semiconductor device 3200 can be processed at a temperature of about 200 ° C. or less.

  Referring to FIGS. 32 and 33, for example, the gate metal layer 3202 can be over the substrate 3208 and / or the barrier layer 3209. In the same or different embodiments, the gate metal layer 3202 can be on the barrier layer 3209.

In various embodiments, the substrate 3208 can include a rigid substrate and / or a flexible substrate. In some embodiments, the substrate 3208 may be a substrate 450 (FIG. 4), a portion of the flexible substrate assembly 540 (FIG. 5, 6, 8, 9, or 10), or a carrier substrate 651 (FIG. 6). It may be similar or identical.

  In many embodiments, the barrier layer 3209 can include a first dielectric material. The first dielectric material can include silicon dioxide and / or silicon nitride. In the same or different embodiments, the barrier layer 3209 may be similar or identical to the passivation layer 1352 (FIG. 13). In the same or different embodiments, the barrier layer 3209 may be about 200 nanometers or more thick and about 400 nanometers or less. In further embodiments, the barrier layer 3209 may be about 300 nanometers thick.

  In many embodiments, the gate metal layer 3202 can include one or more of molybdenum, aluminum, tantalum, chromium, or tungsten. In the same or different embodiments, the gate metal layer 3202 may be similar or identical to the patterned metal gate 1353 (FIG. 13). In the same or different embodiments, the gate metal layer 3202 can be about 100 nanometers or more thick and about 200 nanometers or less. In further embodiments, the gate metal layer 3202 may be about 150 nanometers thick.

  Referring now again to FIG. 31, the method 3100 may include a procedure 3104 that provides a gate barrier layer above and / or above the gate metal layer. In many embodiments, procedure 3104 is performed before procedure 3105 and / or after procedure 3103 as described below. The gate barrier layer may be similar or identical to the gate barrier layer 3510 as shown in FIGS. 35 and 36 and described below.

  Still referring to FIG. 31, method 3100 includes a procedure 3105 of providing a transistor active layer above the gate metal layer. In many embodiments, procedure 3105 is performed before procedure 3106 and / or after procedure 3104 as described below. FIG. 34 is a flowchart illustrating a procedure 3105 for providing a transistor active layer over a gate metal layer according to one embodiment. The transistor active layer may be similar or identical to the transistor active layer 3505 as shown in FIGS. 35 and 36 and described below, and the first active layer 4706 and the first active layer 4706 and as shown in FIG. 47 and described below. Two active layers 4707 may be included. In many embodiments, an etch stop layer (not shown) similar or identical to the etch stop layer 3511 may be present above and / or above the transistor active layer as shown in FIG. 35 and described below. it can.

  Procedure 3105 of FIG. 34 includes a process 3401 that provides a first active layer above and / or above the gate metal layer. In many embodiments, the first active layer may be similar to the first active layer 4706 as described below.

  In some embodiments, the process 3401 includes: (a) placing the substrate inside a vacuum chamber; and (b) inside the vacuum chamber, indium oxide, zinc oxide, gallium oxide, tin oxide, hafnium oxide, or oxide. Sputtering a target material comprising at least one of aluminum with a first feed gas comprising argon. In certain embodiments, the first feed gas can include nitrogen in addition to or instead of argon.

  The procedure 3105 of FIG. 34 includes a process 3402 that provides a second active layer above and / or above the first active layer. In the same or different embodiments, the second active layer may be similar to the second active layer 4707 as described below. With respect to the procedure 3105, in the case of a transistor active layer including only the first active layer, the semiconductor device may not be branched.

  In some embodiments, the process 3402 includes (a) mixing oxygen with a first feed gas to form a second feed gas comprising argon and 2 volume percent oxygen; and (b) a vacuum chamber. And sputtering the target material inside the vacuum chamber using a second supply gas. In various embodiments, process 3402 can occur immediately after process 3401. For example, process 3402 can be performed such that the oxygen supplied in process 3402 is simply added to the first feed gas, thereby transitioning process 3401 directly to process 3402.

  In many embodiments, process 3401 and / or process 3402 can be performed at a pressure of about 10 mTorr or more and about 20 mTorr or less. In the same or different embodiments, process 3401 and / or process 3402 may be performed at a pressure of about 16 millitorr. In the same or different embodiments, process 3401 and / or process 3402 can be performed at a temperature of about 25 ° C. or higher and about 39 ° C. or lower.

  The procedure 3105 of FIG. 34 can include a process 3403 of depositing and developing a second photoresist layer over the second active layer and / or the first active layer. In some embodiments, the second photoresist layer may be similar or identical to the first photoresist layer as described above with respect to process 4902. In many embodiments, the process 3403 can include depositing and developing a second photoresist layer over the etch stop layer, the second active layer, and / or the first active layer. . In many embodiments, the etch stop layer is similar or identical to the etch stop layer 3511 (FIG. 35).

  The procedure 3105 of FIG. 34 can include a process 3404 of etching the second active layer and the first active layer with a second etchant while using the second photoresist layer as a second etch mask. . In many embodiments, the process 3404 uses the second photoresist layer as a second etch mask while the etch stop layer, the second active layer, and the first active layer with a second etchant. Etching. In many embodiments, process 3404 can be performed using AMAT 8330. In some embodiments, the second etchant can include a dry etchant. In the same or different embodiments, the dry etchant can include oxygen, hydrogen chloride, and methane. In the same or different embodiments, oxygen, hydrogen chloride, and methane may be included in 10, 100, and 20 volumes. In many embodiments, the performance of process 3404 may be similar or identical to the etching of ITO layer 2565 (FIG. 25) as described above.

  In some embodiments, process 3403 and process 3404 can occur after process 3401 and can be repeated after process 3402. In the same or different embodiments, the second photoresist and / or the second etchant may be the same in both cases where process 3403 and process 3404 are performed, and one or both may be different. Good. In another embodiment, process 3403 and process 3404 can only occur after completion of both process 3401 and process 3402.

  FIG. 47 shows an example of a semiconductor device 3200 after performing processes 3401 and 3402. Referring to FIG. 47, for example, the first active layer 4706 can be above the gate metal layer 3202 and / or the second active layer 4707 is above the first active layer 4706. be able to. In various embodiments, the first active layer 4706 includes at least one first metal oxide and has a first conductivity. In the same or different embodiments, the second active layer 4707 includes at least one second metal oxide and has a second conductivity. Although not shown in FIG. 47, in certain embodiments, an etch stop layer similar or identical to the etch stop layer 3511 may be present above and / or above the second active layer 4707.

  In many instances, the use of oxides and different conductivities with the first active layer 4706 and / or the second active layer 4707 allows more mobility, more on than active layers composed of amorphous silicon. / Off current ratio and / or stability can be improved. As a result, a smaller semiconductor device can be obtained and the display resolution can be increased.

  In many embodiments, the at least one first metal oxide comprises one or more of indium oxide, zinc oxide, gallium oxide, tin oxide, hafnium oxide, or aluminum oxide in a ratio that is equal to or not equal to each other. Can be included. For example, in some embodiments, the at least one first metal oxide can include about 60 percent zinc oxide and about 40 percent indium oxide. In another example, the at least one first metal oxide can include indium oxide, gallium oxide, and zinc oxide in equal proportions to each other. In various embodiments, the at least one second metal oxide can include at least one first metal oxide. In the same or different embodiments, when the at least one second metal oxide comprises at least one first metal oxide, the at least one second metal oxide is at least one first metal oxide. The constituent compounds / elements of one metal oxide can be included, but the constituent compounds / elements can be included in different ratios, or at least one second metal oxide can contain at least one first Both metal oxide constituent compounds / elements and the relative proportions of the constituent compounds / elements can be included. In another embodiment, the at least one second metal oxide may be different from the at least one first metal oxide, and the at least one second metal oxide is at least 1 At least one type of constituent compound / element that is different from the type of first metal oxide and / or at least one type of first compound in a ratio different from the ratio of the at least one type of first metal oxide. (E.g., the at least one first metal oxide comprises about 60 percent zinc oxide and about 40 percent indium oxide, and the at least one second metal oxide). The object comprises indium oxide, gallium oxide and zinc oxide in equal proportions to each other or vice versa). In another example, both the at least one second metal oxide and the at least one first metal oxide include zinc oxide and indium oxide, but the at least one second metal oxide is The difference between the zinc oxide and indium oxide is about 60:40, and the difference between the at least one first metal oxide is smaller, such as when the ratio of zinc oxide to indium oxide is about 59:41. May be.

  In many embodiments, the transistor active layer 3505 may be about 40 nanometers or more thick and about 60 nanometers or less. In a further embodiment, transistor active layer 3505 may be about 50 nanometers thick. In the same or different embodiments, the first active layer 4706 may be about 5 nanometers or more thick and about 40 nanometers or less. In further embodiments, the first active layer 4706 may be about 5 nanometers or more thick and about 20 nanometers or less. Thus, in many embodiments, if the first active layer 4706 is, for example, 25 nanometers thick, the second active layer 4707 may be about 25 nanometers thick. In a further example, if the first active layer 4706 is 40 nanometers thick, the second active layer 4707 may be about 10 nanometers thick.

  In many embodiments, the first active layer 4706 has a first conductivity. For example, the first conductivity may be about 0.002 ohm centimeters. In the same or different embodiments, the second active layer 4707 has a second conductivity. For example, the second conductivity may be greater than or equal to about 10 ohm centimeters and less than or equal to about 200 ohm centimeters. In various embodiments, the first conductivity is higher than the second conductivity. In another embodiment, the first conductivity is lower than the second conductivity.

  Still referring to FIG. 31, the method 3100 includes a transistor active layer, a first active layer, and / or a second active layer, and / or a transistor active layer, a first active layer, and / or A procedure 3106 may be included that provides an etch stop layer above one of the second active layers. In many embodiments, procedure 3106 is performed before procedure 3107 and / or 3108 and / or after procedure 3105. The etch stop layer may be similar or identical to the etch stop layer 3511 as shown in FIGS. FIGS. 35 and 36 show an example of a semiconductor device 3200 after providing an etch stop layer above the transistor active layer.

  Referring to FIGS. 35 and 36, for example, the gate barrier layer 3510 may be above and / or above the gate metal layer 3202 and / or barrier layer 3209, below the transistor active layer 3505, and / or from the gate metal layer 3202 and transistor active. A layer 3505 may be present. In various embodiments, the gate barrier layer 3510 may be similar or identical to the gate dielectric layer 1554 (FIG. 15). In many embodiments, the gate barrier layer 3510 can include a second dielectric material. The second dielectric material can include silicon dioxide. The gate barrier layer 3510 may be buffered with silicon nitride or other dielectric on the side closest to the gate metal layer 3502. In the same or different embodiments, the gate barrier layer 3510 may be about 100 nanometers or more thick and about 300 nanometers or less.

  Referring again to FIGS. 35 and 36, in some embodiments, the transistor active layer 3505 can be above the gate metal layer 3202 and / or above and / or above the gate barrier layer 3510. Can do. The transistor active layer 3505 may include the first active layer 4706 (FIG. 47) and the second active layer 4707 (FIG. 47) as described above.

  Referring again to FIGS. 35 and 36, in some embodiments, an etch stop layer 3511 can be present above the transistor active layer 3505. In the same or different embodiments, the etch stop layer 3511 is above and / or above at least a portion of the transistor active layer 3505 and / or the gate barrier layer 3510 and below the source / drain contact layer 4150 (FIGS. 41 and 42). And / or between a portion of the transistor active layer 3505 and the source / drain contact layer 4150. In various embodiments, the etch stop layer 3511 may be similar or identical to the IMD layer 1556 (FIG. 15). In many embodiments, the etch stop layer 3511 can include a third dielectric material. The third dielectric material can include silicon dioxide. The etch stop layer 3511 can be buffered by silicon nitride on the side closest to the source / drain contact layer 4150. In the same or different embodiments, the etch stop layer 3511 may be about 50 nanometers or more thick and about 200 nanometers or less. In further embodiments, the etch stop layer 3511 may be about 100 nanometers thick.

  Still referring to FIG. 31, the method 3100 may include a procedure 3107 for providing a mesa passivation layer above and / or above the etch stop layer. In many embodiments, procedure 3107 may be similar or identical to operation 1213 (FIG. 12). In many embodiments, procedure 3107 is performed before procedure 3108 and / or after procedure 3106. The mesa passivation layer may be similar or identical to the mesa passivation layer 3712 as shown in FIGS. FIGS. 37 and 38 show an example of a semiconductor device 3200 after providing a mesa passivation layer above and / or above the etch stop layer.

  Referring to FIGS. 37 and 38, for example, the mesa passivation layer 3712 may be formed above and / or above the etch stop layer 3511, below the source / drain contact layer 4150 (FIGS. 41 and 42), and / or with the etch stop layer 3511. A source / drain contact layer 4150 may be present. In various embodiments, mesa passivation layer 3712 may be similar or identical to mesa passivation layer 1757 (FIG. 17). In many embodiments, the mesa passivation layer 3712 can include a fourth dielectric material. The fourth dielectric material can include silicon dioxide. In the same or different embodiments, the mesa passivation layer 3712 may be about 50 nanometers or more thick and about 200 nanometers or less. In further embodiments, the mesa passivation layer 3712 may be about 100 nanometers thick. Mesa passivation layer 3712 can protect the sidewalls of transistor active layer 3505 during the etching process.

  In many embodiments, the method 3100 can include a procedure 3108 for post-etching one or more mesa passivation layers that is similar or identical to the operation 1214 (FIG. 12) described above. 39 and 40 show a cross-sectional view of semiconductor device 3200 after post-etching one or more mesa passivation layers. For example, FIG. 40 shows the semiconductor device 3200 after performing contact gate etching in the gate contact construction area of the semiconductor device 3200. In the same or different examples, FIG. 39 shows the semiconductor device 3200 after etching the device build contact region in the device build area of the semiconductor device 3200. FIG. After procedure 3109, gate contact 4091 may be formed on semiconductor 3200. The gate contact 4091 corresponds to the gate contact region 4681 in FIG. After procedure 3109, device building contact 3990 is formed on semiconductor 3200. Device construction contact 3990 corresponds to device construction contact region 4680 of FIG.

  Still referring to FIG. 31, the method 3100 includes a procedure 3109 for providing a source / drain contact layer over the transistor active layer, the first active layer, and / or the second active layer. In the same or different embodiments, procedure 3109 may include providing a source / drain contact layer over a portion of the transistor active layer and / or over the mesa passivation layer. In some embodiments, procedure 3109 may be similar or identical to process 1113 (FIG. 11), and the source / drain contact layer is similar or identical to source / drain contact layer 4150 (FIG. 41). It may be. FIG. 48 is a flowchart illustrating a procedure 3109 for providing a source / drain contact layer over a transistor active layer, a first active layer, and / or a second active layer according to one embodiment.

  Referring to FIG. 48, in some embodiments, procedure 3109 includes depositing one or more metal layers over the transistor active layer, the first active layer, and / or the second active layer. Can do. In the same or different embodiments, the procedure 3109 can include a process 4801 of depositing a first metal layer over the transistor active layer, the first active layer, and / or the second active layer. In some embodiments, the process 4801 includes depositing a first metal layer over the transistor active layer, the first active layer, and / or the second active layer to form a source / drain contact layer. Can be included. In a further embodiment, procedure 3109 includes a process of depositing a second metal layer over the first metal layer to form a source / drain contact layer from the first metal layer and the second metal layer. 4802 can be included. In some embodiments, the first metal layer includes molybdenum and the second metal layer includes aluminum. In some embodiments, the procedure 3109 can include a process 4803 of depositing and developing a third photoresist layer over the source / drain contact layer. In a further embodiment, procedure 3109 can include a process 4804 of etching the source / drain contact layer with a third etchant while using the third photoresist layer as a third etch mask. In some embodiments, process 4802 can be omitted. In many embodiments, the third etchant may be a dry etchant. In the same or different embodiments, the dry etchant can include chlorine and boron trichloride, and / or chlorine and oxygen. In the same or different embodiments, chlorine and boron trichloride can be used to etch a first metal layer (eg, aluminum) and chlorine and oxygen cab are used to etch a second metal layer.

  FIG. 41 shows a cross-sectional view of an example device construction area of semiconductor device 3200 after procedure 3109 is completed. Further, FIG. 42 shows a cross-sectional view of an exemplary gate contact construction area of the semiconductor device 3200 after the procedure 3109 is completed.

  Referring to FIGS. 41 and 42, for example, a source / drain contact layer 4150 may be present above the transistor active layer 3505. In the same or different embodiments, the source / drain contact layer 4150 can be on the transistor active layer 3505. Referring again to FIG. 31, in various embodiments, the source / drain contact layer 4150 can include a first source / drain contact 4104 and / or a second source / drain contact 4105. In some embodiments, the first source / drain contact 4104 can include a transistor drain contact, and the second source / drain contact 4105 can include a transistor source contact, or vice versa. . In the same or different embodiments, the source / drain contact layer 4150 can be above and / or above one or both of the mesa passivation layer 3712 and the transistor active layer 3505. In various embodiments, the source / drain contact layer 4150 can include at least one of molybdenum or aluminum. In the same or different embodiments, the source / drain contact layer 4150 may be about 100 nanometers or more thick and about 200 nanometers or less. In further embodiments, the source / drain contact layer 4150 may be about 150 nanometers thick.

  Still referring to FIG. 31, the method 3100 may include a procedure 3110 that provides a base dielectric material that is similar or identical to the process 1198 (FIG. 11). In the same or different embodiments, the method 3100 may include a procedure 3111 for providing a fifth dielectric material that is similar or identical to the process 1114 (FIG. 11). In the same or different embodiments, the method 3100 may include a procedure for baking a semiconductor device that is similar or identical to the process 1115 (FIG. 11). In the same or different embodiments, method 3100 may include a procedure 3112 for curing a fifth dielectric material that is similar or identical to process 1116 (FIG. 11). In the same or different embodiments, the method 3100 may include a procedure 3113 that provides a sixth dielectric material that is similar or identical to the process 1117 (FIG. 11). In the same or different embodiments, the method 3100 may include a procedure 3114 that provides a mask over the sixth dielectric material that is similar or identical to the process 1118 (FIG. 11). In the same or different embodiments, the method 3100 includes a procedure 3115 for etching a base dielectric material, a fifth dielectric material, and a sixth dielectric material similar or identical to the process 1119 (FIG. 11). be able to. In the same or different embodiments, method 3100 may include a procedure 3116 for removing the mask that is similar or identical to process 1120 (FIG. 11). In the same or different embodiments, the method 3100 may include a procedure 3117 that provides one or more semiconductor devices that are similar or identical to the process 1121 (FIG. 11). In various embodiments, one or more of procedures 3110-3117 can be omitted.

  FIG. 43 is a cross-sectional view of an example device construction region of the semiconductor device 3200 after the procedures 3101 to 3116 are performed. Referring to FIG. 43, a dielectric material 4399, a fifth dielectric material 4361, and a sixth dielectric material 4362 are deposited over the source / drain contact layer 4150. Dielectric material 4399, fifth dielectric material 4361, and / or sixth dielectric material 4362 may be dielectric material 2499 (FIG. 24), first dielectric material 2461 (FIG. 24), and / or, respectively. It may be similar to the second dielectric material 2462 (FIG. 24). After procedure 3114 (FIG. 31), semiconductor device 3200 may include vias 4363 as shown in FIG. 43, which may be similar or identical to vias 2463 (FIG. 24). A via 4363 corresponds to the via region 4682 in FIG. The mask over sixth dielectric layer 4362 is not shown in FIG.

  In one embodiment, FIG. 44 shows a cross-sectional view of an example device construction region of semiconductor device 3200 after performing procedure 3117. Referring to FIG. 44, a third metal layer 4464 and an ITO layer 4465 can be provided over the sixth dielectric material 4362. In the same or different embodiments, a third metal layer 4464 can be provided above the sixth dielectric material 4362 and in at least a portion of the via 4363 (FIG. 43). In many embodiments, the third metal layer 4464 and the ITO layer 4465 may be similar to the second metal layer 2564 (FIG. 25) and the ITO layer 2565 (FIG. 25), respectively.

  In another embodiment, different from the embodiment shown in FIG. 44, FIG. 45 shows a cross-sectional view of another example device construction region of semiconductor device 3200 after performing procedure 3117. Referring to FIG. 45, a silicon nitride layer 4566 can be provided over the ITO layer 4465.

  Although the invention has been described with reference to particular embodiments, those skilled in the art will recognize that various modifications can be made without departing from the spirit and scope of the invention. Accordingly, the disclosure of the embodiments is intended as an example of the scope of the present invention and not as a limitation. It is intended that the scope of the invention be limited only to the extent required by the appended claims. The semiconductor devices and methods of providing semiconductor devices discussed herein can be implemented in various embodiments, and the specific discussion of these embodiments described above provides a complete description of all possible embodiments. It will be readily apparent to those skilled in the art that this does not necessarily mean. Rather, the detailed description of the drawings and / or the drawings themselves disclose at least one preferred embodiment and may disclose alternative embodiments. For example, except for the respective active layer, the semiconductor devices 1350 (FIGS. 13-22, 24-26, and 29) and 3200 (FIGS. 32-33 and 35-47) may be similar or identical to each other, Methods 120 (FIG. 11) and 3100 (FIG. 31) may be similar or identical to each other.

  All elements claimed in any particular claim are essential to the embodiment claimed in that particular claim. Thus, replacing one or more claimed elements is reconstituted and cannot be compensated. In addition, benefits, other advantages, and solutions to problems have been described with regard to specific embodiments. However, these benefits, benefits, solutions to problems, and any one or more factors that may generate or become more prominent in any benefit, advantage, or solution are such benefits. If an advantage, solution, or use is not expressly recited in a claim, it should not be construed as an important, essential, or essential feature or element of any or all such claims .

  Further, the embodiments and limitations disclosed herein are not explicitly claimed in (1) the claims, and (2) the claims are clearly based on the doctrine of equivalents. Is not equivalent to a public element based on the principle of public ownership.

Claims (33)

A gate metal layer,
A transistor active layer above the gate metal layer;
A source / drain contact layer above the transistor active layer, comprising a source / drain contact layer including a first source / drain contact and a second source / drain contact;
The transistor active layer is
A first active layer above the gate metal layer, the first active layer comprising at least one first metal oxide; and
A second active layer above the first active layer, the second active layer comprising at least one second metal oxide,
The first active layer has a first conductivity;
The second active layer has a second conductivity;
The first conductivity is higher than the second conductivity;
An electronic device characterized by that. Further comprising a substrate,
The gate metal layer is above the substrate;
The substrate includes one of a rigid substrate or a flexible substrate,
If the substrate comprises the rigid substrate, the rigid substrate comprises silicon;
If the substrate comprises the flexible substrate, the flexible substrate comprises one of plastic or stainless steel, and the plastic comprises polyethylene napthalate;
The electronic device according to claim 1. The transistor active layer is on the gate metal layer;
The first source / drain contact is on the transistor active layer;
The second source / drain contact is on the transistor active layer;
The electronic device according to claim 1, wherein the electronic device is an electronic device. And further comprising one of a liquid crystal display, an electrophoretic display, or an organic light emitting diode display comprising the transistor.
The electronic device according to claim 1, wherein: The at least one first metal oxide includes at least one of indium oxide, zinc oxide, gallium oxide, tin oxide, hafnium oxide, and aluminum oxide.
The electronic device according to claim 1, wherein the electronic device is an electronic device. The at least one first metal oxide comprises about 60 percent zinc oxide and about 40 percent indium oxide.
The electronic device according to claim 1, wherein the electronic device is an electronic device. The at least one first metal oxide includes indium oxide, gallium oxide, and zinc oxide in an equal ratio to each other.
The electronic device according to claim 1, wherein the electronic device is an electronic device. The at least one type of second metal oxide includes the at least one type of first metal oxide.
The electronic device according to claim 1, wherein the electronic device is an electronic device. The first active layer is about 5 nanometers or more thick and about 40 nanometers or less;
The electronic device according to claim 1, wherein: The transistor active layer has a thickness of about 40 nanometers or more and a thickness of about 60 nanometers or less;
The electronic device according to claim 1, wherein the electronic device is an electronic device. The gate metal layer includes at least one of molybdenum, aluminum, tantalum, chromium, and tungsten.
The electronic device according to claim 1, wherein the electronic device is an electronic device. The source / drain contact layer includes at least one of molybdenum and aluminum;
The source / drain contact layer has a thickness of about 100 nanometers or more and a thickness of about 200 nanometers or less.
The electronic device according to claim 1, wherein the electronic device is an electronic device. A barrier layer;
The gate metal layer exists above the barrier layer;
The barrier layer includes a first dielectric material;
The first dielectric material comprises at least one of silicon dioxide and silicon nitride;
The barrier layer has a thickness of about 200 nanometers or more and a thickness of about 400 nanometers or less;
The electronic device according to claim 1, wherein the electronic device is an electronic device. A gate barrier layer between the gate metal layer and the transistor active layer;
The gate barrier layer includes a second dielectric material;
The second dielectric material comprises silicon dioxide;
The gate barrier layer has a thickness of about 100 nanometers or more and a thickness of about 300 nanometers or less;
The electronic device according to claim 1, wherein the electronic device is an electronic device. An etch stop layer above the transistor active layer;
The etch stop layer exists between (a) a portion of the transistor active layer and (b) the source contact and the drain contact;
The etch stop layer includes a third dielectric material;
The third dielectric material comprises silicon dioxide;
The etch stop layer is about 50 nanometers or more thick and about 200 nanometers or less;
The electronic device according to claim 1, wherein the electronic device is an electronic device. Further comprising a mesa passivation layer above the etch stop layer;
The mesa passivation layer exists between (a) the etch stop layer and (b) the source / drain contact layer;
The mesa passivation layer includes a fourth dielectric material;
The fourth dielectric material comprises silicon dioxide;
The mesa passivation layer is about 50 nanometers or more thick and about 200 nanometers or less;
The electronic device according to claim 15. A substrate,
A barrier layer on the substrate;
A gate metal layer on the barrier layer;
A gate barrier layer on the gate metal layer;
A transistor active layer on the gate barrier layer;
An etch stop layer on the transistor active layer;
A mesa passivation layer on the etch stop layer;
A source / drain contact layer on the mesa passivation layer and the transistor active layer, and
The transistor active layer is
A first active layer on the gate metal layer, the first active layer including at least one first metal oxide; and on the first active layer and the first active layer. A second active layer between the layer and the etch stop layer, the second active layer comprising at least one second metal oxide,
The first active layer has a first conductivity;
The second active layer has a second conductivity;
The first conductivity is higher than the second conductivity;
A semiconductor device characterized by that. The at least one first metal oxide includes at least one of indium oxide, zinc oxide, gallium oxide, tin oxide, hafnium oxide, and aluminum oxide.
The semiconductor device according to claim 17. The at least one type of second metal oxide includes the at least one type of first metal oxide.
The semiconductor device according to claim 17 or 18, wherein The first active layer has a thickness of about 5 nanometers or more and a thickness of about 40 nanometers or less.
The semiconductor device according to claim 17, wherein the semiconductor device is a semiconductor device. The transistor active layer has a thickness of about 40 nanometers or more and a thickness of about 60 nanometers or less.
The semiconductor device according to claim 17, wherein the semiconductor device is a semiconductor device. A method for manufacturing a semiconductor device, comprising:
Providing a substrate;
Providing a gate metal layer over the substrate;
Providing a first active layer over the gate metal layer, the first active layer including at least one first metal oxide and having a first conductivity; When,
Providing a second active layer above the first active layer, the second active layer including at least one second metal oxide and the first conductivity; Having a lower second conductivity than:
Providing a source / drain contact layer over the second active layer;
The manufacturing method characterized by including. The substrate includes one of a rigid substrate and a flexible substrate;
If the substrate comprises the rigid substrate, the rigid substrate comprises silicon;
If the substrate comprises the flexible substrate, the flexible substrate comprises one of plastic and stainless steel, and the plastic comprises polyethylene naphthalate;
23. The method of claim 22, wherein: Providing a gate metal layer over the substrate comprises:
Depositing at least one of molybdenum, aluminum, tantalum, chromium, and tungsten over the substrate;
Depositing and developing a first photoresist layer over the gate metal layer;
Etching the gate metal layer with a first etchant while using the first photoresist layer as a first etch mask.
24. A method according to claim 22 or 23. Providing the second active layer above the first active layer comprises:
Depositing the at least one second metal oxide on the first active layer;
Depositing and developing a second photoresist layer over the second active layer;
Etching the second active layer and the first active layer with a second etchant while using the second photoresist layer as a second etching mask.
25. A method according to any one of claims 22 to 24. Providing a source / drain contact layer above the second active layer comprises:
Depositing at least one of molybdenum and aluminum over the second active layer;
Depositing and developing a third photoresist layer over the source / drain contact layer;
Etching the source / drain contact layer with a third etchant while using the third photoresist layer as a third etching mask;
26. The method according to any one of claims 22 to 25, comprising: Providing the first active layer above the gate metal layer comprises:
Placing the substrate inside a vacuum chamber;
Sputtering of a target material containing at least one of indium oxide, zinc oxide, gallium oxide, tin oxide, hafnium oxide, and aluminum oxide inside the vacuum chamber is performed using a first supply gas containing argon. Steps to be performed,
27. A method according to any one of claims 22 to 26, comprising: Providing the second active layer above the first active layer comprises:
Mixing oxygen with the first feed gas to form a second feed gas comprising argon and 2 volume percent oxygen;
Performing sputtering of the target material within the vacuum chamber using the second supply gas within the vacuum chamber;
28. The method of claim 27, comprising: The at least one type of second metal oxide includes the at least one type of first metal oxide.
29. A method according to any one of claims 22 to 28. Providing a first active layer above the gate metal layer and providing a second active layer above the first active layer at a pressure of about 10 mTorr or more and about 20 mTorr or less; At a temperature of about 25 ° C. or higher and about 39 ° C. or lower,
30. A method as claimed in any one of claims 22 to 29. Providing a barrier layer over the substrate prior to providing the gate metal layer over the substrate, the barrier layer including at least one of silicon dioxide and silicon nitride. Steps,
Providing a gate barrier layer above the gate metal layer prior to providing the first active layer above the gate metal layer, the gate barrier layer comprising silicon dioxide; ,
Providing an etch stop layer above the second active layer prior to providing the source / drain contact layer above the second active layer, the etch stop layer being silicon dioxide Including steps,
Providing a mesa passivation layer over the etch stop layer, the mesa passivation layer comprising silicon dioxide;
Further comprising providing at least one material layer over the substrate, including at least one of:
31. A method according to any one of claims 22-30. Providing at least one layer of material over the substrate comprises:
Providing a barrier layer on the substrate prior to providing the gate metal layer over the substrate, the barrier layer including at least one of silicon dioxide and silicon nitride. When,
Providing a gate barrier layer on the gate metal layer prior to providing the first active layer over the gate metal layer, the gate barrier layer comprising silicon dioxide;
Providing an etch stop layer on the second active layer prior to providing the source / drain contact layer over the second active layer, wherein the etch stop layer comprises silicon dioxide; Including steps;
Providing a mesa passivation layer on the etch stop layer, the mesa passivation layer comprising silicon dioxide;
Further comprising at least one of
31. A method as claimed in any one of claims 23 to 30. Providing the gate metal layer over the substrate includes providing the gate metal layer on the barrier layer;
Providing the first active layer over the gate metal layer comprises providing the first active layer on the gate barrier layer;
Providing a second active layer over the first active layer includes providing the second active layer on the first active layer;
33. A method as claimed in any one of claims 22 to 32.

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