CN103545407B - 防止漏电流结构及其制造方法 - Google Patents
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- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
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- 125000006850 spacer group Chemical group 0.000 description 1
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Abstract
提供了一种防止漏电流结构及其制造方法。一种防止漏电流结构,包括:一基板;在所述基板上的一第一III-V族化合物层;在所述第一III-V族化合物层上的一第二III-V族化合物层;以及在所述第二III-V族化合物层上的至少一半导体组件;其中所述第一III-V族化合物层与所述第二III-V族化合物层接触,共同形成一高阻值层,以防止所述至少一半导体组件所产生的漏电流流至所述基板。
Description
技术领域
本发明涉及防止漏电流技术,特别涉及一种防止漏电流结构及其制造方法。
背景技术
图1是示出传统半导体组件100的剖面示意图,在硅(Si)基板11上形成有作为缓冲层的氮化镓(GaN)层12。接着,形成空间(spacer)层13用以形成晶体管或二极管等半导体组件。当操作图1所示的传统半导体组件时,空间层13所产生的电流会经由氮化镓(GaN)层12而流至硅基板11,从而造成漏电流现象,这会影响晶体管或二极管等组件的功率损耗以及操作效率。为了防止漏电流现象,一般会将氮化镓(GaN)层12或缓冲层的厚度提高,此厚度通常远比组件厚度大,但仍无法完全防止漏电流情况。
鉴于漏电流是III族氮化物的一个重大问题,因此亟需提出一种新颖机制以避免或防止漏电流对于半导体组件的影响。
发明内容
鉴于上述,本发明实施例提出一种防止漏电流结构及其制造方法,可有效防止半导体组件的漏电流流至基板,因而得以有效改善操作效率、功率损耗、噪声以及可靠度等特性。
根据本发明实施例,防止漏电流流结构包括基板、第一III-V族化合物层、第二III-V族化合物层以及至少一半导体组件。其中,第一III-V族化合物层位于基板上,第二III-V族化合物层位于第一III-V族化合物层上,且组件位于第二III-V族化合物层上。其中第一III-V族化合物层与第二III-V族化合物层接触,共同形成一高阻值层,以防止至少一半导体组件所产生的漏电流流至基板。
一种防止漏电流结构的制造方法,包括:提供一基板;在所述基板上形成一第一III-V族化合物层;在所述第一III-V族化合物层上形成一第二III-V族化合物层;以及在所述第二III-V族化合物层上形成至少一半导体组件;其中所述第一III-V族化合物层与所述第二III-V族化合物层接触,共同形成一高阻值层,以防止所述至少一半导体组件所产生的电流流至所述基板。
附图说明
图1是示出传统半导体组件的剖面示意图。
图2是示出本发明实施例的防止漏电流结构的剖面示意图。
图3是示出本发明实施例另一防止漏电流结构的剖面示意图。
附图标号说明
100:半导体组件
11:硅(Si)基板
12:氮化镓(GaN)层
13:空间层
200:防止漏电流结构
300:防止漏电流结构
21:基板
22:缓冲层
23:第一III-V族化合物层
24:第二III-V族化合物层
25:半导体组件
251:第一掺杂层
252:发光层
253:第二掺杂层
254:第一n掺杂层
255:p掺杂层
256:第二n掺杂层
C:集极
B:基极
E:射极
具体实施方式
图2是示出本发明实施例的防止漏电流结构200的剖面示意图。本实施例可适用于半导体的半导体组件(例如晶体管或二极管),以防止半导体组件所产生漏电流流至基板21,从而可以提高半导体组件的效能。
首先,提供一基板21(例如硅基板或蓝宝石基板),其可以是导电基板或者绝缘基板。接着,可选择性地在基板21上形成缓冲层22。视应用需求,在缓冲层22与基板21之间,还可形成另一层级或多层级。本实施例的缓冲层22的材质例如氮化镓(GaN),但不局限于此。上述缓冲层22可用于晶格匹配,以便后续层级的形成。上述缓冲层22也可用于应力舒缓,以提高半导体组件的效能。上述缓冲层22还可作为表面修改(surfacemodification),以改变缓冲层22底面(例如基板21)表面的物理或化学特性。
本实施例的缓冲2不像传统结构的缓冲层12(如图1所示)那样用来阻隔漏电流。因此,本实施例的缓冲层22的厚度较薄,例如小于1000纳米,一般若无与基板21结合后有晶格匹配问题,甚至可以省略,因此设计上不像传统结构的缓冲层12那样需要较大的厚度。
接下来,在缓冲层22之上依次形成第一III-V族化合物层23以及第二III-V族化合物层24。视应用需求,在缓冲层22与第一III-V族化合物层23之间还可形成另一层级或多层级。本实施例的第一III-V族化合物层23与第二III-V族化合物层24接触,共同形成一高阻值层或绝缘层。本实施例中所谓“高阻值”是指电阻值为一万欧姆以上。在本实施例中,第一III-V族化合物层23可以是III族氮化物层,包含氮化铟镓(InxGa1-XN,x>0),而第二III-V族化合物层24可以是III族氮化物层,包含氮化铝(AlN)。在一实施例中,第一III-V族化合物层23的厚度小于或等于50纳米,且第二III-V族化合物层24的厚度小于或等于100纳米。第一III-V族化合物层23与第二III-V族化合物层24所形成的高阻值层的厚度小于或等于150纳米。
接下来,在第二III-V族化合物层24上形成至少一半导体组件25。视应用需求,在第二III-V族化合物层24与组件25之间还可形成另一层级或多层级。图2所示半导体组件25是以发光二极管作为例示,其主要(由下而上)依次形成有第一掺杂层251、发光层252以及第二掺杂层253。图3是示出本发明实施例的另一防止漏电流结构300的剖面示意图,所示组件25是以晶体管作为例示,其主要依次形成有第一n掺杂层254、p掺杂层255以及第二n掺杂层256,分别连接至集极C、基极B以及射极E,从而形成NPN型双极性晶体管。
根据上述图2或图3所示的结构,由于第一III-V族化合物层23与第二III-V族化合物层24所形成的高阻值层的电阻值为一万欧姆以上,因此,可以有效防止半导体组件25所产生的漏电流流至基板21,使得组件25的操作效率、功率损耗、噪声以及可靠度等特性可得到显著改善。此外,本实施例所使用的高阻值层23/24厚度极小,不但工艺简便,且不会影响到组件25的特性。
以上所述仅是本发明的较佳实施例,并非用来限定本发明的范围;凡其它未脱离本发明所揭示的精神下所完成的等效改动或改进,均应包含在本发明的权利要求范围内。
Claims (12)
1.一种防止漏电流结构,包括:
一基板;
在所述基板上的一第一III-V族化合物层,其中所述第一III-V族化合物层包含氮化铟镓,且其厚度小于或等于50纳米;
在所述第一III-V族化合物层上的一第二III-V族化合物层,其中所述第二III-V族化合物层包含氮化铝,且其厚度小于或等于100纳米;以及
在所述第二III-V族化合物层上的至少一半导体组件;
其中所述第一III-V族化合物层与所述第二III-V族化合物层接触,共同形成一高阻值层,以防止所述至少一半导体组件所产生的漏电流流至所述基板。
2.如权利要求1所述的防止漏电流结构,还包括形成在所述基板与所述第一III-V族化合物层之间的一缓冲层。
3.如权利要求2所述的防止漏电流结构,其中所述缓冲层由氮化镓构成。
4.如权利要求1所述的防止漏电流结构,其中所述高阻值层的电阻值是一万欧姆以上。
5.如权利要求1所述的防止漏电流结构,其中所述至少一半导体组件是一晶体管。
6.如权利要求5所述的防止漏电流结构,其中所述晶体管是一NPN型双极性晶体管,包括:
在所述第二III-V族化合物层上的一第一n掺杂层;
在所述第一n掺杂层上的一p掺杂层;以及
在所述p掺杂层上的一第二n掺杂层;
其中所述第一n掺杂层、所述p掺杂层以及所述第二n掺杂层分别连接至一集极、一基极以及一射极。
7.一种防止漏电流结构的制造方法,包括:
提供一基板;
在所述基板上形成一第一III-V族化合物层;
在所述第一III-V族化合物层上形成一第二III-V族化合物层;以及
在所述第二III-V族化合物层上形成至少一半导体组件;
其中所述第一III-V族化合物层与所述第二III-V族化合物层接触,共同形成一高阻值层,以防止所述至少一半导体组件所产生的漏电流流至所述基板。
8.如权利要求7所述的防止漏电流结构的制造方法,还包括在所述基板与所述第一III-V族化合物层之间形成一缓冲层。
9.如权利要求7所述的防止漏电流结构的制造方法,其中所述高阻值层的电阻值是一万欧姆以上。
10.如权利要求7所述的防止漏电流结构的制造方法,其中所述第一III-V族化合物层包含氮化铟镓,且所述第二III-V族化合物层包含氮化铝。
11.如权利要求7所述的防止漏电流结构的制造方法,其中所述第一III-V族化合物层的厚度小于或等于50纳米,且所述第二III-V族化合物层的厚度小于或等于100纳米。
12.如权利要求7所述的防止漏电流结构的制造方法,其中所述至少一半导体组件是一晶体管。
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JPH0236584A (ja) * | 1988-07-27 | 1990-02-06 | Matsushita Electric Ind Co Ltd | 光電子集積回路およびその製造方法 |
JP4531071B2 (ja) * | 2007-02-20 | 2010-08-25 | 富士通株式会社 | 化合物半導体装置 |
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CN101101924A (zh) * | 2006-07-05 | 2008-01-09 | 大同股份有限公司 | 一种具低热载子效应的半导体结构 |
CN101276792A (zh) * | 2007-03-30 | 2008-10-01 | 富士通株式会社 | 半导体外延衬底、化合物半导体器件及其制造方法 |
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