CN103545176B - 用于将碳导入半导体结构的方法及由此形成的结构 - Google Patents

用于将碳导入半导体结构的方法及由此形成的结构 Download PDF

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CN103545176B
CN103545176B CN201310044204.0A CN201310044204A CN103545176B CN 103545176 B CN103545176 B CN 103545176B CN 201310044204 A CN201310044204 A CN 201310044204A CN 103545176 B CN103545176 B CN 103545176B
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CN103545176A (zh
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苏玉珍
陈煌明
聂俊峰
苏培钊
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

实施例是一种包括通过衬底的表面扩散碳、通过衬底的表面注入碳以及在通过衬底表面扩散碳和注入碳之后对衬底进行退火的方法。衬底包括第一栅极、栅极间隔件、蚀刻停止层以及层间介电层。第一栅极位于半导体衬底上方。栅极间隔件沿着第一栅极的侧壁。蚀刻停止层位于栅极间隔件的表面上以及半导体衬底的表面上方。层间介电层位于蚀刻停止层的上方。衬底的表面包括层间介电层的表面。本发明还提供了用于将碳导入半导体结构的方法及由此形成的结构。

Description

用于将碳导入半导体结构的方法及由此形成的结构
技术领域
本发明一般地涉及半导体技术领域，更具体地，涉及半导体结构及其形成方法。
背景技术
由于集成电路(IC)的发展，半导体产业寻求继续改进IC的性能或者尺寸。许多这种改进集中于更小的特征尺寸，使得可以提高IC的速度。通过减小部件尺寸，提高了IC上的器件密度(例如，晶体管、二极管、电阻器、电容器等)。通过提高密度，器件之间的间距通常会减小，从而允许器件之间更小的电阻和电容。因此，可以减小电阻-电容(RC)时间常数。
随着器件之间的间距减小，确保上覆层中的部件(例如，接触件)与下面的衬底中的部件(例如，源极或者漏极)的适当对准通常变得更困难。在较小的技术节点中容限变得非常小，并且上覆层小量的未对准会导致可以产生器件故障的覆盖问题。
另外，为了防止未对准所导致的故障，器件中的部件在更小的技术节点中变得更薄且更弱。这些薄层不能经受对这些层没有选择性的蚀刻剂。更进一步，尤其在现在正在开发的发展中后栅极工艺中，这些部件会从不同侧暴露于蚀刻剂。蚀刻剂对这些部件的损害会导致后续不期望的导电部件之间的短路，从而会导致器件失效。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种方法，包括：透过衬底的表面扩散碳，所述衬底包括：第一栅极，位于半导体衬底上方，栅极间隔件，沿着所述第一栅极的侧壁，蚀刻停止层，位于所述栅极间隔件的表面上以及所述半导体衬底的表面上方，以及层间介电层，位于所述蚀刻停止层上方，所述衬底的所述表面包括所述层间介电层的表面；以及透过所述衬底的所述表面注入碳；以及在透过所述衬底的所述表面扩散碳和注入碳之后，对所述衬底进行退火。
在该方法中，透过所述衬底的所述表面扩散碳包括：将所述衬底的所述表面暴露于含碳等离子体。
在该方法中，透过所述衬底的所述表面注入碳包括：沿着所述栅极间隔件的表面，将碳注入到所述间隔件的一部分和所述蚀刻停止层的一部分中。
在该方法中，以与所述衬底的所述表面正交的角度实施注入碳。
在该方法中，以与所述衬底的所述表面不正交的第一角度的第一注入以及以与所述第一角度互补的第二角度的第二注入实施注入碳。
该方法进一步包括：在对所述衬底进行退火之后，去除所述第一栅极，并且在所述第一栅极被去除的区域中形成第二栅极。
该方法进一步包括：穿过所述层间介电层和所述蚀刻停止层蚀刻接触开口到达所述半导体衬底的所述表面。
在该方法中，在扩散碳和注入碳之前，所述栅极间隔件和所述蚀刻停止层都包括氮化硅。
根据本发明的另一方面，提供了一种方法，包括：在从衬底的表面到所述衬底中位于所述衬底的所述表面之下的第一深度的方向上形成第一梯度的碳，形成所述第一梯度的碳包括将所述衬底的所述表面暴露于含碳等离子体，所述衬底包括：栅极间隔件，沿着第一栅极的侧壁，所述栅极间隔件位于半导体衬底上方；蚀刻停止层，沿着所述栅极间隔件的侧壁并位于所述半导体衬底上方；和层间介电层，位于所述蚀刻停止层上方；在从所述衬底的所述表面到所述衬底中位于所述第一深度之下的第二深度的方向上形成第二梯度的碳，形成所述第二梯度的碳包括透过所述衬底的所述表面注入碳；以及在形成所述第一梯度的碳和形成所述第二梯度的碳之后，对所述衬底进行退火。
在该方法中，所述第一梯度的碳包括在从所述衬底的所述表面到所述第一深度的方向上降低的碳浓度，并且所述第二梯度的碳包括从所述衬底的所述表面到所述第二深度的方向上增加且随后降低的碳浓度。
在该方法中，将所述衬底的所述表面暴露于所述含碳等离子体通过扩散碳而形成所述第一梯度的碳。
在该方法中，以与所述衬底的所述表面正交的角度实施透过所述衬底的所述表面注入碳。
在该方法中，透过所述衬底的所述表面注入碳包括第一注入角的第一注入和与所述第一注入角互补的第二注入角的第二注入。
该方法进一步包括：在对所述衬底进行退火之后，去除所述第一栅极，并且在所述第一栅极被去除的区域中形成第二栅极。
该方法进一步包括：穿过所述层间介电层和所述蚀刻停止层蚀刻接触开口到达所述半导体衬底。
根据本发明的又一方面，提供了一种结构，包括：栅极，位于半导体衬底上方；栅极间隔件，沿着所述栅极的侧壁，所述栅极间隔件的第一部分远离所述半导体衬底，所述栅极间隔件的第二部分紧邻所述半导体衬底，所述第一部分具有比所述第二部分更高的碳浓度；蚀刻停止层，位于所述栅极间隔件上方以及所述半导体衬底上方，所述蚀刻停止层的第三部分远离所述半导体衬底，所述蚀刻停止层的第四部分紧邻所述半导体衬底，所述第三部分具有比所述第四部分更高的碳浓度；以及层间介电层，位于所述蚀刻停止层上方。
在该结构中，碳在所述第一部分和第三部分中的浓度介于1×1014/cm3和1×1015/cm3之间。
在该结构中，所述第一部分和所述第三部分包括碳氮化硅，而所述第二部分和所述第四部分包括氮化硅。
在该结构中，所述第一部分具有比所述第二部分更高的密度，并且所述第三部分具有比所述第四部分更高的密度。
在该结构中，所述蚀刻停止层的表面、所述层间介电层的表面以及所述栅极的表面共面。
附图说明
为更完整的理解本实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图8是根据实施例的形成CMOS结构的方法。
具体实施方式
下面详细讨论本实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅仅示出了制造和使用所公开的主题的具体方式，而不用于限制不同实施例的范围。
结合具体上下文描述了实施例，即，形成CMOS结构的方法和CMOS结构。CMOS结构可以包括平面或者鳍式场效应晶体管。此外，本文中描述了后栅极工艺，并且其他实施例考虑先栅极工艺。在20nm技术节点或者更小的技术节点的背景下描述了所公开的方法和结构，并且其他实施例考虑不同的技术节点。本文中所公开的方法以实例顺序进行描述。其他实施例考虑以任何逻辑顺序所实施的方法。附图中相同的参考标号指的是相同的部件。
图1示出了根据实施例的处于加工期间的中间结构。结构包括具有由隔离区16隔离的n型器件区域12(“n区”)和p型器件区域14(“p区”)的衬底10。例如，衬底10为体硅衬底、绝缘体上半导体(SOI)衬底或者其他半导体衬底。n区12可以用于NMOS、n型finFET、核心NMOS或者n型finFET等，并且可以包括p型掺杂阱。p区14可以用于PMOS、p型finFET、核心PMOS或者p型finFET等，并且可以包括n型掺杂阱。隔离区16可以为浅槽沟槽隔离件(STI)、场氧化物等。
在衬底10的区域12和区域14上方形成相应的栅极介电层26和伪栅极28。为了形成这些部件，在衬底10上方沉积介电层。介电层可以为通过化学汽相沉积(CVD)、等离子体增强CVD(PECVD)等或者它们的组合形成的氧化硅、氧氮化硅等或者它们的组合。在介电层上方沉积伪层。在本实施例中的伪层为多晶硅，尽管可以使用其他材料，并且可以使用CVD、原子层沉积(ALD)等或者它们的组合来沉积该介电层。然后，例如，通过旋涂沉积可以在伪层上方沉积光刻胶，并且通过暴露于光下来图案化该光刻胶。然后，蚀刻可以去除伪层和介电层没有被光刻胶覆盖的部分，从而图案化伪栅极28和栅极介电层26。在示例性实施例中，伪栅极28的顶面是在与衬底的顶面正交的方向上距离衬底10的顶面的距离，并且该距离为大约450埃也可以使用用于形成栅极介电层26和伪栅极28的其他可接受的技术。
在形成栅极介电层26和伪栅极28之后，形成位于n区12中的n型轻掺杂延伸区20以及位于p区14中的p型轻掺杂延伸区24。可以在p区14上方图案化诸如光刻胶的第一掩模层，并且可以将n型掺杂剂(例如，磷、砷等或者它们的组合)注入n区12中。然后，去除第一掩模层。可以在n区12上方图案化诸如光刻胶的第二掩模层，并且可以将p型掺杂剂(例如，硼等或者它们的组合)注入p区14内。其他的适当技术可以用于形成轻掺杂延伸区20和24。
在伪栅极28和栅极介电层26的侧壁上形成间隔件衬里30和间隔件32。可以在衬底10和伪栅极28上方并且沿伪栅极28和栅极介电层26的侧壁共形沉积薄介电层。薄介电层可以为通过CVD等或者它们的组合形成的氮化硅、二氧化硅、氧氮化硅等或者它们的组合。间隔件介电层可以共形沉积在薄介电层上方。间隔件介电层可以为通过CVD等或者它们的组合形成的氮化硅、二氧化硅、氧氮化硅等或者它们的组合。然后，各向异性蚀刻可以沿着侧壁将介电层图案化为间隔件衬里30和间隔件32。其他的适当技术可以用于形成间隔件32和间隔件衬里30。
源极/漏极区18和22分别形成在衬底10的n区12和p区14中。在一个实施例中，沿着与伪栅极28相对的间隔件32和间隔件衬里30的边缘在衬底10中蚀刻沟槽。在n区12内的沟槽中外延生长第一半导体材料，并且在p区14内的沟槽中外延生长第二半导体材料。这些外延半导体材料可以生长为衬底10的顶面之上一定高度并且可以在外延半导体材料的相应顶面和衬底10的顶面之间具有小平面。用于n区12中的第一半导体材料的示例性材料包括磷化硅、碳化硅等或者它们的组合，并且通过诸如选择性外延生长(ESG)等形成该第一半导体材料。用于p区14中的第二半导体材料的示例性材料包括硅锗等或者它们的组合，并且通过诸如SEG等形成该第二半导体材料。n区12和p区14中的外延半导体材料在生长期间或者生长之后通过注入分别原位掺杂有n型掺杂剂和p型掺杂剂。在蚀刻、外延生长和/或掺杂期间可以使用各种掩模。在另一个实施例中，可以分别利用n型掺杂剂和p型掺杂剂通过注入掺杂n区12和p区14中的衬底10，以分别形成漏极/源极区18和22，而没有外延材料。其他合适的技术可以用于形成漏极/源极区18和22。
在衬底10、伪栅极28、间隔件32、间隔件衬里30以及源极/漏极区18和22上方形成蚀刻停止层(ESL)34。ESL34共形沉积在衬底10上的部件上方。在一个实施例中，ESL34为氮化硅，并且还可以为其他类似的材料或者它们的组合。可以通过CVD等或者它们的组合形成ESL。
层间介电层(ILD)36形成在ESL34上方。在一个实施例中，ILD36为氧化硅，并且还可以为其他类似的材料或者它们的组合。可以通过CVD、高密度等离子体(HDP)等或者它们的组合来形成ILD36。
在图2中，平坦化ILD36和ESL34以到达伪栅极28的顶面，从而形成平坦表面38。在一个实施例中，通过使用化学机械抛光(CMP)去除部分ILD36和ESL34将ILD36和ESL34平坦化为平坦表面38。在其他实施例中，可使用诸如包括蚀刻的其他平坦化技术。
平坦表面38暴露在碳等离子体中。碳等离子体的示例性参数包括以下参数：大约1mT和大约20mT之间的压力；大约100W和大约300W之间的功率；大约2MHz和大约13.6MHz之间的频率；大约30秒和大约300秒之间的曝光时间；以及大约20％和大约80％之间的脉冲DC占空比。等离子体中的碳与平坦表面38发生反应。碳可从平坦表面38扩散至平坦表面38之下的一定深度，例如，在ILD36、ESL34、间隔件32和/或间隔件衬里30中。随着扩散，碳的浓度从平坦表面38至所述深度会降低。在一个实施例中，平坦表面38处的碳浓度在大约1×10cm-3和大约1×17cm-3之间。
在图3A中，碳注入40至平坦表面38下面一定深度。例如，碳注入40至ILD36、ESL34、间隔件32和/或间隔件衬里30中。以与平坦表面38正交的角度进行注入40。碳可以注入至平坦表面38之下的大约和大约之间的深度。注入的深度可以在从伪栅极28(例如，平坦表面38)的顶面至衬底10的顶面的距离的三分之一至二分之一之间。注入的能量可以在大约2keV和大约10keV之间。碳在平坦表面之下的该深度处的浓度可以在大约1×1014/cm3和大约1×1015/cm3之间。随着注入，注入种类的浓度可以具有梯度作为深度的函数，例如，朝向浓度最大的深度，注入种类的浓度逐渐提高，然后，朝向更远的深度，注入种类的浓度逐步降低。
在等离子体和注入40之后，结构从平坦表面38至该深度可以具有基本一致的碳浓度，但是在其他实施例中，浓度随着该距离而变化。可以通过由于注入所导致的碳浓度随着与平坦表面38的距离增加而提高来补偿由于扩散所导致的碳浓度的降低。在其他实施例中，来自不同步骤的浓度没有抵消，而是结构的总浓度可以作为与平坦表面38的距离的函数进行变化。
在等离子体和注入40之后，对该结构退火以生成含碳区域42。诸如快速热退火的退火可以在大约700℃和大约1,300℃之间(例如，大约1,000℃)的温度下持续大约0.001秒和大约30分钟之间的时间。退火使碳与含碳区域42中的ILD36、ESL34、间隔件32以及间隔件衬里30的材料发生反应。在ILD36是氧化碳并且ESL34、间隔件32以及间隔件衬里30中的每一个都是氮化硅的实施例中，退火在含碳区域42中分别生成碳氧化硅和碳氮化硅。应当注意，ILD36、ESL34、间隔件32以及间隔件衬里30位于含碳区域42之下的部分可以具有比ILD36、ESL34、间隔件32以及间隔件衬里30位于碳区域42中的部分更低的碳浓度(例如，基本上可忽略)。因此，在退火之后，这些下面的部分可以分别保留氧化硅和氮化硅。
图3B和3C是注入碳的另一个实例。在图3B中，碳以第一倾斜角注入44到平坦表面38之下的一定深度，以形成第一碳注入区46。例如，碳被注入44到ILD36、ESL34、间隔件32和/或间隔件衬里30中。在该实例中，第一倾斜角在与伪栅极28的侧壁垂直并且与平坦表面38垂直的平面内。第一倾斜角在该平面内并且是以顺时针方式测量的与垂直于平坦表面38的轴的夹角在大约0°和大约90°之间(例如，45°)的角度。倾斜角的选择可以取决于伪栅极28之间的间距和伪栅极28的定向。碳可以在平坦表面38之下注入大约和大约之间的深度。注入可以到达从伪栅极28的顶面(例如，平坦表面38)至衬底10的顶面的距离的大约三分之一至二分之一的深度处。注入的能量可以在大约2keV和大约10keV之间。
在图3C中，碳以第二倾斜角注入48到位于平坦表面38之下的一定深度。例如，碳注入48到ILD36、ESL34、间隔件32和/或间隔件衬里30中。在本实例中，第二倾斜角与第一倾斜角互补，并且在与伪栅极28的侧壁垂直并与平坦表面38垂直的平面中。第二倾斜角在该平面中并且是以顺时针方式所测量的与垂直于平坦表面38的轴的夹角在大约0°和大约360°之间(例如，315°)的角度(例如，以逆时针方式测量的与轴的夹角为45°)。碳注入到平坦表面38之下的大约和大约之间的深度处。注入可以到达从伪栅极28的顶面(例如，平坦表面38)至衬底10的顶面的距离的大约三分之一至二分之一的深度处。注入的能量可以在大约2keV和大约10keV之间。碳在平坦表面之下的该处深度的浓度可以在大约1×1014/cm-3和大约1×15/cm-3之间。随着注入，注入的种类的浓度可以具有梯度作为深度的函数。
在等离子体和注入44和48之后，结构从平坦表面38至该深度可以具有基本均匀的碳浓度，但是在其他实施例中，浓度随着该距离而变化。可以通过由于注入所导致的碳浓度随着与平坦表面38的距离增加而提高来补偿由于扩散所导致的碳浓度降低。在其他实施例中，不同步骤的浓度没有抵消，并且结构中的总浓度可以作为与平坦表面38的距离的函数进行变化。
在等离子体和注入44和48之后，对结构退火，以生成含碳区域42。退火(例如，快速热退火)可以在大约700℃和大约1300℃之间(例如，大约1000℃)的温度下持续大约0.1秒和大约30分钟之间的时间。退火使碳与含碳区域42中的ILD36、ESL34、间隔件32和/或间隔件衬里30的材料发生反应。在ILD36是氧化碳而ESL34、间隔件32以及间隔件衬里30中的每一个都是氮化硅的实施例中，退火在含碳区域42中分别生成碳氧化硅和碳氮化硅。应当注意，ILD36、ESL34、间隔件32以及间隔件衬里30在含碳区域42之下的部分可以具有比ILD36、ESL34、间隔件32以及间隔件衬里30在含碳区域42中的部分更低的碳浓度(例如，基本可忽略)。因此，在退火之后，这些部件的下部可以分别保留氧化硅和氮化硅。
例如，通过等离子体暴露和/或通过注入将碳引入ESL34、间隔件32以及间隔件衬里30的部分以及后续退火可以提高每个部件的密度。因此，ILD36、ESL34、间隔件32以及间隔件衬里30位于含碳区域42之下的部分可以具有比ILD36、ESL34、间隔件32以及间隔件衬里30位于含碳区域42中的部分更低的碳浓度。
在图4中，去除伪栅极28。可以通过对伪栅极28的材料具有选择性的蚀刻去除伪栅极28。应当注意，如果碳也注入到伪栅极28内使得部分伪栅极28包含碳而其他部分不包含碳，则可以使用不同的蚀刻剂。例如，如果伪栅极28包括多晶硅，伪栅极28在含碳区域42中的顶部可以为碳化硅，而底部为硅。使用诸如CF4的第一次蚀刻可以去除顶部，并且使用诸如NF3、SF6、C12、HBr等或者它们组合的第二次蚀刻可以去除底部。
在图5中，栅极结构52形成在伪栅极28被去除的区域中。各种子层52a至52g可以包括在栅极结构52中。一些子层可以均为高k介电层，例如，HfSiO4、HfSiON、HfSiN、ZrSiO4、ZrSiON、ZrSiN、ZrO2、HfO2、La2O3等。高k介电材料层上方的其他子层可以为金属层，例如，钨、氮化钛等。子层52a至52g顺序共形沉积在ILD36上方和伪栅极28被去除(例如，使用CVD，ALD、热沉积等)的区域中。平坦化(例如，通过CMP)去除这些层在平坦化表面38上方的多余材料，以形成栅极结构52。在实施例中，子层52a至52g中的一些没有形成在栅极结构52中。例如，在n区12上方的栅极结构52中没有子层52e。例如，这可以通过在掩蔽p区14上方的栅极结构52的同时使用蚀刻去除子层52e实现。通过具有不同的子层，可以实现器件的不同功函。
在图6中，CESL54形成在平坦表面38上方。CESL54可以为通过CVD、ALD、热沉积等或者它们的组合所形成的氮化硅、氮氧化硅、碳化硅、碳氧化硅等或者它们的组合。在图7中，蚀刻接触开口56以穿过CESL54、ILD36和CESL34到达源极区18和漏极区22。可以在CESL54上方图案化光刻胶并且一个或者多个蚀刻步骤可以形成接触开口56。在图8中，在接触开口56中形成到达相应的源极区18和漏极区22的接触件58。诸如金属的导电材料可以沉积在接触开口56中并且例如，通过CMP可以去除多余的导电材料，以形成接触件58。在其他实施例中，另一ILD可以形成在CESL54上方，并且可以使用相应的蚀刻步骤蚀刻穿过ILD、CESL54、ILD36，和CESL34的接触开口。接触件可以形成在接触开口中。
实施例可以实现更稳固的间隔件和蚀刻停止层，以自对准接触件。碳等离子体曝光和注入以及后续退火可以使间隔件和蚀刻停止层更密集，因此间隔件和蚀刻停止层可以比没有碳的情况具有更低的蚀刻率。间隔件和蚀刻停止层可以相对于蚀刻剂去除伪栅极和蚀刻剂蚀刻ILD以形成接触开口更强固。由于更强固的间隔件和蚀刻停止层，实施例可以通过防止接触件与金属栅极泄漏来实现更高产量。
实施例是一种方法，包括通过衬底的表面扩散碳，通过衬底的表面注入碳；以及在通过衬底的表面扩散碳和注入碳之后，对衬底进行退火。衬底包括第一栅极、栅极间隔件、蚀刻停止层以及层间介电层。第一栅极位于半导体衬底上方。栅极间隔件沿第一栅极的侧壁。蚀刻停止层位于栅极间隔件的表面上以及半导体衬底的表面上方。层间介电层位于蚀刻停止层上方。衬底的表面包括层间介电层的表面。
另一个实施例是一种方法，包括在从衬底的表面至在衬底中位于衬底的表面之下的第一深度的方向上形成第一梯度的碳，在衬底的表面至在衬底中位于第一深度之下的第二深度的方向上形成第二梯度的碳；在形成第一梯度的碳和形成第二梯度的碳之后，对衬底进行退火。形成第一梯度的碳包括将衬底的表面暴露于含碳等离子体中。形成所述第二梯度的碳包括通过衬底的表面注入碳。衬底包括：栅极间隔件、蚀刻停止层以及层间介电层。栅极间隔件沿着第一栅极的侧壁，并且栅极间隔件位于半导体衬底上方。蚀刻停止层沿着栅极间隔件的表面并且位于半导体衬底上方。层间介电层位于蚀刻停止层上方。
另一个实施例是一种结构，包括：位于半导体衬底上方的栅极；沿所述栅极的侧壁的栅极间隔件；位于栅极间隔件上方以及半导体衬底上方的蚀刻停止层；以及位于蚀刻停止层上方的层间介电层。栅极间隔件的第一部分远离半导体衬底，以及栅极间隔件的第二部分紧邻半导体衬底，第一部分比第二部分具有更高的碳浓度。蚀刻停止层的第三部分远离半导体衬底，并且蚀刻停止层的第四部分紧接所述半导体衬底。第三部分比第四部分具有更高的碳浓度。
尽管已经详细地描述了本实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明的精神和范围的情况下，做各种不同的改变、替换和更改。而且，本申请的范围并不旨在限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应该理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (19)

1.一种用于制造半导体结构的方法，包括：
透过衬底的表面扩散碳，所述衬底包括：
第一栅极，位于半导体衬底上方，
栅极间隔件，沿着所述第一栅极的侧壁，
蚀刻停止层，位于所述栅极间隔件的表面上以及所述半导体衬底的表面上方，以及
层间介电层，位于所述蚀刻停止层上方；
所述衬底的所述表面包括所述层间介电层的表面、所述栅极间隔件的表面以及所述蚀刻停止层的表面；以及
透过所述衬底的所述表面注入碳；以及
在透过所述衬底的所述表面扩散碳和注入碳之后，对所述衬底进行退火；
其中，所述栅极间隔件和所述蚀刻停止层注入有碳，以与所述衬底的所述表面不正交的第一角度的第一注入以及以与所述第一角度互补的第二角度的第二注入实施注入碳。
2.根据权利要求1所述的方法，其中，透过所述衬底的所述表面扩散碳包括：将所述衬底的所述表面暴露于含碳等离子体。
3.根据权利要求1所述的方法，其中，透过所述衬底的所述表面注入碳包括：沿着所述栅极间隔件的表面，将碳注入到所述栅极间隔件的一部分和所述蚀刻停止层的一部分中。
4.根据权利要求1所述的方法，其中，以与所述衬底的所述表面正交的角度实施注入碳。
5.根据权利要求1所述的方法，进一步包括：在对所述衬底进行退火之后，去除所述第一栅极，并且在所述第一栅极被去除的区域中形成第二栅极。
6.根据权利要求1所述的方法，进一步包括：穿过所述层间介电层和所述蚀刻停止层蚀刻接触开口到达所述半导体衬底的所述表面。
7.根据权利要求1所述的方法，其中，在扩散碳和注入碳之前，所述栅极间隔件和所述蚀刻停止层都包括氮化硅。
8.一种用于制造半导体结构的方法，包括：
在从衬底的表面到所述衬底中位于所述衬底的所述表面之下的第一深度的方向上形成第一梯度的碳，形成所述第一梯度的碳包括将所述衬底的所述表面暴露于含碳等离子体，所述衬底包括：
栅极间隔件，沿着第一栅极的侧壁，所述栅极间隔件位于半导体衬底上方；
蚀刻停止层，沿着所述栅极间隔件的侧壁并位于所述半导体衬底上方；和
层间介电层，位于所述蚀刻停止层上方；
所述衬底的所述表面包括所述层间介电层的表面、所述栅极间隔件的表面以及所述蚀刻停止层的表面；
在从所述衬底的所述表面到所述衬底中位于所述第一深度之下的第二深度的方向上形成第二梯度的碳，形成所述第二梯度的碳包括透过所述衬底的所述表面注入碳；以及
在形成所述第一梯度的碳和形成所述第二梯度的碳之后，对所述衬底进行退火；
其中，所述栅极间隔件和所述蚀刻停止层注入有碳。
9.根据权利要求8所述的方法，其中，所述第一梯度的碳包括在从所述衬底的所述表面到所述第一深度的方向上降低的碳浓度，并且所述第二梯度的碳包括从所述衬底的所述表面到所述第二深度的方向上增加且随后降低的碳浓度。
10.根据权利要求8所述的方法，其中，将所述衬底的所述表面暴露于所述含碳等离子体通过扩散碳而形成所述第一梯度的碳。
11.根据权利要求8所述的方法，其中，以与所述衬底的所述表面正交的角度实施透过所述衬底的所述表面注入碳。
12.根据权利要求8所述的方法，其中，透过所述衬底的所述表面注入碳包括第一注入角的第一注入和与所述第一注入角互补的第二注入角的第二注入。
13.根据权利要求8所述的方法，进一步包括：在对所述衬底进行退火之后，去除所述第一栅极，并且在所述第一栅极被去除的区域中形成第二栅极。
14.根据权利要求8所述的方法，进一步包括：穿过所述层间介电层和所述蚀刻停止层蚀刻接触开口到达所述半导体衬底。
15.一种半导体结构，包括：
栅极，位于半导体衬底上方；
栅极间隔件，沿着所述栅极的侧壁，所述栅极间隔件的第一部分远离所述半导体衬底，所述栅极间隔件的第二部分紧邻所述半导体衬底，所述第一部分具有比所述第二部分更高的碳浓度；
蚀刻停止层，位于所述栅极间隔件上方以及所述半导体衬底上方，所述蚀刻停止层的第三部分远离所述半导体衬底，所述蚀刻停止层的第四部分紧邻所述半导体衬底，所述第三部分具有比所述第四部分更高的碳浓度；以及
层间介电层，位于所述蚀刻停止层上方。
16.根据权利要求15所述的半导体结构，其中，碳在所述第一部分和第三部分中的浓度介于1×1014/cm3和1×1015/cm3之间。
17.根据权利要求15所述的半导体结构，其中，所述第一部分和所述第三部分包括碳氮化硅，而所述第二部分和所述第四部分包括氮化硅。
18.根据权利要求15所述的半导体结构，其中，所述第一部分具有比所述第二部分更高的密度，并且所述第三部分具有比所述第四部分更高的密度。
19.根据权利要求15所述的半导体结构，其中，所述蚀刻停止层的表面、所述层间介电层的表面以及所述栅极的表面共面。
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