CN103489850B - 半导体封装中的cte适配 - Google Patents

半导体封装中的cte适配 Download PDF

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Publication number
CN103489850B
CN103489850B CN201310225207.4A CN201310225207A CN103489850B CN 103489850 B CN103489850 B CN 103489850B CN 201310225207 A CN201310225207 A CN 201310225207A CN 103489850 B CN103489850 B CN 103489850B
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Prior art keywords
dielectric layer
cte
value
layer
redistribution layer
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CN201310225207.4A
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CN103489850A (zh
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T.迈耶
G.奥夫纳
S.施特克尔
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Intel Deutschland GmbH
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Intel Mobile Communications GmbH
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Abstract

本发明涉及半导体封装中的CTE适配。提出了一种诸如晶片级封装（WLP）器件之类的器件，其中，电介质层被布置在半导体器件的表面和重分布层（RDL）的表面之间。所述电介质层可以具有延伸穿过电介质层的至少一个互连。所述电介质层可以具有垂直于半导体器件的表面的方向上的小于阈值的热膨胀系数（CTE）值，以及大于另一个阈值的杨氏模量。所述电介质层在平行于半导体器件的表面的方向上在面对RDL的电介质层的表面处可以具有大于另一个阈值的CTE值。

Description

半导体封装中的 CTE 适配
背景技术
对于晶片级封装（WLP）半导体器件，在温度循环和冲击测试（drop testing）期间实现板级可靠性是有挑战性的。WLP技术提供了诸如低成本、小尺寸、和良好的电和热性能之类的许多潜在优势。然而，在发生封装的板装失效（board-mounted failure）之前温度循环的数量通常低于期望。这种失效的根源可能通常是封装的半导体芯片的热膨胀系数（CTE）和封装安装于其上的印刷电路板（PCB）的CTE之间的相对地高度不匹配。典型地，尤其对于用于移动计算和通信行业中的越来越大的封装尺寸，这种不匹配在温度循环期间在位于封装和PCB之间的焊球上引起应力，并可能导致焊点失效以及早期电故障。
发明内容
本文所述的一些特征通常涉及可以提高晶片级封装（WLP）和类似的封装技术的可靠性的结构和过程。在一些方面，通过适配（例如，确定）包括在WLP器件中的电介质层的材料和厚度，WLP器件的热膨胀系数（CTE）可以被提高到接近WLP器件所要安装于其上的电路板的CTE的值。例如，可以适配电介质层的材料和厚度以使得电介质层具有高杨氏模量。此外，所述电介质层在特定方向上的CTE可以在值上近似于在该方向上延伸穿过该电介质层的互连（例如通孔）的CTE。
根据一些方面，可以制造或以其他方式提供包括半导体器件、电介质层、和导电重分布层（RDL）（例如，扇入重分布层或扇出重分布层）的器件。所述半导体器件可以具有一个或多个横向分布在半导体器件的表面上的电接触（electrical contact）。所述电介质层可以被布置在半导体器件的表面和RDL的表面之间。所述电介质层可以具有一个或多个诸如通孔之类的、在深度方向上至少部分延伸穿过电介质层并且将所述半导体器件的一个或多个电接触电耦合于RDL的导电互连。在一些实例中，尽管不需要这么小的厚度，但是所述电介质层的厚度可以小于100微米（例如，在5和15微米之间，在50和70微米之间）。例如，电介质层可以具有等于或大于100微米的厚度。
在一些布置中，所述器件可以进一步包括一个或多个电耦合于重分布层的焊球。在这种布置中，所述重分布层可以被布置在电介质层和一个或多个焊球之间。在一些布置中，所述器件可以进一步耦合于或可以甚至包括诸如印刷电路板（PCB）之类的电路板。在二者任一情况下，PCB可以具有电或机械耦合于一个或多个焊球的电接触。在这种布置中，所述一个或多个焊球可以被布置在重分布层和电路板之间。
所述电介质层可以具有在垂直于半导体器件的表面的方向上的热膨胀系数（CTE）值和杨氏模量。在一些例子中，所述电介质层的CTE值可以小于阈值（例如，32ppm每摄氏度）。在一些例子中，所述电介质层的CTE值和所述一个或多个延伸穿过电介质层的互连的CTE值之间的差异可以小于另一个阈值（例如，15ppm每摄氏度）。在一些例子中，所述电介质层的杨氏模量还可以大于另一个阈值（例如，25GPa）。
所述电介质层可以具有在平行于半导体器件的表面的方向上的CTE值，由于可以被包含于封装中的其他材料的CTE的影响，所述CTE值随着电介质层的厚度增加而增加。例如，所述电介质层可以在面对半导体器件的表面的电介质层表面处具有小于例如3ppm每摄氏度的第一CTE值。相同的电介质层可以在面对重分布层的表面的电介质层表面处具有大于例如6ppm每摄氏度的第二CTE值。因而，在3ppm和6ppm之间的CTE的梯度（例如）可以存在于两个表面之间的电介质层。
本发明内容不意在确定本公开的关键或必需的特征，但是反而仅仅归纳了某些特征及其变型。在下文的部分也将讨论其他细节和特征。
附图说明
通过参考鉴于附图的下述描述，可获得对本公开和本文所述的各种方面的潜在优势的更加完全理解，在附图中相同的附图标记表示相同的特征，并且其中：
图1图示了示例晶片级封装系统的剖面图；
图2图示了示例晶片级封装系统的各种元件的等距视图；
图3图示了用于适配电介质层的材料和厚度的示例技术；以及
图4图示了用于适配电介质层的材料和厚度的示例过程流。
值得注意的是，一个或多个附图可以不必按尺度绘制。
具体实施方式
图1图示了根据本文所述的一个或多个方面的示例晶片级封装（WLP）系统的剖面图。示例WLP系统可以包括，例如，通过一个或多个焊球106电耦合于电路板107的WLP器件100。在一些方面中，示例WLP系统可以包括多于或少于图1所示的那些的元件、层和/或特征。在一些方面中，示例WLP系统的元件、层和/或特征的物理布置可以不同于图1。此外，WLP器件100可以包括更多或更少的元件。例如，WLP器件100可以包括焊球106的阵列。
在图1中示出坐标系150来表示可以与WLP器件100和系统的各个部分相关联的相对位置、方向和向量，例如表面、表面之间的界面、邻近于表面的区域等。坐标系150被示出只是为了解释的目的（且不是系统的实际物理元素），并且尽管本文所讨论的示例参考笛卡尔坐标系，坐标系150还可以是笛卡尔坐标系、极坐标系或任何其他合适的坐标系。在本示例中，坐标系150包括向上/向下延伸的z轴、垂直于z轴向左/向右延伸的y轴、和垂直于y轴和z轴“向页内”/“向页外”延伸的x轴。在一些例子中，参考WLP器件100所描述的表面可以被描述为平行于坐标系150所示的x-y平面154。然而，所述表面、WLP器件100、和系统可以是所期望的任何空间定向。
WLP器件100可以包括半导体器件101、电介质层102、重分布层（RDL）103、一个或多个导电互连104、焊接停止层105、一个或多个电接触111、以及一个或多个电接触112。半导体器件101可以包括一个或多个诸如电学和/或光学元件之类的有源和/或无源元件。例如，半导体器件101可以是包括硅基材料（例如，硅、碳化硅、硅锗等）、III-V族化合物半导体材料（例如，砷化镓、磷化镓、磷化铟、锑化铟等）、II-VI族化合物半导体材料（例如，氧化锌、碲化锌、硒化锌等）、和/或其他半导体材料及其组合的芯片或裸片（die）。在一个示例中，半导体器件101可以包括诸如一个或多个电阻器、晶体管、电容器、二极管、和/或存储单元之类的互补金属氧化物半导体（CMOS）元件，其中一个或多个导线互连以上元件。在另一个示例中，半导体器件101可以包括诸如换能器、传感器、和/或致动器之类的微机电系统（MEMS）元件，其中一个或多个导线互连以上元件。
如图1所示，半导体器件101可以被包含于扇入晶片级球栅阵列（WLB）中。在这种配置中，一个或多个电接触111可以由导电材料制成并被配置为允许半导体器件101与WLP器件100的其他部分进行电通信。电接触111可以是，例如，诸如铝接触垫之类的金属接触。电接触111可以被布置在半导体器件101的面朝下（例如平行于z轴）的表面121上（例如平行于x-y平面154的表面）或以其他方式布置在表面121处。在一些布置中，半导体器件101可以被包含于扇出WLB中。在这种配置中，WLB表面（例如界面130处）可以包括由硅制成的区域和由塑封材料（mold compound）制成被布置邻接于硅区域的区域。因此，电介质层底部（例如，在表面122处）的CTE可以基于介质材料是否被布置邻接于硅或塑封材料而变化。结果，电介质层顶部（例如，在表面131处）的CTE可以根据电介质层底部的CTE而变化。在一些布置中，半导体器件101可以被定向在包括例如焊接凸点和底部填充的倒装芯片配置中。
电介质层102可以被布置在半导体器件101的表面121和重分布层（RDL）103的表面132之间。电介质层102的表面122可以被布置面对半导体器件101的表面121，在电介质层102和半导体器件101之间形成界面120。电介质层102的表面131可以被布置面对RDL 103的表面132，在电介质层102和RDL 103之间形成界面130。表面122和131之间（例如，在平行于z轴的方向）的距离可以对应于电介质层102的厚度T。表面121和122可以彼此直接接触或在表面121和122之间可以存在一个或多个中间层。同样地，表面131和132可以彼此直接接触或在表面131和132之间可以存在一个或多个中间层。
电介质层102可以包括，例如，环氧树脂和/或另一个电介质材料。在一个示例中，电介质层102可以由诸如A型HL832NX之类的非卤化低热膨胀系数（CTE）双马来酰亚胺三嗪（BT）树脂而制成。在另一个示例中，电介质层102可以由包括树脂的环氧树脂而制成，例如有或没有填充物的环氧酚醛或氰酸酯环氧树脂。电介质层102可以通过例如旋涂、显影（developing）、蚀刻、和/或印刷过程和/或层压、淋涂（curtain coating）、喷涂和激光成型来形成。在下文中并参考图3和图4将会进一步详细讨论用于确定电介质层102的材料和厚度的技术。
电介质层102可以包括一个或多个诸如互连104之类的延伸穿过电介质层102并且将一个或多个电接触111电耦合到RDL 103的导电互连。互连104可以是，例如，包括诸如铜、金属堆叠、金属填充聚合物（例如，银填充聚合物）、各向同性导电胶（ICA）、或其他导电材料之类的导电材料的通孔。RDL 103可以是包括诸如铜、金属填充聚合物（例如，银填充聚合物）、各向同性导电胶（ICA）、或其他导电材料之类的导电材料的扇入或扇出重分布层。电介质层102可以被成型（例如，通过光刻或通过激光），以使得暴露出半导体器件101的一个或多个电接触111。随后，一个或多个互连104、RDL 103、或二者可以通过例如使用溅射、蒸发、防镀（plating resist）、电镀（electroplating）、剥离、蚀刻、无电（electro-less）过程、滴涂（dispensing）和/或印刷过程来形成。在一个示例中，一个或多个互连104可以是一个或多个延伸穿过电介质层102并且将半导体器件101电耦合到RDL 103的铜圆柱体或柱（post），其可以包括，例如图案化的铜互连。
RDL 103可以被布置在电介质层102的表面131和一个或多个焊球106之间。一个或多个焊球106可以由锡、铅、铟、和/或任何其他可焊接材料或合金而制成。RDL 103可以通过可以各自与焊球106之一机械和电接触的一个或多个电接触112而被电耦合到一个或多个焊球106。一个或多个电接触112可以具有与参考电接触111所讨论的那些特征相类似的特征。
焊接停止层105可以被布置邻接于RDL103和焊球106。焊接停止层105可以由非焊接材料（例如诸如WPR 5100、LTC 7320或层压焊接停止树脂之类的阻焊）制成并使用例如光刻或激光来成型，以便暴露一个或多个电接触112。
一个或多个焊球106可以被布置在RDL 103和电路板107之间。电路板107可以是例如印刷电路板（PCB）。焊球106可以通过一个或多个电接触113被电或机械耦合到电路板107。一个或多个电接触113可以具有与参考电接触111所讨论的那些特征相类似或不同的特征。在某些实现方式中，一个或多个焊球106可以被布置为焊球的球栅阵列（BGA），所述焊球被布置在RDL 103下面并电耦合（例如，焊接）到电路板107。因而，示例WLP器件100可以被放置在电路板107上，作为较大的电路和/或设备的部分，例如笔记本电脑、平板电脑、台式机或服务器计算机；移动电话；全球定位系统（GPS）设备；电子医疗设备；机动车或其元件；飞行器或其元件；或任何其它设备、系统或包括电子设备的其他产品。
在一些布置中，示例WLP系统的各种层和元件的每一个可以具有各自的热膨胀系数（CTE）和各自的杨氏模量（例如，拉伸模量）、和/或其范围。对于各向异性材料，CTE可以包括平面内CTE元件和不同于平面内CTE元件的平面外（例如法向（cross-plane）、层面间（through-plane））CTE元件。参考图1的示例坐标系，平面内CTE元件可以对应于在平行于x-y平面154并垂直于z轴的方向上（例如，在平行于半导体器件101的表面121的方向上）的CTE值。平面外CTE可以对应于在平行于z轴并垂直于x-y平面154的方向上（例如，在垂直于半导体器件101的表面121的方向上）的CTE。对于各向同性材料，平面内和平面外CTE元件可以在值上相等或近似。对于各向同性和各向异性材料层二者，CTE在层内的不同位置处可以变化。在层内给定位置的实际CTE值可以取决于诸如机械耦合到和/或埋入层内的其他材料之类的与层不相关的因素。因而，给定层在层内的第一位置可以具有第一平面内或平面外CTE，且在层内的不同的第二位置可以具有第二不同的平面内或平面外CTE。如本文将要讨论的，这种在电介质层102内CTE的分级可以被有利地使用。
如图1所示，半导体器件101可以在表面121或接近表面121处具有平面内CTE值CTE-XY-S。电介质层102可以在表面122或接近表面122处（例如，面对表面121）具有平面内CTE值CTE-XY-D-1。电介质层102可以在表面131或接近表面131处（例如，面对RDL 103的表面132）具有平面内CTE值CTE-XY-D-2。电介质层102可以具有平面外CTE值CTE-Z-D。一个或多个互连（例如，互连104）可以具有平面外CTE值CTE-Z-I。电路板107可以在接触焊球106的表面处具有平面内CTE值CTE-XY-B。图1的上述CTE值是在如图1所示的完备系的环境中所经历的那些CTE值。值得注意的是，对于包括电介质层102的至少一些层，当那些层是在隔离状态下时（例如，不附着于任何其它层），CTE值可以不同。这种区别至少部分归因于可以在层之间的界面处受到的各种力和/或机械阻力。
为了提供潜在地更加可靠的器件，电介质层102的材料可以被选择为具有类似于焊球106被焊接于其上的电路板107的CTE值（例如，CTE-XY-B）的平面内CTE值（例如，CTE-XY-D-2）。电介质层102的材料也可以被选择为具有类似于一个或多个互连（例如，互连104）的CTE值（例如，CTE-Z-I）的平面外CTE值（例如，CTE-Z-D）。此外，电介质层102的材料可以被选择为具有高到足以使得电介质层102的厚度T相对小（例如小于100微米）的杨氏模量（例如，为了减小由增加电介质层102的厚度T所引起的弯曲的增大的可能性）。在这样做时，在热事件期间（例如，诸如温度增加或降低之类的环境温度变化）一个或多个焊球106所可能受到的应力可以被减小，并且继而，由这些应力所引起的半导体器件101和电路板107之间的相对运动也可以被减小。因为可能需要被焊球106所吸收的平面内CTE的差异（在RDL的可能接近CTE-XY-D-2的平面内CTE和在电路板107的平面内CTE-XY-B之间的差异）可以被降低，所以所述应力可以减小。此外，在一些例子中，由于电介质层102和互连104的平面外CTE之间的不匹配（CTE-Z-D和CTE-Z-I之间的差异）的任何减小，在电介质层102和在RDL 103的表面132或接近表面132处的互连104之间的界面处分层和/或裂化的可能性可以减小。参考图3以示例的方式进一步详细讨论了用于确定电介质层102的材料和厚度的技术（例如，使用WLP器件100的区域140的透视图作为参考）。
图2图示了根据一个或多个方面的半导体器件101、电介质层102和焊球106的等距分解图。示例WLP器件100的其他层和/或元件没有在图2中示出以避免视图过于复杂。如图2所示，坐标系150被旋转以使得x轴向下延伸、y轴垂直于x轴向右延伸、且z轴垂直于x轴和y轴延伸。半导体器件101的表面121和电介质层102的表面122和131可以均平行于x-y平面154。
图3图示了用于适配电介质层102的材料和厚度的示例技术。为了说明以及非限制目的，WLP器件100的区域140（见图1）被用作参考。
电介质层102可以由一种材料制成，对于该材料，电介质层102的平面内CTE值（如图1，当附着到周围层时）根据从表面122在z轴方向向下延伸的深度D而增长，以示例的方式如图3中CTE-XY-D曲线301所示。在一些例子中，曲线301的诸如随深度D增长的平面内CTE值CTE-XY-D的线性或非线性增长率之类的属性可以取决于电介质层102的体（bulk）（或平面外）CTE值和杨氏模量。例如，半导体器件101可以在表面121或接近表面121处具有平面内CTE值CTE-XY-S 304。例如，对于硅基半导体器件，平面内CTE值CTE-XY-S 304可以近似3.0ppm每摄氏度。由于硅的高杨氏模量（例如，高于100GPa），因此在表面122或接近表面122处的平面内CTE值CTE-XY-D-1 302可以在值上近似于平面内CTE值CTE-XY-S 304。例如，平面内CTE值CTE-XY-D-1 302也可以近似3.0ppm每摄氏度。在一些布置中，平面内CTE值CTE-XY-D-1 302可以是小于预定阈值320（例如，3ppm每摄氏度）的值。
在一些布置中，可以确定电介质层102的材料和/或厚度T以使得平面内CTE值CTE-XY-D-2 303可以具有半导体器件101的平面内CTE值CTE-XY-S 304和电路板107的平面内CTE值CTE-XY-B（例如，对于PCB近似16ppm每摄氏度）之间的值。例如，可以确定电介质层102的材料和/或厚度以使得平面内CTE值CTE-XY-D-2 303可以具有大于预定阈值330（例如，6ppm每摄氏度）的值。结果，电介质层102可以吸收由CTE值CTE-XY-S和CTE-XY-B的不匹配所引起的部分应力，因此减小由一个或多个焊球106所吸收的应力的量。然而，如果平面内CTE值CTE-XY-D-2 303太高或以其他方式接近电路板107的平面内CTE值CTE-XY-B，那么更可能发生分层（例如，在半导体器件101和电介质层102之间）或裂化（例如，在电介质层102中）。因此，可以确定电介质层102的材料和/或厚度T以使得平面内CTE值CTE-XY-D-2 303可以具有诸如近似7到10ppm每摄氏度的值之类的中间值。再次重申，上述CTE值仅仅是非限制性示例。
电介质层102可以由具有随着在电介质层102中的深度D增加而保持相对恒定的（例如，在基值（base value）或体值（bulk value）的特定范围内）平面外CTE值CTE-Z-D 312的材料而制成，以示例的方式如CTE-Z-D曲线311所示。在一些例子中，可以确定电介质层102的材料以使得平面外CTE值CTE-Z-D 312可以具有小于预定阈值340（例如，32ppm每摄氏度）或在值的特定预定范围（例如，在近似20和25ppm每摄氏度之间）的值。在一些例子中，可以确定电介质层102的材料以使得平面外CTE值CTE-Z-D 312可以在互连104的平面外CTE值CTE-Z-D 313（例如，对于铜互连，近似10ppm每摄氏度）的预定范围350内（例如，±15ppm每摄氏度）。例如，可以确定电介质层102的材料以使得CTE-Z-D 312和CTE-Z-D 313之间的差异小于预定阈值（例如，15ppm每摄氏度）。在一个示例中，可以确定电介质层102的材料以使得平面外CTE值CTE-Z-D 312可以具有近似7到10ppm每摄氏度的值。在另一个示例中，可以确定电介质层102的材料以使得平面外CTE值CTE-Z-D 312可以具有近似15到21ppm每摄氏度的值，其可以允许减少在电介质层102的厚度范围中（例如，在近似50和70微米之间）裂化的可能性。
电介质层102可以由具有高到足以支持期望CTE值CTE-XY-D-2 303和CTE-Z-D 312的杨氏模量的材料而制成。例如，电介质层102的材料可以被选择为具有大于预定阈值（例如，25GPa）或在值的特定预定范围内（例如，在近似24和34GPa之间）的杨氏模量，其可以允许电介质层102的厚度T是期望的小的厚度，例如小于100微米，以及，在一些例子中，在50和70微米之间。再次重申，本文所提及的这些和所有其他值都仅仅是非限制性示例。
在图示的示例中，电介质层102可以由诸如A型HL832NX之类的非卤化低CTE BT树脂而制成。例如，具有30微米的厚度T的A型HL832NX电介质层102可以具有10.06ppm每摄氏度的CTE-XY-D-2 303、30ppm每摄氏度的CTE-Z-D 312和28GPa的杨氏模量。在另一个示例中，具有60微米的厚度T的A型HL832NX电介质层102可以具有10.22ppm每摄氏度的CTE-XY-D-2 303。在另一个示例中，具有100微米的厚度T的A型HL832NX电介质层102可以具有10.47ppm每摄氏度的CTE-XY-D-2 303。在另一个示例中，具有150微米的厚度T的A型HL832NX电介质层102可以具有10.80 ppm每摄氏度的CTE-XY-D-2 303。
图4图示了用于确定电介质层（例如，电介质层102）的材料和/或厚度以及建造包括已确定的材料和/或厚度的已确定的电介质层的器件（例如，WLP器件100）的示例过程流。该示例过程流的一些方面可以包括参考图1-3所述的各方面。另外，虽然关于图4所讨论的步骤将参考图1的系统，但是这只是示例；这些或类似步骤还可以在该系统的变型上执行。
在步骤401处，用于电介质层（例如电介质层102）的材料至少可以基于将被电耦合到电介质层的互连的期望或另外已知的CTE值（例如，互连104的CTE值CTE-Z-I）来确定。例如，可以确定用于电介质层的材料以使得电介质层的平面外CTE值（例如，CTE-Z-D）小于阈值（例如，32ppm每摄氏度，阈值340）。在另一个示例中，可以确定用于电介质层的材料以使得电介质层的平面外CTE值和电介质层中的一个或多个互连（例如互连104）的CTE值之间的差异小于预定阈值（例如，15ppm每摄氏度，或使得CTE-Z-D在预定范围350内）。在一些实施例中，可以确定用于电介质层的材料以使得电介质层的杨氏模量大于阈值（例如，25GPa）。
在步骤402处，可以确定电介质层的厚度T以便达到特定的预定的平面内CTE值，以便在期望的平面内CTE值的预定范围内，以便大于（或大于等于）预定的平面内CTE值，或以便小于（或小于等于）预定的平面内CTE值。例如，可以确定电介质层的厚度T以使得在面对重分布层（例如，RDL 103）的表面的电介质层的表面（例如，表面131）处，电介质层的平面内CTE值（例如，CTE-XY-D-2）大于预定阈值（例如，6ppm每摄氏度，阈值330）。在一些示例中，在面对半导体器件（例如，半导体器件101）的表面处（例如表面122），电介质层的平面内CTE值（例如，CTE-XY-D-1）可以小于预定阈值（例如，3ppm每摄氏度，阈值320）。
在步骤403处，制造包括由步骤401处所确定的材料和步骤402处所确定的厚度T所制成的电介质层的器件。例如，所述器件可以包括WLP器件（例如，WLP器件100）。在另一个示例中，所述器件可以包括WLP器件和一个或多个电耦合到所述WLP器件（例如，到RDL 103）的焊球（例如，焊球106）。在另一个示例中，所述器件可以包括WLP器件、一个或多个焊球、和电耦合到一个或多个焊球的电路板（例如，电路板107）。
因而，已经描述了各种示例，其中，可以确定器件的电介质层的材料和厚度来增大其平面内热膨胀系数（CTE），同时保持电介质层的平面外CTE相对接近延伸穿过电介质层的互连的平面外CTE。结果，很大一部分由包括电介质层的器件（例如晶片级封装器件）和焊接到该器件的电路板之间的CTE不匹配所引起的应力可以被电介质层所吸收，并且继而可以减少由焊球所吸收的应力。这可以减小由热事件期间的分层和裂化所引起的电路断开和/或短路的可能性。在一些例子中，这可以导致更长的使用寿命并改善诸如TCoB（板上温度、循环）测试之类的板级测试的可靠性，其独立于半导体器件（例如半导体器件101）、较大的器件（例如，WLP器件100）或二者的尺寸。在一些例子中，与传统技术相比，这还可以允许由于减小由焊球所吸收的应力而增加半导体器件和/或总体器件的尺寸。在一些布置中，例如，如果使用本文所述的单面方法，器件的弯曲超过特定量或变得不可接受地高，那么可以将电介质或其他材料以合适的厚度施加于WLP器件的背面（例如，在半导体器件101的与表面121相对的表面）来至少部分补偿过分的弯曲。
虽然已经图示并描述了各种实施例，但是这仅仅是示例。在本说明书中使用的词语是描述的词语而非限制，并且理解为可以在不背离本公开的精神和范围的情况下进行各种改变。

Claims (20)

1.一种器件，包括：
半导体器件，在所述半导体器件的第一表面上具有至少一个电接触；
导电重分布层；以及
电介质层，被布置在所述第一表面和重分布层的表面之间，所述电介质层具有延伸穿过电介质层并且将所述至少一个电接触电耦合于重分布层的至少一个互连，
其中，所述电介质层具有垂直于所述第一表面的方向上的热膨胀系数（CTE）值和杨氏模量，
其中，所述电介质层的CTE值小于第一阈值，以及
其中，所述电介质层的杨氏模量大于第二阈值，
其中，确定所述电介质层的材料和厚度来增大其在平行于所述第一表面的方向上的热膨胀系数（CTE）值，同时保持所述电介质层的在垂直于所述第一表面的方向上的热膨胀系数（CTE）值接近于所述至少一个互连的热膨胀系数（CTE）值。
2.如权利要求1所述的器件，进一步包括，电耦合于所述重分布层的至少一个焊球，其中所述重分布层被布置在电介质层和所述至少一个焊球之间。
3.如权利要求2所述的器件，进一步包括，电耦合于所述至少一个焊球的电路板，其中所述至少一个焊球被布置在重分布层和所述电路板之间。
4.如权利要求1所述的器件，其中，所述重分布层是扇入重分布层和扇出重分布层之一。
5.如权利要求1所述的器件，其中，所述第一阈值是32ppm每摄氏度。
6.如权利要求1所述的器件，其中，所述第二阈值是25GPa。
7.如权利要求1所述的器件，
其中，所述电介质层在平行于第一表面的方向上面对第一表面的表面处具有第一CTE值，以及在平行于第一表面的方向上面对所述重分布层的表面的表面处具有第二CTE值，
其中，所述电介质层的第一CTE值小于4ppm每摄氏度，并且
其中，所述电介质层的第二CTE值大于6ppm每摄氏度。
8.如权利要求7所述的器件，其中，所述电介质层的厚度小于100微米。
9.一种器件，包括：
半导体器件，在所述半导体器件的第一表面上具有至少一个电接触；
导电重分布层；以及
电介质层，被布置在所述第一表面和重分布层的表面之间，所述电介质层具有延伸穿过电介质层并且将所述至少一个电接触电耦合于重分布层的至少一个互连，
其中，所述电介质层具有垂直于所述第一表面的方向上的热膨胀系数（CTE）值和杨氏模量，
其中，所述电介质层的CTE值和所述至少一个互连的CTE值之间的差异小于第一阈值，以及
其中，所述电介质层的杨氏模量大于第二阈值，
其中，确定所述电介质层的材料和厚度来增大其在平行于所述第一表面的方向上的热膨胀系数（CTE）值，同时保持所述电介质层的在垂直于所述第一表面的方向上的热膨胀系数（CTE）值接近于所述至少一个互连的热膨胀系数（CTE）值。
10.如权利要求9所述的器件，进一步包括，电耦合于所述重分布层的至少一个焊球，其中所述重分布层被布置在电介质层和所述至少一个焊球之间。
11.如权利要求10所述的器件，进一步包括，电耦合于所述至少一个焊球的电路板，以使得所述焊球被布置在重分布层和所述电路板之间。
12.如权利要求10所述的器件，其中，所述重分布层是扇入重分布层和扇出重分布层之一。
13.如权利要求9所述的器件，其中，所述第一阈值是15ppm每摄氏度。
14.如权利要求9所述的器件，其中，所述第二阈值是25GPa。
15.如权利要求9所述的器件，
其中，所述电介质层在平行于第一表面的方向上面对第一表面的表面处具有第一CTE值，以及在平行于第一表面的方向上面对所述重分布层的表面的表面处具有第二CTE值，
其中，所述电介质层的第一CTE值小于4ppm每摄氏度，并且
其中，所述电介质层的第二CTE值大于6ppm每摄氏度。
16.如权利要求15所述的器件，其中，所述电介质层的厚度小于100微米。
17.一种器件，包括：
半导体器件，包括硅并且在所述半导体器件的第一表面处具有至少一个电接触；
导电重分布层；以及
电介质层，包括环氧树脂并且被布置在所述第一表面和重分布层的表面之间，所述电介质层具有延伸穿过电介质层的至少一个铜互连，其将所述至少一个电接触电耦合于重分布层，
其中，确定所述电介质层的材料和厚度来增大其在平行于所述第一表面的方向上的热膨胀系数（CTE）值，同时保持所述电介质层的在垂直于所述第一表面的方向上的热膨胀系数（CTE）值接近于所述至少一个互连的热膨胀系数（CTE）值。
18.如权利要求17所述的器件，
其中，所述电介质层具有垂直于所述第一表面的方向上的热膨胀系数（CTE）值和杨氏模量，
其中，所述电介质层的CTE值和所述至少一个铜互连的CTE值之间的差异小于15ppm每摄氏度，以及
其中，所述电介质层的杨氏模量大于25GPa。
19.如权利要求18所述的器件，
其中，所述电介质层在平行于第一表面的方向上面对第一表面的表面处具有第一CTE值，以及在平行于第一表面的方向上面对所述重分布层的表面的表面处具有第二CTE值，
其中，所述电介质层的第一CTE值小于4ppm每摄氏度，并且
其中，所述电介质层的第二CTE值大于6ppm每摄氏度。
20.如权利要求17所述的器件，其中，所述电介质层的厚度在50和70微米之间。
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