CN103378052B - 半导体器件及其制造方法以及形成导电部件的方法 - Google Patents
半导体器件及其制造方法以及形成导电部件的方法 Download PDFInfo
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- CN103378052B CN103378052B CN201210350994.0A CN201210350994A CN103378052B CN 103378052 B CN103378052 B CN 103378052B CN 201210350994 A CN201210350994 A CN 201210350994A CN 103378052 B CN103378052 B CN 103378052B
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- 238000000034 method Methods 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 230000015572 biosynthetic process Effects 0.000 title claims description 15
- 239000010410 layer Substances 0.000 claims abstract description 275
- 239000012774 insulation material Substances 0.000 claims abstract description 167
- 239000000463 material Substances 0.000 claims abstract description 90
- 239000011241 protective layer Substances 0.000 claims abstract description 78
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims description 53
- 238000000059 patterning Methods 0.000 claims description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 239000003989 dielectric material Substances 0.000 claims description 32
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 29
- 239000011435 rock Substances 0.000 claims description 24
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 229960001866 silicon dioxide Drugs 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 7
- 229910052741 iridium Inorganic materials 0.000 claims description 7
- 229910052742 iron Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 7
- 229910052703 rhodium Inorganic materials 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 230000000717 retained effect Effects 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 claims description 3
- 150000001412 amines Chemical class 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 description 13
- 239000010941 cobalt Substances 0.000 description 13
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000000654 additive Substances 0.000 description 6
- 230000000996 additive effect Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
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- 238000001514 detection method Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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Abstract
公开了半导体器件及其制造方法以及形成其导电部件的方法。半导体器件包括在工件上方设置的绝缘材料层。绝缘材料层包含具有约13%以上的碳(C)的含硅材料。导电部件设置在绝缘材料层内。导电部件包括在其顶面上设置的保护层。
Description
技术领域
本发明涉及半导体器件及其制造方法以及形成半导体器件的导电部件的方法。
背景技术
半导体器件用于各种电子应用中,举例来说,诸如个人电脑、移动电话、数码相机和其他电子设备。通常通过提供工件、在工件上方形成各种材料层和采用光刻来图案化各种层以形成集成电路来制造半导体器件。半导体产业通过不断减小最小部件尺寸来继续提高集成电路的各种电子元件(即,晶体管、二极管、电阻器、电容器等)的集成密度,这容许将更多的元件集成到给定区域中。
在半导体器件中使用诸如金属或半导体的导电材料用于建立集成电路的电连接。多年来,铝用作导电材料金属进行电连接,而二氧化硅用作绝缘体。但是,随着器件尺寸的降低,为了改善器件性能,用于导体和绝缘体的材料已经发生了改变。现在,在一些应用中,铜通常用作导电材料进行互连。在一些设计中已经开始应用低介电常数(k)材料和极低k材料。
本领域中需要用于半导体器件的导电部件的改进制造技术。
发明内容
为了解决上述技术问题,一方面,本发明提供了一种半导体器件,包括:绝缘材料层,设置在工件上方,所述绝缘材料层包含具有约13%以上的碳(C)的含硅材料;以及导电部件,设置在所述绝缘材料层内,所述导电部件包括在其顶面上设置的保护层。
在所述的半导体器件中,所述半导体器件还包括在所述工件上方设置的低介电常数(k)介电材料层,所述低k介电材料层的k值大约小于二氧化硅(SiO2)的k值,其中,所述绝缘材料层包括在所述低k介电材料层上方设置的保护盖层,并且所述导电部件的一部分还设置在所述低k介电材料层内。
在所述的半导体器件中,所述半导体器件还包括在所述工件上方设置的低介电常数(k)介电材料层,所述低k介电材料层的k值大约小于二氧化硅(SiO2)的k值,其中,所述绝缘材料层包括在所述低k介电材料层上方设置的保护盖层,并且所述导电部件的一部分还设置在所述低k介电材料层内,其中,所述保护盖层还包含氮(N)。
在所述的半导体器件中,所述半导体器件还包括在所述工件上方设置的低介电常数(k)介电材料层,所述低k介电材料层的k值大约小于二氧化硅(SiO2)的k值,其中,所述绝缘材料层包括在所述低k介电材料层上方设置的保护盖层,并且所述导电部件的一部分还设置在所述低k介电材料层内,其中,所述保护盖层还包含氮(N),并且所述保护盖层的总碳氮百分比为至少约50%。
在所述的半导体器件中,所述半导体器件还包括在所述工件上方设置的低介电常数(k)介电材料层,所述低k介电材料层的k值大约小于二氧化硅(SiO2)的k值,其中,所述绝缘材料层包括在所述低k介电材料层上方设置的保护盖层,并且所述导电部件的一部分还设置在所述低k介电材料层内,其中,所述保护盖层的厚度约为4至200nm。
在所述的半导体器件中,所述绝缘材料层包括低介电常数(k)介电材料层,所述低k介电材料层的k值大约小于二氧化硅(SiO2)的k值,并且所述低k介电材料层包含分别具有约60%以上的SiC或SiCN的富SiC材料或富SiCN材料。
所述的半导体器件还包括在所述工件上方设置的蚀刻终止层以及在所述蚀刻终止层上方设置的原硅酸四乙酯(TEOS)层,其中,所述绝缘材料层设置在所述TEOS层上方,并且所述导电部件还设置在所述TEOS层内。
所述的半导体器件还包括在所述工件上方设置的蚀刻终止层以及在所述蚀刻终止层上方设置的原硅酸四乙酯(TEOS)层,其中,所述绝缘材料层设置在所述TEOS层上方,并且所述导电部件还设置在所述TEOS层内,其中,所述导电部件还形成在所述蚀刻终止层的至少一部分内。
另一方面,本发明提供了一种制造半导体器件的方法,所述方法包括:在工件上方形成绝缘材料层,所述绝缘材料层包含具有约13%以上的碳(C)的富碳化硅(SiC)材料;图案化所述绝缘材料层;在图案化的绝缘材料层中形成导电部件;以及在所述导电部件的顶面上形成保护层,其中,形成所述保护层包括形成选自基本上由Co、Rh、Ir、Fe、Ni和它们的组合所组成的组的材料。
在所述的方法中,形成所述导电部件包括在所述图案化的绝缘材料层上方形成导电材料以及采用化学机械抛光(CMP)工艺从所述图案化的绝缘材料层的顶面上方去除所述导电材料的多余部分,留下位于所述图案化的绝缘材料层中的导电部件。
在所述的方法中,形成所述导电部件包括在所述图案化的绝缘材料层上方形成导电材料以及采用化学机械抛光(CMP)工艺从所述图案化的绝缘材料层的顶面上方去除所述导电材料的多余部分,留下位于所述图案化的绝缘材料层中的导电部件,其中,形成所述导电部件包括单镶嵌工艺或双镶嵌工艺。
在所述的方法中,形成所述导电部件包括在所述图案化的绝缘材料层上方形成导电材料以及采用化学机械抛光(CMP)工艺从所述图案化的绝缘材料层的顶面上方去除所述导电材料的多余部分,留下位于所述图案化的绝缘材料层中的导电部件,其中,形成所述导电部件包括单镶嵌工艺或双镶嵌工艺,其中,形成所述导电部件包括形成具有通孔部分和在所述通孔部分上方设置的导线部分的导电部件。
在所述的方法中,所述富SiC材料保护所述绝缘材料层免受来自所述保护层中的材料的污染,或者所述富SiC材料保护设置在所述绝缘材料层下面的材料层免受来自所述保护层的污染。
在所述的方法中,形成所述保护层包括形成第二保护层,并且还包括在形成所述第二保护层之前,采用H2和/或He处理在所述绝缘材料层上方形成第一保护层。
又一方面,本发明提供了一种形成半导体器件的导电部件的方法,所述方法包括:提供工件;在所述工件上方形成蚀刻终止层;在所述蚀刻终止层上方形成第一绝缘材料层;在所述第一绝缘材料层上方形成第二绝缘材料层,所述第二绝缘材料层包含具有约13%以上的碳(C)的富碳化硅(SiC)材料;用导电部件的图案来图案化所述第一绝缘材料层和所述第二绝缘材料层;在图案化的第一绝缘材料层和图案化的第二绝缘材料层上方形成衬垫;在所述衬垫上方形成导电材料;实施化学机械抛光(CMP)工艺,从所述第二绝缘材料层的顶面上方去除所述导电材料和所述衬垫并形成导电部件,所述导电部件包含保留在所述图案化的第一绝缘材料层和所述图案化的第二绝缘材料层中的所述导电材料和所述衬垫;以及在所述导电部件的顶面上形成保护层,其中,形成所述保护层包括形成选自基本上由Co、Rh、Ir、Fe、Ni和它们的组合所组成的组的材料。
在所述的方法中,所述蚀刻终止层包括第一蚀刻终止层,所述方法还包括在所述保护层和所述第二绝缘材料上方形成第二蚀刻终止层。
在所述的方法中,形成所述保护层包括形成厚度约为1至3nm的保护层。
所述的方法还包括在所述导电部件的顶面上抛光所述保护层。
在所述的方法中,形成所述导电衬垫包括形成厚度约为1.0至4.5nm的层,或者形成所述衬垫包括形成选自基本上由TiN、TaN和它们的组合所组成的组的材料。
在所述的方法中,形成所述第二绝缘材料层包括在胺环境中形成所述富SiC材料。
附图说明
为了更全面地理解本发明及其优点,现在参考结合附图所进行的以下描述,其中:
图1至图8示出采用单镶嵌工艺在各个制造阶段形成根据本发明实施例的半导体器件的导电部件的方法的截面图,其中在介电堆叠件上方形成保护盖层以保护下面的材料层免受污染;
图9是另一实施例的截面图,其中绝缘材料包括在其中形成的用于污染保护的保护物质;
图10示出其中采用双镶嵌工艺形成导电部件并且该结构包括接近导电部件的用于污染保护的材料层的实施例的截面图;
图11是根据实施例示出形成半导体器件的导电部件的方法的流程图;以及
图12至图18示出根据另一实施例在各个制造阶段形成导电部件的方法的截面图。
除非另有说明,不同附图中的相应标号和符号通常是指相应部件。绘制附图用于清楚地示出实施例的相关方面而不必按比例绘制。
具体实施方式
在下面详细论述本发明实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅是制造和使用本发明的说明性具体方式,而不用于限制本发明的范围。
本发明的实施例涉及半导体和半导体器件结构的制造方法。在本文中将描述形成半导体器件及其结构的导电部件的新方法,其中接近导电部件形成保护材料以防止接近导电部件的材料层受到将在本文进一步描述的随后形成的保护层的污染。
图1至图8示出在采用单镶嵌工艺制造的各个阶段形成根据本发明实施例的半导体器件100的导电部件130(见图8)的方法的截面图。注意到在本文的附图中仅示出一个导电部件130;但是,根据本文中的实施例,在半导体器件100的整个表面形成多个导电部件130。
首先参照图1,为了形成导电部件130,提供工件102。举例来说,工件102可以包括包含硅或其他半导体材料的半导体衬底并且可以被绝缘层覆盖。工件102还可以包括未示出的其他有源元件或电路。举例来说,工件102可以包含位于单晶硅上方的氧化硅。工件102可以包括其他导电层或其他半导体元件,例如晶体管、二极管等。化合物半导体例如GaAs、InP、Si/Ge或SiC可以用于替代硅。作为实例,工件102可以包括绝缘体上硅(SOI)或绝缘体上锗(GOI)衬底。举例来说,工件102可以包括在其上形成的一个或多个电路和/或电子功能层,并且可以包括导线、通孔、电容器、二极管、晶体管、电阻器、电感器和/或在前段工序(FEOL)工艺和/或后段工序(BEOL)工艺中形成的其他电子元件(未示出)。
如图1所示,在工件102上方形成包含绝缘体的蚀刻终止层(ESL)104。ESL104可以包含通过化学汽相沉积(CVD)或物理汽相沉积(PVD)形成的约8至30nm的氮化硅或SiCN,然而可选地,ESL104可以包含其他材料和尺寸并且可以采用其他方法形成。ESL104在本文中也被称为例如第一蚀刻终止层。
如图1所示,在ESL104上方形成第一绝缘材料层106。第一绝缘材料层106包括通过CVD形成的厚度约为5至30nm的原硅酸四乙酯(TEOS)层。第一绝缘材料层106可以可选地包含其他尺寸和材料并且可以采用其他方法形成。举例来说,在一些实施例中,TEOS106保护随后形成的第二绝缘材料层108不暴露于ESL104中的氮。
在图1中还示出,在第一绝缘材料层106上方形成第二绝缘材料层108。第二绝缘材料层108包含k值大约小于二氧化硅(SiO2)的k值(约3.9)的低介电常数(k)介电材料。作为实例,在一些实施例中,第二绝缘材料层108包含介电常数小于约2.7的极低k介电材料。第二绝缘材料层108可以包含通过CVD沉积的约40至200nm的SiCOH,然而可选地,第二绝缘材料层108可以可选地包含其他尺寸和材料并且可以采用其他方法形成。
在一些实施例中,第一绝缘材料层106包含在结构上比第二绝缘材料层108更坚固的材料。举例来说,为了集成目的,第一绝缘材料层106可以具有大于第二绝缘材料层108的k值。举例来说,第二绝缘材料层108可以是多孔的,还提供小于第一绝缘材料层106的k值,从而降低包括层104、106、108和110的介电堆叠件的总介电常数。
根据实施例,如图1所示,在第二绝缘材料层108上方形成覆盖层110。覆盖层110在本文中也被称为保护盖层或绝缘材料层。在该实施例中,覆盖层110适合于保护下面的第二绝缘材料层108。在一些实施例中,覆盖层110包含具有约13%以上的碳(C)的富碳化硅(SiC)材料。在一些实施例中,覆盖层110包含SiC。覆盖层110还可以包含氮(N);例如,覆盖层110可以包含SiCN。在一些实施例中,保护盖层110的总碳氮百分比为至少约50%。可以采用CVD或PVD沉积保护盖层110并且保护盖层110的厚度可以约为4至200nm。作为实例,在一些实施例中可以通过在胺环境中形成富SiC材料来形成覆盖层110,从而将N引入富SiC材料中。可选地,覆盖层110可以包含其他尺寸和材料并且可以采用其他方法形成。
第一绝缘材料层106和第二绝缘材料层108在本文中又被统称为第一绝缘材料层106/108(例如在一些权利要求中)。在这些实施例中,覆盖层110在本文中也被称为第二绝缘材料层110,其中第二绝缘材料层110包含具有约13%以上的碳(C)的富碳化硅(SiC)材料。
根据本发明的实施例,覆盖层110、第二绝缘材料层108、第一绝缘材料层106和任选的ESL104或其一部分包括将其中形成有导电部件130(见图8)的介电堆叠件。采用光刻来图案化介电堆叠件,并用导电材料填充图案化的介电堆叠件以形成将在本文中进一步描述的导电部件130。
如图1所示,在覆盖层110上方形成光刻胶层112。采用光刻通过将光刻胶层112曝露于穿过光刻掩模(未示出)或从光刻掩模反射的能量来图案化光刻胶层112。然后,如图2所示,灰化并蚀刻掉光刻胶层112的暴露(或未暴露,取决于光刻胶112是正的还是负的)部分,在光刻胶层112中形成用于导电部件的图案114。然后,如图3所示,光刻胶层112在蚀刻工艺116过程中用作蚀刻掩模,将光刻胶层112的图案114转印到第二绝缘材料层108和第一绝缘材料层106。蚀刻工艺116可以包括反应离子蚀刻(RIE)工艺或其中蚀刻掉部分的覆盖层110、第二绝缘材料层108、第一绝缘材料层106,以及任选部分或全部的蚀刻终止层104(图3中未示出,参见图10中示出的实施例)的其他类型的蚀刻工艺。然后,如图4所示,去除光刻胶层112。
如图5所示,在图案化的覆盖层110、第二绝缘材料层108和第一绝缘材料层106上方形成衬垫118。作为实例,衬垫118可以包含通过PVD或溅射形成的约1.0至4.5nm的导电材料,诸如TiN、TaN、或它们的组合或多层。可选地,衬垫118可以包含其他尺寸和材料并且可以采用其他方法形成。举例来说,在一些实施例中,衬垫118可以用作后续沉积的导电材料120的阻挡层。
在图5中还示出,例如在位于图案化的覆盖层110和绝缘材料层108和106内的衬垫118上方形成导电材料120。作为实例,导电材料120包含铜(Cu)或其合金并且可以通过溅射、电镀或无电镀来形成,然而可选地,导电材料120可以包含其他材料和尺寸。导电材料120填充覆盖层110及绝缘材料层108和106中的图案,并且导电材料120还形成在位于图案化的覆盖层110的顶面上的衬垫118的顶面上方。如图6所示,实施化学机械抛光(CMP)工艺122以从覆盖层110的顶面上方去除导电材料120和衬垫118并形成导电部件121。导电部件121包括在该制造工艺阶段保留在图案化的第一绝缘材料层106、第二绝缘材料层108、覆盖层110以及任选的至少一部分ESL104中的导电材料120和衬垫118。
在图6中还示出,在CMP工艺122之后,衬垫118和导电材料120的顶面可以任选地略微凹陷低于覆盖层110的顶面。可选地,如将在本文中进一步描述的图10示出的实施例中所示,衬垫118和导电材料120的顶面可以与覆盖层110的顶面基本共面。
如图7所示,在导电部件121的顶面上形成包含Co、Rh、Ir、Fe、Ni、或它们的组合或多层的保护层124。如图7所示,可以通过在加工半导体器件100的室中引入诸如CpCo(CO)2的含钴气体和NH3形成保护层124,从而在导电材料120和衬垫118的暴露表面上形成包括钴层的保护层124。举例来说,由于覆盖层110的材料,保护层124未形成在覆盖层110上。保护层124的厚度可以约为1至3nm。可选地,可以采用其他方法形成保护层124,并且保护层124可以包含其他材料和尺寸。在凹陷的导电材料120和衬垫118上方形成保护层124。在导电材料120和衬垫118上方设置的保护层124改善了导电材料120和衬垫118的电迁移特性。
在图7中还示出,可以采用任选的抛光工艺126抛光保护层124。在该实施例中,包含富SiC或富SiCN材料的覆盖层110在抛光工艺126的过程中保护下面的第二绝缘材料层108,有利地阻止第二绝缘材料层108的顶面在抛光保护层124的过程中免受来自保护层124中的诸如钴的材料的污染。举例来说,没有覆盖层110,第二绝缘材料层108的顶面可能被保护层124中的钴或其他材料污染,因为钴是导电的,这可能导致时间相关电介质击穿(TDDB)退化。
在抛光工艺126之后,在该实施例中,保护层124的顶面与覆盖层110的顶面基本共面。可选地,保护层124的顶面可以与覆盖层110非共面,并且可以具有大于保护层124的顶面的高度,如将在本文中作进一步描述的图9和图10所示。
如图8所示,在抛光保护层124之后,可以在保护层124和覆盖层110上方形成任选的蚀刻终止层128。蚀刻终止层128在本文中也被称为第二蚀刻终止层128。举例来说,第二蚀刻终止层128可以包含与对第一蚀刻终止层104所述的相类似的材料和尺寸并且可以通过相类似的方法形成。第二蚀刻终止层128可以包括用于例如后续形成的材料层(未示出)的蚀刻终止层。
在图案化的第一绝缘材料层106、第二绝缘材料层108和覆盖层110中形成的导电部件130包括导电材料120、衬垫118以及在它们的顶面形成的保护层124。导电部件130可以包括例如在纸(未示出)内外延伸的通孔、插塞或导线。有利地是,保护盖层110保护下面的包含低k介电材料的第二绝缘材料108免受钴污染或来自保护层124中的另一材料的污染,防止最终产品中的导电部件130的电迁移问题。
在其他实施例中,在结构中不包括覆盖层110,并且在包含低k材料的第二绝缘材料层108’中包含保护材料,如图9所示。示出了实施例的截面图,其中第二绝缘材料层108’包含在其中形成的用于钴污染保护或保护免受保护层124中的另一材料的污染的保护物质。在一些实施例中,绝缘材料层108’包含具有约13%以上的碳(C)的富碳化硅(SiC)材料。绝缘材料层108’包括低介电常数(k)介电材料层,低k介电材料层的k值大约小于例如二氧化硅(SiO2)的k值。在一些实施例中,低k介电材料层包含分别具有约60%以上的SiC或SiCN的富SiC材料或富SiCN材料。可选地,低k介电材料可以包含其他材料。
用导电部件的所需图案来图案化第二绝缘材料层108’和第一绝缘材料层106,如对图1至图8的实施例所述的,并且在第二绝缘材料层108’上方形成衬垫118和导电材料120。CMP工艺122用于从第二绝缘材料层108的顶面上方(不是从覆盖层110的上方,在该实施例中不包括覆盖层110)去除多余的衬垫118和导电材料120。在导电材料120和衬垫118上方形成保护层124,在第一绝缘材料层106和第二绝缘材料层108’内(以及任选地在ESL104(未示出)的至少一部分中)形成导电部件130。在该实施例中,保护层124可以是足够薄的而不需要抛光。在图9中还示出,可以在第二绝缘材料层108’和导电部件130上方任选地形成第二ESL128。在该实施例中,第二绝缘材料层108’的富SiC材料保护第二绝缘材料层108’的顶面在钴沉积工艺过程中免受来自保护层124中的钴或另一材料的污染。
在图9中示出的实施例中,在CMP工艺122之后,衬垫118和导电材料120的顶面可以任选地略微凹陷低于第二绝缘材料层108’的顶面。如图所示,保护层124的顶面可以与第二绝缘材料层108’的顶面不共面并且可以位于第二绝缘材料层108’的顶面上方。可选地,衬垫118和导电材料120的顶面可以与CMP工艺122的顶面基本共面,和/或保护层124的顶面在保护层124的抛光工艺126之后可以与第二绝缘材料层108’的顶面共面(未示出)。
图10示出其中采用双镶嵌工艺形成导电部件130的实施例的截面图。在工件102上方形成本文所述的材料层104、106、108或108’、和/或110之后,采用两种光刻掩模(一种用于通孔而另一种用于在通孔上方设置的导线)图案化材料层104、106、108或108’、和/或110。实施本文中先前描述的制造工艺步骤,形成导电部件130,其具有位于下部区域中的通孔部分132和在通孔部分132上方设置的导线部分134。举例来说,在衬垫118和导电材料120的沉积工艺中同时填充通孔部分132和导线部分134的图案。在该结构中可以任选地包括具有富SiC材料的覆盖层110和第二绝缘材料层108’,或者可选地,在该结构中可以包括覆盖层110或第二绝缘材料层108’用于保护免受来自保护层124的材料的污染。
在图10中示出的实施例中,还用导电部件130的通孔部分132的图案来图案化蚀刻终止层104。举例来说,当在蚀刻工艺116的过程中再也检测不到蚀刻终止层104的化学物质或者检测到蚀刻终止层104的化学物质减少的时候,可以适时停止蚀刻工艺116(在图10中未示出;见图3),从而当图案化蚀刻终止层104时,中断蚀刻工艺116。可选地,在中断蚀刻工艺116之后,通过检测到达蚀刻终止层104的时间,可以图案化蚀刻终止层104的一部分。在这些实施例中,可以图案化蚀刻终止层104的顶部的一小部分。
图10还示出其中衬垫118和导电材料120的顶面在CMP工艺122之后与覆盖层110(或绝缘材料层108’(如果不包括覆盖层110))的顶面基本共面的实施例。在保护层124的抛光工艺126之后,保护层124的顶面与覆盖层110(或绝缘材料层108’)的顶面不共面并且位于覆盖层110(或绝缘材料层108’)的顶面上方。可选地,衬垫118和导电材料120的顶面可以凹陷低于覆盖层110或绝缘材料108’的顶面,如先前实施例中所示,和/或保护层124的顶面可以与覆盖层110或绝缘材料108’的顶面基本共面(未示出)。
图11是示出根据实施例形成半导体器件100的导电部件130的方法的流程图160。在步骤162中,提供工件102。在步骤164中,在工件102上方形成包含富SiC材料的绝缘材料层110或108’。在步骤166中,图案化绝缘材料层110或108’。在步骤168中,在图案化的绝缘材料层110或108’中形成导电部件121。在步骤170中,在导电部件121的顶面上形成保护层124,从而形成包括保护层124的导电部件130。
图12至图18示出根据本发明的另一实施例在各个制造阶段形成导电部件的方法的截面图,其中采用H2和/或He处理形成覆盖层110。如图12所示,在工件102上方形成ESL104,在ESL104上方形成第一绝缘材料层106,以及在第一绝缘材料层106上方形成第二绝缘材料层108。在第二绝缘材料层108上方形成光刻胶层112。如图13所示,图案化光刻胶层112,然后将其用作掩模,同时采用蚀刻工艺116蚀刻掉部分的第二绝缘材料层108、第一绝缘材料层106和ESL104。
如图14所示,在图案化的材料层108、106和104上方形成衬垫118,并且在衬垫118上方形成导电材料120。在图14中还示出,采用CMP工艺122从第二绝缘材料层108的顶面上方去除部分的导电材料120和衬垫118,形成导电部件121并留下图15中所示的结构。
在图15中还示出,将半导体器件100暴露于H2和/或He处理180,如图16所示,形成覆盖层110。H2和/或He处理180与第二绝缘材料层108的顶面反应,形成包含诸如SiCOH的材料的覆盖层110。由于H2和/或He处理180,覆盖层110是密实的并且具有较少的水分。举例来说,覆盖层110通过保护层124中诸如Co的材料防止绝缘材料层108受到污染。
然后,如图17所示,在导电材料120和衬垫118的顶面上方形成保护层124,并且可以任选地抛光保护层124。如图18所示,可以在保护层124和覆盖层110的顶面上方形成ESL128。注意到,举例来说,在本发明的一些权利要求中,保护层124也被称为第二保护层124,而覆盖层110也被称为第一保护层110。
本发明的实施例包括制造半导体器件100和导电部件的方法,并且还包括采用本文中所述的方法制造的半导体器件100。
本发明实施例的优点包括提供用于具有改进的钴保护完整性的导电部件130的新设计及其制造方法。保护层124包括用于导电部件130的覆盖层,其减少了导电部件130的电迁移,并且避免了下面的低介电常数材料层(诸如本文中所述的第二绝缘材料层108和108’)的钴和其他材料的污染。在一些实施例中,第二绝缘材料层108’中包含的富SiC材料保护第二绝缘材料层108’免受来自保护层124中的钴或其他材料的污染。在其他实施例中,保护盖层110中的富SiC材料保护设置在保护盖层110下面的材料层(诸如第二绝缘材料层108)免受来自保护层124的污染。在一些实施例中,在第二绝缘材料层108’和保护盖层110中都可以包含富SiC材料,提供额外的污染保护。
由于阻止对敏感低k绝缘材料层108和108’的钴和其他材料的污染,新型半导体器件100的TDDB结果得到了改善。保护盖层110和/或第二绝缘材料层108’的高碳含量还导致了改善的击穿电压(VBD)结果。作为一个实例,测试结果揭示了通过实施本发明的实施例实现了大于约90%的Co污染降低。在制造工艺流程中新型半导体器件100和制造方法是容易实施的。
根据本发明的一个实施例,半导体器件包括在工件上方设置的绝缘材料层。绝缘材料层包含具有约13%以上的碳(C)的含硅材料。导电部件设置在绝缘材料层内。导电部件包括在其顶面上设置的保护层。
根据另一实施例,制造半导体器件的方法包括在工件上方形成绝缘材料层,包含富SiC材料的绝缘材料层包含约13%以上的碳。该方法包括图案化绝缘材料层,以及在图案化的绝缘材料层中形成导电部件。在导电部件的顶面上形成保护层。保护层包含选自基本上由Co、Rh、Ir、Fe、Ni和它们的组合所组成的组的材料。
根据又一实施例,一种形成半导体器件的导电部件的方法包括提供工件;在工件上方形成蚀刻终止层;在蚀刻终止层上方形成第一绝缘材料层;以及在第一绝缘材料层上方形成第二绝缘材料层。第二绝缘材料层包含具有约13%以上的碳的富SiC材料。该方法包括用导电部件的图案来图案化第一绝缘材料层和第二绝缘材料层;在图案化的第一绝缘材料层和图案化的第二绝缘材料层上方形成衬垫;以及在衬垫上方形成导电材料。实施CMP工艺,从第二绝缘材料层顶面的上方去除导电材料和衬垫以及形成包括保留在图案化的第一绝缘材料层和图案化的第二绝缘材料层中的导电材料和衬垫的导电部件。在导电部件的顶面上形成保护层。保护层包含选自基本上由Co、Rh、Ir、Fe、Ni和它们的组合所组成的组的材料。
尽管已经详细地描述了本发明的实施例及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,在其中做各种不同的改变、替换和更改。例如,本领域的技术人员将很容易理解本文中描述的许多部件、功能、工艺和材料都可以发生改变而仍保留在本发明的范围内。而且,本申请的范围并不限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的发明内容将很容易理解,根据本发明可以利用现有的或今后开发的用于执行与根据本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此,所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。
Claims (19)
1.一种半导体器件,包括:
绝缘材料层,设置在工件上方,所述绝缘材料层包含具有13%以上的碳(C)的含硅材料;以及
导电部件,设置在所述绝缘材料层内,所述导电部件包括在其顶面上设置的保护层;
所述半导体器件还包括在所述工件上方设置的低介电常数(k)介电材料层,所述低介电常数介电材料层的介电常数值小于二氧化硅(SiO2)的介电常数值,其中,所述绝缘材料层包括在所述低介电常数介电材料层上方设置的保护盖层,并且所述导电部件的一部分还设置在所述低介电常数介电材料层内。
2.根据权利要求1所述的半导体器件,其中,所述保护盖层还包含氮(N)。
3.根据权利要求2所述的半导体器件,其中,所述保护盖层的总碳氮百分比为至少50%。
4.根据权利要求1所述的半导体器件,其中,所述保护盖层的厚度为4至200nm。
5.根据权利要求1所述的半导体器件,其中,所述低介电常数介电材料层包含分别具有60%以上的SiC或SiCN的富SiC材料或富SiCN材料。
6.根据权利要求1所述的半导体器件,还包括在所述工件上方设置的蚀刻终止层以及在所述蚀刻终止层上方设置的原硅酸四乙酯(TEOS)层,其中,所述绝缘材料层设置在所述原硅酸四乙酯层上方,并且所述导电部件还设置在所述原硅酸四乙酯层内。
7.根据权利要求6所述的半导体器件,其中,所述导电部件还形成在所述蚀刻终止层的至少一部分内。
8.一种制造半导体器件的方法,所述方法包括:
在工件上方形成绝缘材料层,所述绝缘材料层包含具有13%以上的碳(C)的富碳化硅(SiC)材料;
图案化所述绝缘材料层;
在图案化的绝缘材料层中形成导电部件;以及
在所述导电部件的顶面上形成保护层,其中,形成所述保护层包括形成选自由Co、Rh、Ir、Fe、Ni和它们的组合所组成的组的材料;
在所述工件上方设置低介电常数(k)介电材料层,所述低介电常数介电材料层的介电常数值小于二氧化硅(SiO2)的介电常数值,其中,所述绝缘材料层包括在所述低介电常数介电材料层上方设置的保护盖层,并且所述导电部件的一部分还设置在所述低介电常数介电材料层内。
9.根据权利要求8所述的制造半导体器件的方法,其中,形成所述导电部件包括在所述图案化的绝缘材料层上方形成导电材料以及采用化学机械抛光(CMP)工艺从所述图案化的绝缘材料层的顶面上方去除所述导电材料的多余部分,留下位于所述图案化的绝缘材料层中的导电部件。
10.根据权利要求9所述的制造半导体器件的方法,其中,形成所述导电部件包括单镶嵌工艺或双镶嵌工艺。
11.根据权利要求10所述的制造半导体器件的方法,其中,形成所述导电部件包括形成具有通孔部分和在所述通孔部分上方设置的导线部分的导电部件。
12.根据权利要求8所述的制造半导体器件的方法,其中,所述富碳化硅材料保护所述绝缘材料层免受来自所述保护层中的材料的污染,或者所述富碳化硅材料保护设置在所述绝缘材料层下面的材料层免受来自所述保护层的污染。
13.根据权利要求8所述的制造半导体器件的方法,其中,形成所述保护层包括形成第二保护层,并且还包括在形成所述第二保护层之前,采用H2和/或He处理所述保护盖层。
14.一种形成半导体器件的导电部件的方法,所述方法包括:
提供工件;
在所述工件上方形成蚀刻终止层;
在所述蚀刻终止层上方形成第一绝缘材料层;
在所述第一绝缘材料层上方形成第二绝缘材料层,所述第二绝缘材料层包含具有13%以上的碳(C)的富碳化硅(SiC)材料;
用导电部件的图案来图案化所述第一绝缘材料层和所述第二绝缘材料层;
在图案化的第一绝缘材料层和图案化的第二绝缘材料层上方形成衬垫;
在所述衬垫上方形成导电材料;
实施化学机械抛光(CMP)工艺,从所述第二绝缘材料层的顶面上方去除所述导电材料和所述衬垫并形成导电部件,所述导电部件包含保留在所述图案化的第一绝缘材料层和所述图案化的第二绝缘材料层中的所述导电材料和所述衬垫;以及
在所述导电部件的顶面上形成保护层,其中,形成所述保护层包括形成选自由Co、Rh、Ir、Fe、Ni和它们的组合所组成的组的材料。
15.根据权利要求14所述的形成半导体器件的导电部件的方法,其中,所述蚀刻终止层包括第一蚀刻终止层,所述方法还包括在所述保护层和所述第二绝缘材料上方形成第二蚀刻终止层。
16.根据权利要求14所述的形成半导体器件的导电部件的方法,其中,形成所述保护层包括形成厚度为1至3nm的保护层。
17.根据权利要求14所述的形成半导体器件的导电部件的方法,还包括在所述导电部件的顶面上抛光所述保护层。
18.根据权利要求14所述的形成半导体器件的导电部件的方法,其中,形成所述衬垫包括形成厚度为1.0至4.5nm的层,或者形成所述衬垫包括形成选自由TiN、TaN和它们的组合所组成的组的材料。
19.根据权利要求14所述的形成半导体器件的导电部件的方法,其中,形成所述第二绝缘材料层包括在胺环境中形成所述富碳化硅材料。
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US10910307B2 (en) | 2018-11-02 | 2021-02-02 | International Business Machines Corporation | Back end of line metallization structure |
US10930551B2 (en) * | 2019-06-28 | 2021-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for fabricating a low-resistance interconnect |
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