CN103353832B - 应用于嵌入式显示接口的动态随机存取存储器 - Google Patents
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Abstract
应用于嵌入式显示接口的动态随机存取存储器包含一记忆核心单元、一周边电路单元及一输入/输出单元。该记忆核心单元是用以操作于一第一预定电压;该周边电路单元是电性连接于该记忆核心单元,用以操作于一第二预定电压,其中该第二预定电压是小于1.1V;该输入/输出单元是电性连接于该周边电路单元与该记忆核心单元,用以操作于一第三预定电压,其中该第三预定电压是小于1.1V。
Description
技术领域
本发明涉及一种动态随机存取存储器,尤其涉及一种应用于嵌入式显示接口的动态随机存取存储器。
背景技术
视频电子协会(Video Electronics Standards Association,VESA)所发表的嵌入式显示接口(Embedded Display Port,eDP)技术是用以做为外部连接的标准显示面板接口。例如嵌入式显示接口可做为显示卡与笔记型计算机面板之间的接口。视频电子协会所发表的嵌入式显示接口1.3版新增面板自动刷新(panel selfrefresh,PSR)功能,其中面板自动刷新功能可使图形处理器(Graphic ProcessingUnit,GPU)在画面静止时,关闭图形处理器与液晶面板之间的连接,可大幅降低图形处理器的功耗以及延长电池续航力。
另外,支援面板自动刷新功能的液晶显示器的时序控制器必须包含一画面暂存器(动态随机存取存储器)。当图形处理器关闭与液晶面板之间的连接时,画面暂存器必须储存图形处理器关闭与液晶面板之间的连接前的最后一个画面。因此,当图形处理器关闭与液晶面板之间无数据传输时,时序控制器可直接输出储存于画面暂存器的最后一个画面。
虽然面板自动刷新功能可使图形处理器的功耗大幅降低,但时序控制器的功耗却因画面暂存器的运作而上升。因此,如何设计画面暂存器以降低时序控制器的功耗将成为存储器制造商的一项重要课题。
发明内容
本发明的目的在于提供一种应用于嵌入式显示接口,可以使系统功耗大幅降低,不会使时序控制器的功耗因画面暂存器的运作而上升,以及延长手持式装置的电池续航力。
本发明的一实施例提供一种应用于嵌入式显示接口(Embedded DisplayPort)的动态随机存取存储器。该动态随机存取存储器包含一记忆核心单元及一周边电路单元。该记忆核心单元是用以操作于一第一预定电压;该周边电路单元是电性连接于该记忆核心单元,用以操作于一第二预定电压,其中该第二预定电压是小于1.1V。
本发明的另一实施例提供一种应用于嵌入式显示接口的动态随机存取存储器。该动态随机存取存储器包含一记忆核心单元、一周边电路单元及一输入/输出单元。该记忆核心单元是用以操作于一第一预定电压;该周边电路单元是电性连接于该记忆核心单元,用以操作于一第二预定电压,其中该第二预定电压是小于1.1V;该输入/输出单元是电性连接于该周边电路单元与该记忆核心单元,用以操作于一第三预定电压,其中该第三预定电压是小于1.1V。
本发明提供一种应用于嵌入式显示接口的动态随机存取存储器。该动态随机存取存储器是使其记忆核心单元、其周边电路单元和其输入/输出单元操作在较低的电压。相较于现有技术,本发明所提供的动态随机存取存储器的功耗是远低于一动态随机存取存储器操作在联合电子设备工程委员会所提供的操作电压时的功耗。如此,当本发明所提供的动态随机存取存储器应用于一嵌入式显示接口时,本发明可使系统功耗(例如图形处理器的功耗)大幅降低,不会使一时序控制器的功耗因一画面暂存器的运作而上升,以及延长一手持式装置的电池续航力。
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
附图说明
图1是本发明的一实施例说明一种应用于嵌入式显示接口的动态随机存取存储器的示意图。
其中,附图标记
100 动态随机存取存储器
102 记忆核心单元
104 周边电路单元
106 输入/输出单元
具体实施方式
下面结合附图对本发明的结构原理和工作原理作具体的描述:
请参照图1,图1是本发明的一实施例说明一种应用于嵌入式显示接口(Embedded Display Port)的动态随机存取存储器100的示意图,其中动态随机存取存储器100是做为液晶显示器内时序控制器的画面暂存器,且动态随机存取存储器100是相容于单倍数据速率(Single Data Rate,SDR)规格、双倍数据速率(Double Data Rate,DDR)规格、第二代双倍数据速率(DDR II)规格或第三代双倍数据速率(DDR III)规格。如图1所示,动态随机存取存储器100包含一记忆核心单元102、一周边电路单元104及一输入/输出单元106,其中周边电路单元104是电性连接于记忆核心单元102,以及输入/输出单元106是电性连接于周边电路单元104与记忆核心单元102。请参照表一,表一是说明联合电子设备工程委员会(Joint Electron Device Engineering Council,JEDEC)所规范动态随机存取存储器在第一代双倍数据速率(DDR I)规格、第一代低功耗双倍数据速率(Low Power DDR I)规格、第二代双倍数据速率(DDR II)规格和第二代低功耗双倍数据速率(Low Power DDR II)规格的操作电压。
表一
如果要使动态随机存取存储器100具有低功耗以降低时序控制器的功耗,则动态随机存取存储器100必须具有低操作功耗(例如动态随机存取存储器100输出所储存画面至时序控制器的功耗)与低待机功耗。但是联合电子设备工程委员会所规范的操作电压(如表一所示)并无法满足嵌入式显示接口1.3版的需求(低操作功耗与低待机功耗)。
请参照表二,表二是本发明的一实施例说明动态随机存取存储器100在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格的操作电压范围。
记忆核心单元102 | 周边电路单元104 | 输入/输出单元106 | |
操作电压范围 | <1.1V | <1.1V | <1.1V |
表二
如表二所示,记忆核心单元102在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于一第一预定电压,其中第一预定电压是小于1.1V。周边电路单元104在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于一第二预定电压,其中第二预定电压是小于1.1V。输入/输出单元106在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于一第三预定电压,其中第三预定电压是小于1.1V。
如表二所示,因为记忆核心单元102在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于第一预定电压,所以动态随机存取存储器100具有较低的记忆核心功耗;因为周边电路单元104在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于第二预定电压,所以动态随机存取存储器100具有较低的存取功耗;因为输入/输出单元106在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于第三预定电压,所以动态随机存取存储器100具有较低的输入/输出功耗。另外,输入/输出单元106是与现有的技术所提供的接口相容。因此,本发明所提供的动态随机存取存储器100的功耗是远低于动态随机存取存储器操作在联合电子设备工程委员会所提供的操作电压时的功耗。
请参照表三,表三是本发明的另一实施例说明动态随机存取存储器100在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格的操作电压范围。
记忆核心单元102 | 周边电路单元104 | 输入/输出单元106 | |
操作电压范围 | 1.8V±0.1V | <1.1V | <1.1V |
表三
如表三所示,记忆核心单元102在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于一第一预定电压,其中第一预定电压是等于1.8V±0.1V。周边电路单元104在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于一第二预定电压,其中第二预定电压是小于1.1V。输入/输出单元106在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于一第三预定电压,其中第三预定电压是小于1.1V。
如表三所示,因为记忆核心单元102在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于第一预定电压(1.8V±0.1V),所以动态随机存取存储器100具有较高的电荷泵效率;因为周边电路单元104在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于第二预定电压,所以动态随机存取存储器100具有较低的存取功耗;因为输入/输出单元106在第一代双倍数据速率规格、第一代低功耗双倍数据速率规格、第二代双倍数据速率规格和第二代低功耗双倍数据速率规格都是操作于第三预定电压,所以动态随机存取存储器100具有较低的输入/输出功耗。另外,输入/输出单元106是与现有的技术所提供的接口相容。因此,本发明所提供的动态随机存取存储器100的功耗是远低于动态随机存取存储器操作在联合电子设备工程委员会所提供的操作电压时的功耗。
综上所述,本发明所提供的应用于嵌入式显示接口的动态随机存取存储器是使记忆核心单元、周边电路单元和输入/输出单元操作在较低的电压。相较于现有技术,本发明所提供的动态随机存取存储器的功耗是远低于动态随机存取存储器操作在联合电子设备工程委员会所提供的操作电压时的功耗。如此,当本发明所提供的动态随机存取存储器应用于嵌入式显示接口时,本发明可使系统功耗(例如图形处理器的功耗)大幅降低,不会使时序控制器的功耗因画面暂存器的运作而上升,以及延长手持式装置的电池续航力。
当然,本发明还可有其他多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (5)
1.一种应用于嵌入式显示接口的动态随机存取存储器,其特征在于,包含:
一记忆核心单元,用以操作于一第一预定电压;及
一周边电路单元,电性连接于该记忆核心单元,用以操作于一第二预定电压,其中该第二预定电压是小于1.1V。
2.根据权利要求1所述的动态随机存取存储器,其特征在于,该第一预定电压是小于1.1V。
3.根据权利要求1所述的动态随机存取存储器,其特征在于,该第一预定电压是等于1.8V±0.1V。
4.根据权利要求2或3所述的动态随机存取存储器,其特征在于,另包含:
一输入/输出单元,电性连接于该周边电路单元与该记忆核心单元,用以操作于一第三预定电压,其中该第三预定电压是小于1.1V。
5.一种应用于嵌入式显示接口的动态随机存取存储器,其特征在于,包含:
一记忆核心单元,用以操作于一第一预定电压;
一周边电路单元,电性连接于该记忆核心单元,用以操作于一第二预定电压,其中该第二预定电压是小于1.1V;及
一输入/输出单元,电性连接于该周边电路单元与该记忆核心单元,用以操作于一第三预定电压,其中该第三预定电压是小于1.1V。
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