TWI355590B - Common module for ddrii sdram and ddriii sdram - Google Patents

Common module for ddrii sdram and ddriii sdram Download PDF

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TWI355590B
TWI355590B TW096117224A TW96117224A TWI355590B TW I355590 B TWI355590 B TW I355590B TW 096117224 A TW096117224 A TW 096117224A TW 96117224 A TW96117224 A TW 96117224A TW I355590 B TWI355590 B TW I355590B
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sdram
slot
ddriii
ddrii
mode
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TW096117224A
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Chinese (zh)
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TW200844758A (en
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Chin Hui Chen
Hou Yuan Lin
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Giga Byte Tech Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Description

1355590 第96117224號專利說明書修正本 修正日期：]00年4月1]曰 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種記憶體共用模組，更特別是有關 於一種DDRII SDRAM與DDRIII SDRAM之共用模組。 【先前技術】 隨著高傳輸率與低功率消耗的需求增加，近來發展出 雙倍資料傳輸率III之同步動態隨機存取記憶體（DDRIII φ SDRAJVT)。此外 ’ DDRIII SDRA]V[的電壓從 1-.8V 下降至 了 1.5V ’這意味著内存晶片功耗的降低，以延長應用裝 *. 置，例如及電腦和手機，的續航時間。此外，在晶片封裝、 '' 引腳和信號方面，DDRIII也有了全面的技術改進。 第1圖係表示習知DDRII SDRAM之主機板配置示意 圖。在第1圖中，DDRII SDRAM 11配置在主機板1之 DDRII插槽上。主控制器1〇傳送資料信號DATA、位址 信號ADD '以及控制信號CMD至DDRII SDRAM 11。其 中，主控制器10可以是英特爾（intel)的北橋晶片組或 ® 是超微（AMD)的中央處理單元。參閱第1圖，位址信 號ADD以及控制信號CMD所需之終端電阻Radd及Rcmd 皆是配置在主機板1上；而資料信號DATA所需之終端 電阻Rdata 則是配置於DDRII SDRAM 11内。 第2圖係表示習知DDRIII SDRAM之主機板配置示意 圖。在第2圖中，DDRIII SDRAM 21配置在主機板2之 DDRIII插槽上。主控制器2〇傳送資料信號DATA、位址 信號ADD、以及控制信號CMD至DDRIII SDRAM 21。 其中’主控制器20可以是英特爾的北橋晶片組或是超微 5 1355590 第961]7224號專利說明書修正本 修正曰期：100年4月11日 的中央處理單元。參閱第2圖，資料信號DATA、位址信 號ADD、以及控制信號CMD所需之終端電阻RDATA、 Radd、及Rcmd皆是配置在DDRIII SDRAM 21内。與第1 圖之DDRII SDRAM之主機板1比較起來，位址信號ADD 及控制信號CMD所需之終端電阻Radd及Rcmd從主機板 上移出，而配置於DDRIII SDRAM 21。 如上所述，DDRII SDRAM與DDRIII SDRAM之規格 不同，因此，當使用者欲交替使用DDRII SDRAM與 DDRIII SDRAM時，則需更換兩種不同規格的主機板。 因此，期望提供一種DDRII SDRAM與DDRIII SDRAM的共用模組，讓使用者不需更換主機板而可選擇 性地使用 DDRII SDRAM 或 DDRIII SDRAM。 【發明内容】 本發明提供一種雙倍資料傳輸率II之同步動態隨機 存取記憶體（DDRII SDRAM)與雙倍資料傳輸率III之同 步動態隨機存取記憶體（DDRIII SDRAM)之共用模組， 其適用於電腦系統。此共用模組包括第一匯流排、終端電 路卡、第一插槽、以及第二插槽。第一匯流排傳送複數信 號。終端電路卡具有複數終端電阻。第一插槽配置在共用 模組上且耦接第一匯流排，用以安裝DDRII SDRAM。第 二插槽配置在共用模組上且耦接第一匯流排，用以安裝 DDRIII SDRAM或終端電路卡。其中，當DDRII SDRAM 安裝在第一插槽上時且終端電路卡安裝在第二插槽上。1355590 Patent No. 96171224 Revision of this revision date:] April 1st, 2001] 曰 、, invention description: [Technical Field] The present invention relates to a memory sharing module, and more particularly to a DDRII A common module for SDRAM and DDRIII SDRAM. [Prior Art] With the increasing demand for high transmission rate and low power consumption, a synchronous dynamic random access memory (DDRIII φ SDRAJVT) with double data transfer rate III has recently been developed. In addition, the voltage of 'DDRIII SDRA】V[ drops from 1-.8V to 1.5V, which means that the power consumption of the memory chip is reduced to extend the life of the application, such as computers and mobile phones. In addition, DDRIII has a comprehensive technical improvement in chip packaging, ''pins and signals'). Figure 1 is a schematic diagram showing the configuration of a motherboard of a conventional DDRII SDRAM. In Fig. 1, the DDRII SDRAM 11 is disposed on the DDRII slot of the motherboard 1. The main controller 1 transmits a data signal DATA, an address signal ADD ', and a control signal CMD to the DDRII SDRAM 11. The main controller 10 can be an Intel Northbridge chipset or a Central Processing Unit of Ultra Micro (AMD). Referring to Fig. 1, the termination resistors Radd and Rcmd required for the address signal ADD and the control signal CMD are disposed on the motherboard 1; and the termination resistor Rdata required for the data signal DATA is disposed in the DDRII SDRAM 11. Figure 2 is a schematic diagram showing the configuration of a motherboard of a conventional DDRIII SDRAM. In Fig. 2, the DDRIII SDRAM 21 is disposed on the DDRIII slot of the motherboard 2. The main controller 2 transmits a data signal DATA, an address signal ADD, and a control signal CMD to the DDRIII SDRAM 21. The main controller 20 may be Intel's Northbridge chipset or AMD 5 1355590 961] Patent Specification No. 7224 Amendment Revision: The central processing unit on April 11, 100. Referring to Fig. 2, the termination resistors RDATA, Radd, and Rcmd required for the data signal DATA, the address signal ADD, and the control signal CMD are disposed in the DDRIII SDRAM 21. In comparison with the motherboard 1 of the DDRII SDRAM of Fig. 1, the termination resistors Rdd and Rcmd required for the address signal ADD and the control signal CMD are removed from the motherboard and are disposed in the DDRIII SDRAM 21. As mentioned above, the specifications of DDRII SDRAM are different from those of DDRIII SDRAM. Therefore, when users want to use DDRII SDRAM and DDRIII SDRAM alternately, they need to replace two different specifications of the motherboard. Therefore, it is desirable to provide a shared module of DDRII SDRAM and DDRIII SDRAM, allowing users to selectively use DDRII SDRAM or DDRIII SDRAM without replacing the motherboard. SUMMARY OF THE INVENTION The present invention provides a shared module of a double data transmission rate II synchronous dynamic random access memory (DDRII SDRAM) and a double data transmission rate III synchronous dynamic random access memory (DDRIII SDRAM). It is suitable for computer systems. The common module includes a first bus, a terminal circuit card, a first slot, and a second slot. The first bus transmits a complex signal. The terminal circuit card has a plurality of terminating resistors. The first slot is disposed on the shared module and coupled to the first bus to mount the DDRII SDRAM. The second slot is disposed on the shared module and coupled to the first bus to mount the DDRIII SDRAM or the terminal circuit card. Wherein, when the DDRII SDRAM is mounted on the first slot and the terminal circuit card is mounted on the second slot.

本發明更提出一種雙倍資料傳輸率II之同步動態隨 機存取記憶體（DDRII SDRAM)與雙倍資料傳輸率III 1355590 第96117224號專利說明書修正本 修正日期：100年4月11曰 之同步動態隨機存取記憶體（DDRIII SDRAM )之共用模 組，其適用於電腦系統。此共用模組包括第一匯流排、第 一插槽、第二插槽、複數終端電阻、以及複數開關。第一 匯流排傳送複數信號。第一插槽配置在共用模組上且耦接 第一匯流排，用以在第一模式下安裝DDRII SDRAM。第 二插槽配置在共用模組上且耦接第一匯流排，用以在第二 模式下安裝DDRIII SDRAM。複數開關對應耦接複數終端 電阻與第一匯流排之間。於第一模式時，複數開關導通， 將複數終端電阻對應耦接至第一匯流排。於第二橋式時， 複數開關關閉。 • · 本發明更提出一種雙倍資料傳輸率II之同步動態隨 ·- 機存取記憶體（DDRII SDRAM)與雙倍資料傳輸率III ' 之同步動態隨機存取記憶體（DDRIII SDRAM)之共用模 組，其適用於電腦系統。此共用模組包括第一匯流排、第 _ 一插槽、第二插槽、以及複數終端電阻。第一匯流排傳送 - 複數信號。第一插槽配置在共用模組上且耦接第一匯流 排，用以安裝DDRII SDRAM。第二插槽配置在共用模組 • 上且耦接第一匯流排，用以安裝DDRIII SDRAM。複數終 端電阻則對應耦接第一匯流排。其中，在第一模式下， DDRII SDRAM安裝於該第一插槽；在一第二模式下，該 DDRII SDRAM自該第一插槽移除，且該DDRIII SDRAM 安裝於該第二插槽。 為使本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下。 7 修正曰期_· 100年4月n曰 第96117224號專利說明書修正本 【實施方式】 第一實施例：The present invention further proposes a double data transmission rate II synchronous dynamic random access memory (DDRII SDRAM) and double data transmission rate III 1355590 Patent 96117224 Patent Specification Amendment Revision Date: April 11th, 100th Synchronous Dynamics A shared module of random access memory (DDRIII SDRAM), which is suitable for computer systems. The common module includes a first bus, a first slot, a second slot, a plurality of terminating resistors, and a plurality of switches. The first bus transmits a complex signal. The first slot is disposed on the common module and coupled to the first busbar for installing the DDRII SDRAM in the first mode. The second slot is disposed on the common module and coupled to the first bus bar for mounting the DDRIII SDRAM in the second mode. The plurality of switches are coupled between the plurality of terminal resistors and the first bus bar. In the first mode, the plurality of switches are turned on, and the plurality of terminal resistors are correspondingly coupled to the first bus bar. In the second bridge mode, the complex switch is turned off. • The present invention further proposes a synchronous data sharing rate II synchronous memory with memory access memory (DDRII SDRAM) and double data transfer rate III 'synchronous dynamic random access memory (DDRIII SDRAM) sharing Module, which is suitable for computer systems. The common module includes a first bus, a first slot, a second slot, and a plurality of terminating resistors. The first bus transmits - a complex signal. The first slot is disposed on the common module and coupled to the first bus bar for mounting the DDRII SDRAM. The second slot is disposed on the common module and coupled to the first bus to mount the DDRIII SDRAM. The plurality of terminal resistors are coupled to the first bus bar. Wherein, in the first mode, the DDRII SDRAM is mounted in the first slot; in a second mode, the DDRII SDRAM is removed from the first slot, and the DDRIII SDRAM is mounted in the second slot. The above described objects, features, and advantages of the invention will be apparent from the description and appended claims 7 Correction period _· 100 years April n曰 No. 96171224 Patent specification revisions [Embodiment] First embodiment:

第3a圖係表示本發明第一實施例之雙倍資料傳 資態j财取記憶體（DDRI1 SDRAM)與雙倍 snR J 之同步動態隨機存取記憶體（DDRIII 之共賴組，其適用於電腦系統。參閱第3a圖， :用換、、且3包括第一匯流排3〇、至少一第一插槽31、第 二t槽32、第二插槽33、以及終端電路卡％ 路卡34並非固定於第％圖中的位置，僅：表 不其包含於共用模組3。第一 $笼— 丘用槿細1 ^ 至第二插槽31-33係配置在 ^叫^、、，― 二耦接第一匯流排30。電腦系統之主控 二於^在第三插槽33上。在一些實施例中，主控制 H 複數信號至第—匯流排3G，且在實㈣用上， 二·]态35可以超微（AMD )的中央處理單元來實現。 ^另一些實施例中，參閱第3b圖，共用模組3更包括晶 =組％，其耦接主控制器35，用將來自主控制器％之複 虎轉送至第-匯流排3〇。根據第3b圖之實施例，在 ^際的應用上，主控制器35可以英特爾（intd)的中央 處理單^來實現’而晶片組36則以北橋晶片組來實現。 =控W器35提供至第-匯流排3Q之複數信號包括複數資 枓信號、複數位址信號、以及複數控制信號。在下列之說 2。中將以資料#说D0-D2、位址信號Α〇·Α2、以及控制 "is 虎 C0-C2 為例。FIG. 3a is a diagram showing a double-data-sourced memory (DDRI1 SDRAM) and a double-snR-J synchronous dynamic random access memory (DDRIII) according to the first embodiment of the present invention, which is applicable to Computer system. Referring to Fig. 3a, : for replacement, and 3 includes first bus bar 3〇, at least one first slot 31, second t slot 32, second slot 33, and terminal circuit card % road card 34 is not fixed at the position in the % map, only: the table is not included in the common module 3. The first $cage - the mound is fine 1 ^ to the second slot 31-33 is configured in ^, ^, 2 is coupled to the first bus 30. The main control of the computer system is in the third slot 33. In some embodiments, the main control H complex signal to the first bus 3G, and in the real (four) The second state 35 can be implemented by a central processing unit of AMD. In other embodiments, referring to FIG. 3b, the common module 3 further includes a crystal=group%, which is coupled to the main controller 35. Transferring to the first bus bar 3〇 with the future self-controller%. According to the embodiment of FIG. 3b, in the application of the main controller, the main controller 35 can The central processing unit of the int is implemented and the chip group 36 is implemented by the north bridge chip set. The complex signal provided by the controller 35 to the first bus bar 3Q includes a complex signal and a complex address signal. And the complex control signal. In the following 2, the Chinese will use the data # said D0-D2, the address signal Α〇·Α2, and the control "is Tiger C0-C2 as an example.

一共用杈組3具有兩種模式，一種是支援DDRII SDRAM 的杈式（之後稱第一模式）；另一種則是支援DDRm SDRAM的模式（之後稱第二模式）。 1355590 第961]7224號專利說明書修正本 修正日期：100年4月11曰 第4a圖係表示於第一模式下共用模組3之配置示意 圖。參閱第4a圖，在第一模式下，DDRII SDRAM 40安 裝在第一插槽31上，且終端電路卡34安裝在第二插槽 32上。參閱第4b圖，終端電路卡34具有複數終端電阻R， 且這些終端電阻R與位址信號A0-A2以及控制信號 C0-C2阻抗匹配。舉例來說，終端電阻RA0-RA2分另丨J與 位址信號A0-A2阻抗匹配，且終端電阻RC0-RC2分別與 控制信號C0-C2阻抗匹配。與資料信號D0-D2阻抗匹配 之終端電阻則内置在DDRII SDRAM 40中。當終端電路 ® 卡34安裝在第二插槽32上時，終端電阻RA0-RA2及 • - RC0-RC2貝|J對應耦接第一匯流排30，使得終端電阻 ' RA0-RA2與分別耦合位址信號A0-A2，且終端電阻 RC0-RC2分另丨J耦合控制信號C0-C2 〇 第5圖係表示於第二模式下共用模組3之配置示意 - 圖。參閱第5圖，在第二模式下，將DDRII SDRAM 40 - 自第一插槽31移除，且將終端電路卡34自第二插槽32 移除，而將DDRIII SDRAM 50安裝在第二插槽32上。由 •於根據 DDRIII SDRAM 之規格，DDRIII SDRAM 5〇 内置 資料信號D0-D2、位址信號A0-A2、以及控制信號C0-C2 所需之終端電阻，因此不再需要安裝終端電路卡34。 根據本發明之第一實施例，如上所述，當使用者欲交 替使用DDRII SDRAM與DDRIII SDRAM B寺，在同一模 組上，可選擇性地安裝DDRII SDRAM 40與終端電路卡 34之組合或DDRIII SDRAM 50，因此，使用者不需換兩 種不同規格的模組。 ，在第一實施例中，係以一個第一插槽31為例。然而， 9 1355590 第961〗7224號專利說明書修正本 根據應用所需，共用模組 31。當在第一模式時，每 SDRAM。A shared group 3 has two modes, one is a mode that supports DDRII SDRAM (hereinafter referred to as a first mode); the other is a mode that supports DDRm SDRAM (hereinafter referred to as a second mode). 1355590 961] No. 7224 Patent Specification Revision Date: April 11th, 100th Figure 4a shows a schematic diagram of the configuration of the shared module 3 in the first mode. Referring to Fig. 4a, in the first mode, the DDRII SDRAM 40 is mounted on the first slot 31, and the termination circuit card 34 is mounted on the second slot 32. Referring to Figure 4b, the termination circuit card 34 has a plurality of termination resistors R, and these termination resistors R are impedance matched to the address signals A0-A2 and the control signals C0-C2. For example, the termination resistors RA0-RA2 are separately matched to the address signals A0-A2 and the termination resistors RC0-RC2 are impedance matched to the control signals C0-C2, respectively. The termination resistors that match the impedance of the data signals D0-D2 are built into the DDRII SDRAM 40. When the terminal circuit® card 34 is mounted on the second slot 32, the terminating resistors RA0-RA2 and _RC0-RC2 are coupled to the first busbar 30 such that the terminating resistors 'RA0-RA2 and the respective coupling bits are respectively coupled. The address signals A0-A2, and the termination resistors RC0-RC2 are separated from the J-coupling control signals C0-C2. FIG. 5 is a schematic diagram showing the configuration of the shared module 3 in the second mode. Referring to FIG. 5, in the second mode, the DDRII SDRAM 40 - is removed from the first slot 31, and the terminal circuit card 34 is removed from the second slot 32, and the DDRIII SDRAM 50 is mounted in the second slot. On the slot 32. According to the specifications of the DDRIII SDRAM, the DDRIII SDRAM 5 内置 has built-in data signals D0-D2, address signals A0-A2, and terminal resistances required for the control signals C0-C2, so that it is no longer necessary to install the terminal circuit card 34. According to the first embodiment of the present invention, as described above, when the user wants to alternately use the DDRII SDRAM and the DDRIII SDRAM B Temple, the combination of the DDRII SDRAM 40 and the terminal circuit card 34 or the DDRIII can be selectively mounted on the same module. SDRAM 50, therefore, the user does not need to change the modules of two different specifications. In the first embodiment, a first slot 31 is taken as an example. However, the amendment to the patent specification of 9 1355590, No. 961, No. 7224, shares the module 31 as required by the application. When in the first mode, every SDRAM.

修正曰期：100年4月η曰 可包括複數串接之第一插槽 第一插槽安裝一個DDRII 第^實施例： 第6a圖係表示本發明第—麻 與咖m SDRAM之丑用^ 7 =之MRI1 閱第6a圖，Γ用权 其適用於電腦系統。參 H , 包括第一匯流排6〇、至少-第一 插槽6卜第二插槽62、第三插槽 ：Correction period: 100 years in April η曰 can include the first slot of the first serial connection. The first slot is installed with a DDRII. Embodiment: Figure 6a shows the ugly use of the invention - the hemp and the m SDRAM ^ 7 = MRI1 Read Figure 6a, which is applicable to computer systems. The reference H includes a first busbar 6〇, at least a first slot 6b, a second slot 62, and a third slot:

複數開關SW、以及開關控制器6 =電阻R 61_63係配置在丘 至第二插槽 聪备姑夕核 且轉接第一匯流排60。電 〇w ^ 女裝在弟二插槽〇上。複數開關 輕接於^數終端電阻R與第-匯流排60之間。 士在-些實施例中，主控制器65輸出複數信號至第一 匯&排6〇’且在實際應用上，主控制器65可以超微（AMD) 的中央處理單元來實現。在另一些實施例中，，參閱第6b 囷/、用模組6更包括晶片組66，其轉接主控制器65， 用將來自主控制器65之複數信號轉送至第一匯流排60。 根據第6b圖之實施例，在實際的應用上，主控制器65可 以英特爾（intel)的中央處理單元來實現，而晶片組66 則以北橋晶片組來實現。 主控制器65提供至第一匯流排60之複數信號包括複 數資料信號'複數位址信號、以及複數控制信號。在下列 之說明中’將以資料信號D0-D2、位址信號A0-A2、以及 控制彳&號C0-C2為例。 複數終端電阻r與位址信號AO-A2及控制信號C0-C2 阻抗匹配。舉例來說，終端電阻RA0-RA2分別與位址信 1355590 修正日期：100年4月11日 第96117224號專利說明書修正本 號A0-A2阻抗匹配，且終端電阻RC〇_RC2分別與控制信 號C0-C2阻抗匹配。複數開關sw包括開關SWA〇_SWA2 以及開關SWC0-SWC2。開關SWA0-SWA2分別耦接於終 端電阻RA0-RA2與位址信號a〇-A2之間，且開關 SWC0-SWC2分別耦接於終端電阻RC〇_RC2與控制信號 C0-C2之間。The plurality of switches SW and the switch controller 6 = resistor R 61_63 are arranged in the second to the second slot and are switched to the first bus 60. Electric 〇 w ^ women in the second slot of the brother. The plurality of switches are lightly connected between the terminal resistor R and the first bus bar 60. In some embodiments, the main controller 65 outputs a complex signal to the first sink & row 6 〇 ' and in practical applications, the main controller 65 can be implemented by a central processing unit of the AMD. In other embodiments, referring to FIG. 6b, the module 6 further includes a chipset 66 that is transferred to the main controller 65 and forwarded to the first busbar 60 by a plurality of signals from the future master controller 65. According to the embodiment of Fig. 6b, in practical applications, the main controller 65 can be implemented in an Intel central processing unit, and the chip group 66 is implemented in a Northbridge chipset. The complex signals provided by the main controller 65 to the first bus 60 include a complex data signal 'complex address signal' and a complex control signal. In the following description, the data signals D0-D2, the address signals A0-A2, and the control 彳& numbers C0-C2 will be taken as an example. The complex termination resistor r is matched to the address signal AO-A2 and the control signal C0-C2. For example, the terminating resistors RA0-RA2 are respectively matched with the address letter 1355590, the date of correction: the correction of the A0-A2 of the patent specification No. 96171224 of April 11, 100, and the terminal resistance RC〇_RC2 and the control signal C0, respectively. -C2 impedance matching. The complex switch sw includes a switch SWA〇_SWA2 and switches SWC0-SWC2. The switches SWA0-SWA2 are respectively coupled between the terminal resistors RA0-RA2 and the address signals a〇-A2, and the switches SWC0-SWC2 are respectively coupled between the termination resistors RC〇_RC2 and the control signals C0-C2.

共用模組6具有兩種模式，—種是支援ddrii SDRAM 的模式（之後稱第一模式）；另一種則是支援ddriii SDRAM的模式（之後稱第二模式）。 第7圖係表示於第一模式下共用模組6之配置示意 ·-圖。參閱第7圖，在第一模式下，DDRII SDRAM 70安裝 --在第一插槽61上，且開關控制器64導通開關 SWA0-SWA2以及開關SWC0_SWC2，使得終端電阻 RA0-RA2以及終端電阻RC0-RC2對應柄接第一匯流排。 ' 因此，終端電阻RA0-RA2分別耦合位址信號A0-A2，且 終端電阻RC0-RC2分別耦合控制信號C0-C2。此外，與 資料信號D0-D2阻抗匹配之終端電阻則内置在DDRII SDRAM 70 中。 第8圖係表示於第二模式下共用模組6之配置示意 圖。參閱第8圖，在第二模式下，將DDRII SDRAM 70 自第一插槽61移除，且將DDRIII SDRAM 80安裝在第二 插槽62上。此外，開關控制器64關閉開關SWAO-SWA2 以及開關SWC0-SWC2。由於根據DDRIII SDRAM之規 格，DDRIII SDRAM 80内置資料信號D0-D2、位址信號 A0-A2、以及控制信號C0-C2所需之終端電阻，因此不再 需要將開關SWA0-SWA2以及開關SWC0-SWC2耦接於第 11 1355590 第96117224號專利說明書修正本 修正日期：100年4月11日 一匯流排60。 根據本發明之第二實施例，如上所述，當使用者欲交 替使用DDRII SDRAM與DDRIII SDRAM時，在同一模 組上，可選擇性導通或關閉複數終端電阻R與第一匯流排 60間的複數開關SW，因此，使用者不需換兩種不同規格 的模組。 在第二實施例中，係以一個第一插槽61為例。然而， 根據應用所需，共用模組6可包括複數串接之第一插槽 61。當在第一模式時，每一第一插槽安裝一個DDRII SDRAM。 第三實施例： 第9a圖係表示本發明第三實施例之DDRII SDRAM 與DDRIII SDRAM之共用模組，其適用於電腦系統。參 閱第9a圖，共用模組9包括第一匯流排90、至少一第一 插槽91、第二插槽92、第三插槽93、以及複數終端電阻 R。其中，第一至第三插槽91-93係配置在共用模組9上， 且耦接第一匯流排90。電腦系統之主控制器94安裝在第 三插槽93上。複數終端電阻R對應耦接第一匯流排90。 在一些實施例中，主控制器94輸出複數信號至第一 匯流排90,且在實際應用上，主控制器94可以超微（AMD) 的中央處理單元來實現。在另一些實施例中，參閱第9b 圖，共用模組9更包括晶片組95，其耦接主控制器94， 用將來自主控制器94之複數信號轉送至第一匯流排90。 根據第9b圖之實施例，在實際的應用上，主控制器94可 以英特爾（intel )的中央處理單元來實現，而晶片組95 則以北橋晶片組來實現。 12 1355590 ' 第96] 17224號專利說明書修正本 修正日期：1 〇〇年4月11曰 主控制器94提供至第一匯流排90之複數信號包括複 數資料信號、複數位址信號、以及複數控制信號。在下列 之說明中，將以資料信號D0-D2、位址信號A0-A2、以及 控制信號C0_C2為例。 複數終端電阻R對應耦接第一匯流排90，且與位址 信號A0-A2及控制信號C0-C2耦合。舉例來說，終端電 阻RA0-RA2分別耦合位址信號A0-A2，且終端電阻 RC0-RC2分別耦合控制信號C0-C2。 共用模組90具有兩種模式，一種是支援DDRII ® SDRAM的模式（之後稱第一模式）；另一種則是支援 • - DDRIII SDRAM的模式（之後稱第二模式）。 .. 第10圖係表示於第一模式下共用模組9之配置示意 圖。參閱第10圖，在第一模式下，DDRII SDRAM 100安 裝在第一插槽91。與資料信號D0-D2阻抗匹配之終端電 - 阻則内置在DDRII SDRAM 100中。因此，資料信號 . D0-D2、位址信號A0-A2、以及控制信號C0-C2皆具有對 應之終端電阻。 • 第11圖係表示於第二模式下共用模組9之配置示意 圖。參閱第11圖，在第二模式下，將DDRII SDRAM 100 自第一插槽91移除，且將DDRIII SDRAM 110安裝在第 二插槽9 2上。 在本發明之第三實施例中，每一終端電阻R介於〇歐 姆至100歐姆之間。在一些實施例中，每一終端電阻R 介於10歐姆至100歐姆之間。 根據本發明之第三實施例，如上所述，當使用者欲交 替使用DDRII SDRAM與DDRIII SDRAM時，僅需在同 13 1355590 第961Π224號專利說明書修正本 修正日期：〗〇〇年4月11曰 一模組上，將選擇性地安裝DDRII SDRAM 100與DDRIII SDRAM 110，因此，使用者不需換兩種不同規格的模組。 在第三實施例中，係以一個第一插槽91為例。然而， 根據應用所需，共用模組9可包括複數串接之第一插槽 91。當在第一模式時，每一第一插槽安裝一個DDRII SDRAM。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍，任何所屬技術領域令具有通常知識者，在 不脫離本發明之精神和範圍内，當可做些許的更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 14 1355590 第96Π 7224號專利說明書修正本 修正日期：]00年4月11曰 【圖式簡單說明】 - 第1圖表示習知DDRII SDRAM之主機板配置示意圖。 第2圖表示習知DDRIII SDRAM之主機板配置示意圖。 第3a及3b表示本發明第一實施例之DDRII SDRAM 與DDRIII SDRAM之共用模組。 第4a圖表示根據第一實施例，於第一模式下共用模組 之配置示意圖。 第4b圖表示根據第一實施例，終端電阻卡之示意圖。 第5圖表示根據第一實施例，於第二模式下共用模組_ •之配置示意圖。The shared module 6 has two modes, a mode supporting ddrii SDRAM (hereinafter referred to as a first mode), and a mode supporting ddriii SDRAM (hereinafter referred to as a second mode). Fig. 7 is a view showing the arrangement of the common module 6 in the first mode. Referring to FIG. 7, in the first mode, the DDRII SDRAM 70 is mounted-on the first slot 61, and the switch controller 64 turns on the switches SWA0-SWA2 and the switches SWC0_SWC2, so that the termination resistors RA0-RA2 and the termination resistor RC0- The RC2 corresponding handle is connected to the first bus bar. Therefore, the termination resistors RA0-RA2 are coupled to the address signals A0-A2, respectively, and the termination resistors RC0-RC2 are coupled to the control signals C0-C2, respectively. In addition, the termination resistors that match the impedance of the data signals D0-D2 are built into the DDRII SDRAM 70. Fig. 8 is a view showing the configuration of the shared module 6 in the second mode. Referring to Fig. 8, in the second mode, the DDRII SDRAM 70 is removed from the first slot 61, and the DDRIII SDRAM 80 is mounted on the second slot 62. Further, the switch controller 64 turns off the switches SWAO-SWA2 and the switches SWC0-SWC2. Since the DDRIII SDRAM 80 has built-in data signals D0-D2, address signals A0-A2, and terminal resistances required for control signals C0-C2 according to the specifications of the DDRIII SDRAM, the switches SWA0-SWA2 and the switches SWC0-SWC2 are no longer required. Coupling with the patent specification No. 11 1355590 No. 96,172,224, this revision date is: April 14, 100, a busbar 60. According to the second embodiment of the present invention, as described above, when the user wants to alternately use the DDRII SDRAM and the DDRIII SDRAM, the same terminal can be selectively turned on or off between the plurality of terminal resistors R and the first bus bar 60. The plurality of switches SW, therefore, the user does not need to change the modules of two different specifications. In the second embodiment, a first slot 61 is taken as an example. However, depending on the application, the common module 6 can include a plurality of first slots 61 that are serially connected. When in the first mode, one DDRII SDRAM is mounted in each first slot. Third Embodiment: Fig. 9a shows a shared module of a DDRII SDRAM and a DDRIII SDRAM according to a third embodiment of the present invention, which is suitable for a computer system. Referring to Figure 9a, the common module 9 includes a first bus bar 90, at least a first slot 91, a second slot 92, a third slot 93, and a plurality of terminating resistors R. The first to third slots 91-93 are disposed on the common module 9 and coupled to the first bus bar 90. The main controller 94 of the computer system is mounted on the third slot 93. The plurality of terminal resistors R are coupled to the first bus bar 90. In some embodiments, main controller 94 outputs a complex signal to first busbar 90, and in practical applications, main controller 94 can be implemented as a central processing unit of the AMD. In other embodiments, referring to FIG. 9b, the common module 9 further includes a chip set 95 coupled to the main controller 94 and forwarded to the first bus bar 90 by a complex signal of the future autonomic controller 94. According to the embodiment of Figure 9b, in practical applications, the main controller 94 can be implemented in an Intel central processing unit, while the chip set 95 is implemented in a Northbridge chipset. 12 1355590 'No. 96】 Patent Specification No. 17224 Amendment Revision Date: 1 April 11th, the complex signal provided by the main controller 94 to the first bus 90 includes a complex data signal, a complex address signal, and a complex control signal. In the following description, the data signals D0-D2, the address signals A0-A2, and the control signal C0_C2 will be taken as an example. The plurality of terminating resistors R are coupled to the first bus bar 90 and coupled to the address signals A0-A2 and the control signals C0-C2. For example, terminal resistors RA0-RA2 are coupled to address signals A0-A2, respectively, and termination resistors RC0-RC2 are coupled to control signals C0-C2, respectively. The shared module 90 has two modes, one is a mode supporting DDRII ® SDRAM (hereinafter referred to as a first mode); the other is a mode supporting - DDRIII SDRAM (hereinafter referred to as a second mode). Fig. 10 is a schematic view showing the configuration of the shared module 9 in the first mode. Referring to Fig. 10, in the first mode, the DDRII SDRAM 100 is mounted in the first slot 91. The terminal power-resistance that matches the impedance of the data signal D0-D2 is built into the DDRII SDRAM 100. Therefore, the data signals D0-D2, the address signals A0-A2, and the control signals C0-C2 all have corresponding termination resistors. • Fig. 11 is a view showing the configuration of the shared module 9 in the second mode. Referring to Fig. 11, in the second mode, the DDRII SDRAM 100 is removed from the first slot 91, and the DDRIII SDRAM 110 is mounted on the second slot 92. In the third embodiment of the invention, each of the terminating resistors R is between 〇 ohm and 100 ohms. In some embodiments, each termination resistor R is between 10 ohms and 100 ohms. According to the third embodiment of the present invention, as described above, when the user wants to alternately use the DDRII SDRAM and the DDRIII SDRAM, it is only necessary to amend the revised date in the same patent specification as 13 1355590 No. 961Π224: 4April 11曰On one module, DDRII SDRAM 100 and DDRIII SDRAM 110 will be selectively installed, so that the user does not need to change modules of two different specifications. In the third embodiment, a first slot 91 is taken as an example. However, the shared module 9 can include a plurality of first slots 91 in series depending on the application. When in the first mode, one DDRII SDRAM is mounted in each first slot. The present invention has been disclosed in the above preferred embodiments. However, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make a few modifications and changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims. 14 1355590 Rev. 96Π 7224 Patent Specification Amendment Revision Date: April 11, 2011 [Simplified Schematic] - Figure 1 shows the schematic diagram of the motherboard configuration of the conventional DDRII SDRAM. Figure 2 is a schematic diagram showing the configuration of a motherboard of a conventional DDRIII SDRAM. 3a and 3b show a shared module of the DDRII SDRAM and the DDRIII SDRAM of the first embodiment of the present invention. Fig. 4a is a diagram showing the configuration of a shared module in the first mode according to the first embodiment. Fig. 4b is a view showing a terminal resistance card according to the first embodiment. Fig. 5 is a view showing the configuration of the shared module in the second mode according to the first embodiment.

-- 第6a及6b表示本發明第二實施例之DDRII SDRAM -、 與DDRIII SDRAM之共用模組。 ' 第7圖表示根據第二實施例，於第一模式下共用模組 之配置示意圖。 ' 第8圖表示根據第二實施例，於第二模式下共用模組 、 之配置示意圖。 第9a及9b表示本發明第三實施例之DDRII SDRAM • 與DDRIII SDRAM之共用模組。 第10圖表示根據第三實施例，於第一模式下共用模組 之配置示意圖。 第11圖表示根據第三實施例，於第二模式下共用模組 之配置示意圖。 【主要元件符號說明】 1〜主機板； 10〜主控制器； 11〜DDRII SDRAM ; 2〜主機板; 20〜主控制器； 21〜DDRIII SDRAM ; 1355590 第96117224號專利說明書修正本-- 6a and 6b show a DDRII SDRAM - a shared module with a DDRIII SDRAM according to a second embodiment of the present invention. Fig. 7 is a view showing the configuration of a shared module in the first mode according to the second embodiment. Fig. 8 is a view showing the configuration of a shared module in the second mode according to the second embodiment. 9a and 9b show a DDRII SDRAM of the third embodiment of the present invention and a shared module with DDRIII SDRAM. Fig. 10 is a view showing the configuration of a shared module in the first mode according to the third embodiment. Fig. 11 is a view showing the configuration of a shared module in the second mode according to the third embodiment. [Main component symbol description] 1~ motherboard; 10~ main controller; 11~DDRII SDRAM; 2~ motherboard; 20~ main controller; 21~DDRIII SDRAM; 1355590 Patent No. 96171224

Radd、Rcmd、Rdata' 3〜共用模組； 31〜第一插槽 33〜第三插槽 35〜主控制器 40 〜DDRII SDRAM AO-A2〜位址信號； 修正日期：100年4月11曰 •終端電阻； 3〇〜第一匯流排； 32〜第二插槽； 34〜終端電路卡， 36〜晶片組； 50〜DDRIII SDRAM ; C0-C2〜控制信號； D0-D2〜資料信號； R、RA0-RA2、RC0-RC2 〜終端電阻； 6〜共用模組； 61〜第一插槽； 63〜第三插槽； SW〜複數開關； 65〜主控制器； 70 〜DDRII SDRAM ; A0-A2〜位址信號； 60〜第一匯流排； 62〜第二插槽； R〜終端電阻； 64〜開關控制器； 66〜晶片組； 80 〜DDRIII SDRAM ; C0-C2〜控制信號； D0-D2〜資料信號； R、RA0-RA2、RC0-RC2〜終端電阻； SW、SWA0-SWA2、SWC0-SWC2〜開關； 9〜共用模組； 91〜第一插槽； 93〜第三插槽； 95〜晶片組； 110〜DDRIII SDRAM C0-C2〜控制信號； 90〜第一匯流排； 92〜第二插槽； 94〜主控制器； 100 〜DDRII SDRAM ; A0-A2〜位址信號； D0-D2〜資料信號； R、RA0-RA2、RC0-RC2 〜终端電阻 16Radd, Rcmd, Rdata' 3 ~ shared module; 31 ~ first slot 33 ~ third slot 35 ~ main controller 40 ~ DDRII SDRAM AO-A2 ~ address signal; Correction date: 100 years April 11曰• Terminating resistor; 3〇~first busbar; 32~2nd slot; 34~terminal circuit card, 36~ chipset; 50~DDRIII SDRAM; C0-C2~ control signal; D0-D2~ data signal; , RA0-RA2, RC0-RC2 ~ terminating resistor; 6 ~ shared module; 61 ~ first slot; 63 ~ third slot; SW ~ complex switch; 65 ~ main controller; 70 ~ DDRII SDRAM; A0- A2 ~ address signal; 60 ~ first bus; 62 ~ second slot; R ~ termination resistor; 64 ~ switch controller; 66 ~ chipset; 80 ~ DDRIII SDRAM; C0-C2 ~ control signal; D0- D2 ~ data signal; R, RA0-RA2, RC0-RC2 ~ terminal resistance; SW, SWA0-SWA2, SWC0-SWC2 ~ switch; 9 ~ shared module; 91 ~ first slot; 93 ~ third slot; 95~ chipset; 110~DDRIII SDRAM C0-C2~ control signal; 90~first busbar; 92~second slot; 94~ main controller; 100~DDRII SDRAM; A0 -A2~ address signal; D0-D2~ data signal; R, RA0-RA2, RC0-RC2~ terminating resistor 16

Claims (1)

13^55590 第96117224號申請專利範圍修正本 修正日期：100年10月5日 十、申請專利範圍： • 一種雙倍資料傳輸率II之同步動態隨機存取記憶體 (DDRII SDRAM)與雙倍資料傳輸率III之同步動態隨機 存取記憶體（DDRIII SDRAM )之共用模組，適用於一電 腦系統且操作在一第一模式或一第二模式，包括： 一第一匯流排’用以傳送複數信號； 一終端電路卡’具有複數終端電阻； 一第一插槽’配置在該共用模組上，且耦接該第一匯 $ 流排；以及 一第一插槽，配置在該共用模組上，且輕接該第一匯 •- 流排，； 其中’在該第—模式下，該DDRII SDRAM安裝在該 第一插槽上且該終端電路卡安裝在該第二插槽上；以及 其中，在該第二模式下，該DDRII SDRAM自該第-•插槽移除’該終端電路卡自該第二插槽移除，且DDRm -SDRAM安裝在該第二播槽上。 2·如申明專利範圍第1項所述之DDRII SDRAM與 DDRIII RAM之共用模組，更包括一第三插槽，配置在 該共用权組上，用以安裝該電腦系統之-主控制H，其 中’該主控制器提供該等信號至該第—匯流排。 3.如申明專利|巳圍第2項所述之DDRn sdram與 DDRm SDRAM之共用模址，更包括一晶片組，輕接該主 控制益，用;以將該等信號轉送至該第-匯流排。 4_如申请專利範圍第1項所述之DDRII SDRAM與 DDRIII SDRAM之共用模組，其中，該等信號包括複數資 料U虎複數位址號、以及複數控制信號，且該等終端 17 1355590 第96117224號申請專利範圍修正本 修正日期：100年1〇月5日 電阻包括複數第一終端電阻與複數第二終端電阻，該等第 一終端電阻與該等位址信號相匹配，該等第二終端電阻與 該等控制信號相匹配。 5·如申請專利範圍第1項所述之DDRII SDRAM與 DDRIII SDRAM之共用模組，其中，該等終端電阻對應該 第一匯流排。 6.—種雙倍資料傳輸率II之同步動態隨機存取記憶體 (DDRII SDRAM )與雙倍資料傳輸率III之同步動態隨機 存取記憶體（DDRIII SDRAM )之共用模組，適用於一電 腦系統，包括： 一第一匯流排，用以傳送複數信號； 一第一插槽，配置在該共用模組上，且耦接該第一匯 流排，用以在一第一模式下安裝該DDRII SDRAM ; 一第二插槽，配置在該共用模組上，且耦接該第一匯 流排，用以在一第二模式下安裝該DDRIII SDRAM ; 複數終端電阻；以及 複數開關，對應耦接該等終端電阻與該第一匯流排之 間； 其中，於該第一模式時，該等開關導通，將該等終端 電阻對應耦接至該第一匯流排； 其中，於該第二模式時，該等開關關閉； 其中，在該第一模式下，該DDRII SDRAM安裝在該 第一插槽上且該DDRIII SDRAM非安裝在該第二插槽；以 及 其中，在該第二模式下，該DDRII SDRAM自該第一 插槽移除，且DDRIII SDRAM安裝在該第二插槽上。 18 1355590 修正日期：1〇〇年10月5日 第96117224號申請專利範圍修正本 7. 如申請專利範圍第6項所述之DDRII SDRAM與 DDRIII SDRAM之共用模組，更包括一第三插槽，配置在 該共用模組上，用以安裝該電腦系統之一主控制器，其 中，該主控制器提供該等信號至該第一匯流排。 8. 如申請專利範圍第7項所述之DDRII SDRAM與 DDRIII SDRAM之共用模組，更包括一晶片組，麵接該主 控制器’用以將該等信號轉送至該第一匯流排。 9. 如申請專利範圍第6項所述之DDRII SDRAM與 φ DDRIII SDRAM之共用模組，其中，該等信號包括複數資 料信號、複數位址信號、以及複數控制信號，且複數終端 :_ 電阻包括複數第一終端電阻複數第二終端電阻，該等第一 終端電阻與該等位址信號相匹配，該等第二終端電阻與該 等控制信號相匹配。 10.—種雙倍資料傳輸率II之同步動態隨機存取記憶 體（DDRII SDRAM)與雙倍資料傳輸率III之同步動態隨 機存取記憶體（DDRIII SDRAM )之共用模組，適用於一 電腦系統且操作在一第一模式或一第二模式，包括： 一第一匯流排，用以傳送複數信號； 一第一插槽，配置在該共用模組上，且耦接該第一匯 流排，用以在該第一模式下安裝該DDRII SDRAM ; 一第二插槽，配置在該共用模組上，且耦I接該第一匯 流排，用以在該第二模式下安裝該DDRIII SDRAM ;以及 複數終端電阻，對應耦接該第一匯流排； 其中，每一該終端電阻介於0歐姆至100歐姆之間； 其中，在該第一模式下，該DDRII SDRAM安裝在該 第一插槽上且該DDRIII SDRAM非安裝在該第二插槽；以 19 1355590 第96117224號申請專利範圍修正本 修正曰期：100年10月5日 及 其中，在該第二模式下，該DDRII SDRAM自該第一 插槽移除，且DDRIII SDRAM安裝在該第二插槽上。 11. 如申請專利範圍第10項所述之DDRII SDRAM與 DDRIII SDRAM之共用模組，更包括一第三插槽，配置在 該共用模組上，用以安裝該電腦系統之一主控制器配置， 其中，該主控制器提供該等信號至該第一匯流排。 12. 如申請專利範圍第11項所述之DDRII SDRAM與 DDRIII SDRAM之共用模組，更包括一晶片組，輕接該主 控制器’用以將該等信號轉送至該第一，匯流排。 13. 如申請專利範圍第1〇項所述之DDRII SDRAM與 DDRIII SDRAM之共用模組，其中，該等信號¥包-括複數資 料信號、’·複數位址信·號、以及複數·控制信號，且:複數終端 »4»· •令. - · 電阻包括複數第一終端電阻複數第二終端電阻，該等第一 終端電阻耦合該等位址信號，該等第二終端電阻耦合該等 控制信號。 14. 如申請專利範圍第1〇項所述之DDRII SDRAM與 DDRIII SDRAM之共用模組，其中，每一該終端電阻介於 10歐姆至100歐姆之間。 2013^55590 No. 96117224 Application for Patent Revision Amendment Date: October 5, 100. Patent scope: • A double data rate II synchronous dynamic random access memory (DDRII SDRAM) and double data A shared module of the synchronous dynamic random access memory (DDRIII SDRAM) of the transmission rate III is applicable to a computer system and operates in a first mode or a second mode, including: a first bus bar 'for transmitting a plurality of numbers a terminal circuit card having a plurality of terminal resistors; a first slot configured on the common module and coupled to the first stream; and a first slot disposed in the common module Up, and lightly connecting the first sink-stream, wherein 'in the first mode, the DDRII SDRAM is mounted on the first slot and the terminal circuit card is mounted on the second slot; Wherein, in the second mode, the DDRII SDRAM is removed from the first-slot, the terminal circuit card is removed from the second slot, and the DDRm-SDRAM is mounted on the second slot. 2. The shared module of the DDRII SDRAM and the DDRIII RAM described in the first paragraph of the patent scope further includes a third slot disposed on the sharing right group for installing the main control H of the computer system. Where the master controller provides the signals to the first bus. 3. For example, the shared phantom of the DDRn sdram and the DDRm SDRAM described in item 2 of the claim, further includes a chip set, which is connected to the main control, for transferring the signals to the first-convection row. 4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ No. Patent Application Range Amendment Revision Date: 100 years 1 month 5th resistor includes a plurality of first terminating resistors and a plurality of second terminating resistors, the first terminating resistors matching the address signals, the second terminals The resistance matches the control signals. 5. The shared module of the DDRII SDRAM and the DDRIII SDRAM described in claim 1 wherein the termination resistors correspond to the first busbar. 6. A shared module with double data transfer rate II synchronous dynamic random access memory (DDRII SDRAM) and double data transfer rate III synchronous dynamic random access memory (DDRIII SDRAM), suitable for one computer The system includes: a first bus bar for transmitting a complex signal; a first slot disposed on the common module and coupled to the first bus bar for installing the DDR II in a first mode a second slot disposed on the common module and coupled to the first bus bar for mounting the DDRIII SDRAM in a second mode; a plurality of termination resistors; and a plurality of switches correspondingly coupled to the Between the terminal resistance and the first busbar; wherein, in the first mode, the switches are turned on, and the terminal resistors are correspondingly coupled to the first busbar; wherein, in the second mode, The switches are turned off; wherein, in the first mode, the DDRII SDRAM is mounted on the first slot and the DDRIII SDRAM is not mounted in the second slot; and wherein, in the second mode, the DDRII SDRAM since the first The slot is removed and the DDRIII SDRAM is mounted on the second slot. 18 1355590 Amendment date: October 5, 2010, No. 96171224, the scope of application for patent modification 7. The shared module of DDRII SDRAM and DDRIII SDRAM as described in claim 6 of the patent application, including a third slot And configured on the shared module to install one of the main controllers of the computer system, wherein the main controller provides the signals to the first bus. 8. The shared module of the DDRII SDRAM and the DDRIII SDRAM described in claim 7 further includes a chipset that is coupled to the main controller for transferring the signals to the first bus. 9. The shared module of DDRII SDRAM and φ DDRIII SDRAM as claimed in claim 6, wherein the signals comprise a plurality of data signals, a complex address signal, and a plurality of control signals, and the plurality of terminals: _ resistors include The plurality of first termination resistors have a plurality of second termination resistors, the first termination resistors are matched to the address signals, and the second termination resistors are matched to the control signals. 10. A shared module with double data rate II synchronous dynamic random access memory (DDRII SDRAM) and double data rate III synchronous dynamic random access memory (DDRIII SDRAM), suitable for one computer The system is operated in a first mode or a second mode, and includes: a first bus bar for transmitting a complex signal; a first slot disposed on the common module and coupled to the first bus bar The DDRII SDRAM is installed in the first mode; a second slot is disposed on the common module, and the first bus is connected to the first bus bar for installing the DDRIII SDRAM in the second mode. And a plurality of termination resistors correspondingly coupled to the first busbar; wherein each of the termination resistors is between 0 ohms and 100 ohms; wherein, in the first mode, the DDRII SDRAM is mounted on the first plug The DDRIII SDRAM is not mounted in the second slot; the patent scope is modified by the Japanese Patent Application No. 96 1 355 590, which is incorporated herein by reference. The first slot is removed, DDRIII SDRAM mounted on the second slot. 11. The shared module of the DDRII SDRAM and the DDRIII SDRAM according to claim 10, further comprising a third slot disposed on the shared module for installing a main controller configuration of the computer system The main controller provides the signals to the first bus. 12. The shared module of the DDRII SDRAM and the DDRIII SDRAM according to claim 11 further includes a chipset that is lightly connected to the first controller for transferring the signals to the first busbar. 13. The shared module of the DDRII SDRAM and the DDRIII SDRAM according to the first aspect of the patent application, wherein the signals include: a complex data signal, a 'multiple address letter number', and a complex number control signal And: a plurality of terminals »4»· •令. - · The resistor includes a plurality of first terminating resistors, a plurality of second terminating resistors, the first terminating resistors are coupled to the address signals, and the second terminating resistors are coupled to the controls signal. 14. The shared module of the DDRII SDRAM and the DDRIII SDRAM according to the first aspect of the patent application, wherein each of the termination resistors is between 10 ohms and 100 ohms. 20
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