CN103311303B - 一种n型横向碳化硅金属氧化物半导体管 - Google Patents
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- 229910052710 silicon Inorganic materials 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 2
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Abstract
一种N型横向碳化硅金属氧化物半导体管,包括:P型衬底,在P型衬底上设有P型外延层,在P型外延层的内部设有N型漂移区、N型源区和P型体接触区,在N型漂移区内设有N型漏区,在P型外延层的表面设有栅氧化层和场氧化层,在栅氧化层和场氧化层的表面设有多晶硅栅,其特征在于,在场氧化层的下方靠近栅氧化层的位置设有重掺杂深P型柱,在栅氧化层正下方设有轻掺杂P型基区,重掺杂深P型柱的存在使得该器件的抗穿通能力有了很大的提高,使得P型基区相对于一般器件,长度更短,浓度更淡,从而降低了器件的导通电阻和阈值电压。
Description
技术领域
本发明主要涉及高压功率半导体器件领域,具体的说,是一种具有低导通电阻、较强防穿通能力的一种N型横向碳化硅金属氧化物半导体管,适用于航天、航空、石油勘探、核能等领域。
背景技术
随着科学技术的发展,越来越多的领域如航天、航空、石油勘探、核能、通信等,迫切需要能够在高温及辐射等极端环境下工作的电子器件。众所周知,硅器件难以在高于250℃的高温下运行,特别是当高的工作温度、大功率、高频及强辐射环境条件并存时,硅器件就难以胜任。碳化硅具有高击穿电场、大禁带宽度、高热导率等优点,使其在功率电路方面更具有应用潜力。
目前N型横向碳化硅金属氧化物半导体管的导通电阻过高使其发展受到了一定的限制,但是N型横向碳化硅金属氧化物半导体管更便于集成,有望将来在功率集成电路领域得到更为广泛的应用。目前在N型横向碳化硅金属氧化物半导体管的设计中,一般通过引入一种降低表面电场的结构来降低N型横向碳化硅金属氧化物半导体管的导通电阻。这种降低表面电场的结构实际上就是一种特殊的漂移区,在截止态时,该漂移区主要被纵向电场耗尽,导致漂移区中的横向电场下降,因此漂移区长度可以设计得更短、掺杂浓度可以设计得更大,从而降低了N型横向碳化硅金属氧化物半导体管的导通电阻。
虽然这种降低表面电场的结构在一定程度上减小了N型横向碳化硅金属氧化物半导体管的导通电阻,但是在沟道开启时其导通电阻依然很高。这是因为N型横向碳化硅金属氧化物半导体管中的反型层电子迁移率很低,使得其导通电阻主要由反型层沟道电阻来决定。而且碳化硅禁带宽度是硅的三倍,所以N型横向碳化硅金属氧化物半导体管的阈值电压相对较高。在N型横向碳化硅金属氧化物半导体管设计中,可以通过降低P型基区浓度、缩短沟道长度来降低阈值以及导通电阻,但是如果P区浓度太淡、沟道长度太小,又会使得器件在截止态时易于发生穿通,导致击穿电压下降。
发明内容
本发明提供一种能够有效提高器件抗穿通能力的N型横向碳化硅金属氧化
物半导体管。
一种N型横向碳化硅金属氧化物半导体管,包括:P型衬底,在P型衬底上设有P型外延层,在P型外延层的内部设有N型漂移区、N型源区和P型体接触区,在N型漂移区内设有N型漏区,在P型外延层的表面设有栅氧化层和场氧化层且栅氧化层的一端和场氧化层的一端相抵,所述栅氧化层的另一端向N型源区延伸并止于N型源区的边界,所述场氧化层的另一端向N型漏区延伸并止于N型漏区的边界,在栅氧化层的表面设有多晶硅栅且多晶硅栅延伸至场氧化层的上表面,在场氧化层、P型体接触区、N型源区、多晶硅栅和N型漏区的表面设有钝化层,在N型源区和P型体接触区表面连接有第一金属层,在多晶硅栅的表面连接有第二金属层,在N型漏区表面连接有第三金属层,其特征在于,在栅氧化层正下方设有轻掺杂的P型基区,且在场氧化层的下方靠近栅氧化层的位置设有重掺杂深P型柱。
与现有技术相比,本发明具有如下优点:
(1)、本发明器件在场氧化层11的下方靠近栅氧化层8的位置设有重掺杂深P型柱15,在截止态时,随着漏端电压的增加,N型漂移区3与P型基区14边界处的耗尽层向重掺杂深P型柱15扩展,当耗尽层扩展到重掺杂深P型柱15时,随着漏端电压的增加将由重掺杂深P型柱15与N型漂移区3的边界来承受高电场,因此将P型基区14屏蔽于高电场之外,有效地提高了该器件的抗穿通能力。如图4所示,本发明器件在沟道长度缩短后,击穿电压并没有因此下降,所以本发明器件有效地防止了器件的穿通。
(2)、本发明器件在栅氧化层的正下方设有长度较短的P型基区14,对于一般器件来说,沟道长度如果做得太短,就会使得器件在截止态时易于发生穿通,击穿电压下降,但是本发明器件中由于重掺杂深P型柱15的存在,使得器件的抗穿通能力有了很大的提高,使得长度较短的P型基区14的引入不会造成器件的提前穿通,因此P型基区14和重掺杂P型柱的共同作用使得本发明器件的沟道长度要比一般器件短得多,由于N型横向碳化硅金属氧化物半导体管中的导通电阻主要由沟道电阻来决定,所以本发明器件可以有效地降低N型横向碳化硅金属氧化物半导体管中的导通电阻,同时也能从一定程度上缩小器件所占的面积。如图3所示,在相同漏压下,本发明器件中的电流要比一般器件的电流大,所以本发明器件有效地降低了器件的导通电阻。
(3)、本发明器件在栅氧化层8的下方设有轻掺杂的P型基区14,由于碳化硅材料的禁带宽度较大,因此N型横向碳化硅金属氧化物半导体管的阈值电压相对较高,在一般器件中可以通过降低P区的浓度来降低阈值电压,但是如果P型浓度太淡会使得器件在截止态时易于穿通,造成击穿电压的下降,而本发明器件中由于重掺杂深P型柱15的存在显著提高了该器件的抗穿通能力,使得轻掺杂P型基区14的引入不会造成器件的提前穿通,因此P型基区14和重掺杂P型柱的共同作用使得N型横向碳化硅金属氧化物半导体管的阈值电压要比一般器件小的多。如图5所示,在漏压一定的情况下,本发明器件沟道开启所需的栅压要比一般器件小,所以本发明器件有效地降低了器件的阈值电压。
附图说明
图1所示为一般结构的N型横向碳化硅金属氧化物半导体管的器件剖面结构。
图2所示为本发明改进后的N型横向碳化硅金属氧化物半导体管的器件剖面结构。
图3所示为本发明器件的导通电阻与一般器件的导通电阻的比较图。可以看出在相同源漏电压下,本发明器件中的电流较大,导通电阻有了有效地降低。
图4所示为本发明器件在截止态时的击穿电压与一般器件的击穿电压的比较图。可以看出本发明在改善了器件的导通电阻的同时,对器件的击穿电压几乎没有影响。
图5所示为本发明器件的阈值电压与一般器件的阈值电压的比较图。可以看出本发明器件的阈值电压相对于一般器件有了明显地降低。
具体实施方式
下面结合附图2,对本发明做详细说明,一种N型横向碳化硅金属氧化物半导体管,包括:P型衬底1,在P型衬底1上设有P型外延层2,在P型外延层2的内部设有N型漂移区3、N型源区5和P型体接触区6,在N型漂移区3内设有N型漏区4,在P型外延层2的表面设有栅氧化层8和场氧化层11且栅氧化层8的一端和场氧化层11的一端相抵,所述栅氧化层8的另一端向N型源区5延伸并止于N型源区5的边界,所述场氧化层11的另一端向N型漏区4延伸并止于N型漏区4的边界,在栅氧化层8的表面设有多晶硅栅9且多晶硅栅9延伸至场氧化层11的上表面,在场氧化层11、P型体接触区6、N型源区5、多晶硅栅9和N型漏区4的表面设有钝化层12,在N型源区5和P型体接触区6表面连接有第一金属层7,在多晶硅栅9的表面连接有第二金属层10,在N型漏区4表面连接有第三金属层13,其特征在于在场氧化层11的下方靠近栅氧化层8的位置设有重掺杂深P型柱15。
所述栅氧化层8的正下方设有轻掺杂的P型基区14。
所述轻掺杂P型基区14的一端与N型漂移区3相抵,所述P型基区14的另一端与N型源区5相抵,且P型基区14的深度是N型源区5深度的1/2倍到1倍。
所述轻掺杂P型基区14的深度为0.2μm,N型源区5的深度为0.4μm。
所述轻掺杂P型基区14的杂质浓度为P型外延层2杂质浓度的1/10倍到1/5倍。
所述轻掺杂P型基区14的杂质浓度为1e15cm-3, P型外延层2的杂质浓度为1e16cm-3。
所述重掺杂深P型柱15与P型基区14的相邻边界之间的距离0.5~1μm,所述重掺杂深P型柱15的端部与N型漂移区3的下边界之间的距离为0.5~1μm。
所述重掺杂深P型柱15的深度为P型基区14深度的2倍到4倍,所述重掺杂深P型柱15的杂质浓度为P型体接触区6的杂质浓度的1倍到2倍。
所述重掺杂深P型柱15的深度为0.8μm,P型基区14的深度为0.2μm,重掺杂深P型柱15的杂质浓度为1e20cm-3,P型体接触区6的杂质浓度为5e19cm-3。
本发明采用如下方法来制备:
首先是在P型衬底1上生长一层P型外延层2,然后在P型外延层2的表面再生长一层轻掺杂的P型外延层,接下来向P型外延层中注入氮离子形成N型漂移区3,再向N型漂移区3中注入铝离子形成重掺杂深P型柱15,然后再向P型外延层中分别注入磷离子和铝离子形成重掺杂的N型源区5、N型漏区4和P型体接触区6。所有掺杂完成后,在第二层P型外延中N型源区5和N型漂移区3之间的位置形成了P型基区14。 接下来进行局部氧化形成场氧化层11,然后进行栅氧化层8的生长,之后淀积多晶硅9,刻蚀形成栅。淀积二氧化硅,刻蚀电极接触区后淀积金属,再刻蚀金属并进出电极,最后进行钝化处理。
Claims (6)
1.一种N型横向碳化硅金属氧化物半导体管,包括:P型衬底(1),在P型衬底(1)上设有P型外延层(2),在P型外延层(2)的内部设有N型漂移区(3)、N型源区(5)和P型体接触区(6),在N型漂移区(3)内设有N型漏区(4),在P型外延层(2)的表面设有栅氧化层(8)和场氧化层(11)且栅氧化层(8)的一端和场氧化层(11)的一端相抵,所述栅氧化层(8)的另一端向N型源区(5)延伸并止于N型源区(5)的边界,所述场氧化层(11)的另一端向N型漏区(4)延伸并止于N型漏区(4)的边界,在栅氧化层(8)的表面设有多晶硅栅(9)且多晶硅栅(9)延伸至场氧化层(11)的上表面,在场氧化层(11)、P型体接触区(6)、N型源区(5)、多晶硅栅(9)和N型漏区(4)的表面设有钝化层(12),在N型源区(5)和P型体接触区(6)表面连接有第一金属层(7),在多晶硅栅(9)的表面连接有第二金属层(10),在N型漏区(4)表面连接有第三金属层(13),其特征在于在场氧化层(11)的下方靠近栅氧化层(8)的位置设有重掺杂深P型柱(15),在栅氧化层(8)正下方设有轻掺杂的P型基区(14),所述轻掺杂P型基区(14)的杂质浓度为P型外延层(2)杂质浓度的1/10倍到1/5倍,所述重掺杂深P型柱(15)的深度为P型基区(14)深度的2倍到4倍,所述重掺杂深P型柱(15)的杂质浓度为P型体接触区(6)的杂质浓度的1倍到2倍。
2.根据权利要求1所述的N型横向碳化硅金属氧化物半导体管,其特征在于所述轻掺杂P型基区(14)的一端与N型漂移区(3)相抵,所述P型基区(14)的另一端与N型源区(5)相抵,且P型基区(14)的深度是N型源区(5)深度的1/2倍到1倍。
3.根据权利要求2所述的N型横向碳化硅金属氧化物半导体管,特征在于所述轻掺杂P型基区(14)的深度为0.2μm,N型源区(5)的深度为0.4μm。
4.根据权利要求1所述N型横向碳化硅金属氧化物半导体管,其特征在于所述轻掺杂P型基区(14)的杂质浓度为1e15cm-3,P型外延层(2)的杂质浓度为1e16cm-3。
5.根据权利要求1所述N型横向碳化硅金属氧化物半导体管,其特征在于所述重掺杂深P型柱(15)与P型基区(14)的相邻边界之间的距离0.5~1μm,所述重掺杂深P型柱(15)的端部与N型漂移区(3)的下边界之间的距离为0.5~1μm。
6.根据权利要求1所述的N型横向碳化硅金属氧化物半导体管,其特征在于所述重掺杂深P型柱(15)的深度为0.8μm,P型基区(14)的深度为0.2μm,重掺杂深P型柱(15)的杂质浓度为1e20cm-3,P型体接触区(6)的杂质浓度为5e19cm-3。
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