CN103247581B - 芯片封装和装置 - Google Patents

芯片封装和装置 Download PDF

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Publication number
CN103247581B
CN103247581B CN201310049127.8A CN201310049127A CN103247581B CN 103247581 B CN103247581 B CN 103247581B CN 201310049127 A CN201310049127 A CN 201310049127A CN 103247581 B CN103247581 B CN 103247581B
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China
Prior art keywords
antenna
chip
substrate
rfic
rfic chip
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CN103247581A (zh
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刘兑现
J-O·普卢沙尔
S·K·雷诺兹
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Tessera Inc
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07775—Antenna details the antenna being on-chip
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Waveguide Aerials (AREA)

Abstract

本发明涉及芯片封装和装置。提供了晶片尺寸结构和方法以集成封装天线结构与半导体RFIC（射频集成电路）芯，从而形成用于毫米波（mm波）和太赫兹（THz）应用的紧凑型集成无线电/无线通信系统。例如，芯片封装包括RFIC芯片、天线结构和界面层。所述RFIC芯片包括具有活性表面和非活性表面的半导体衬底以及在所述半导体衬底的所述活性表面上形成的BEOL（后段制程）结构。所述天线结构包括天线衬底和在所述天线衬底的表面上形成的平面天线辐射器，其中所述天线衬底由低损耗半导体材料形成。所述界面层将所述天线结构连接到所述RFIC芯片的所述BEOL结构。

Description

芯片封装和装置
技术领域
本发明一般地涉及带有集成天线的晶片尺寸（wafer-scale）封装结构。更具体地说，涉及晶片尺寸封装结构和用于整体地封装天线结构与半导体RFIC（射频集成电路）芯片的方法，从而形成用于毫米波（mm波）和太赫兹（THz）应用的紧凑型集成无线电/无线通信系统。
背景技术
在无线网络中，使用与接收器或发射器耦合的天线实现设备间的连接性和通信，以便与网络中的其它元件相互发射所需信号。在传统无线电通信系统（例如，毫米波无线电）中，分立部件通常以低集成水平组装。这些系统常使用昂贵且庞大的波导和封装级或板级微带结构进行组装以互连半导体及其所需的发射器或接收器天线。随着半导体技术和封装工程的最新发展，这些无线电通信系统的尺寸变得越来越小。
对于某些现有技术而言，可使用多层印刷电路板（PCB）（基于有机）或使用低温共烧陶瓷（LTCC）技术（基于陶瓷）制造多层集成天线结构。这些多层有机或陶瓷集成天线结构可使用标准C4（可控坍塌芯片连接）技术与半导体IC芯片相连。使用基于有机或陶瓷的封装技术制造的集成天线结构一般适合于60GHz，甚至最高94GHz频带中的应用工作频率，同时能实现适当性能。但是，对于94GHz甚至更高的频带的操作频率，由于例如低PCB和LTCC制造解析度，使用上述基于有机或陶瓷的多层天线结构便成问题。而且，用于PCB和LTCC技术的封装材料对于高频应用而言损耗度太大。因此，需要设计具有与半导体IC芯片（例如，RFIC）耦合的集成天线的封装结构，从而为工作频率最高达到THz范围的应用提供高性能操作。
发明内容
一般而言，本发明的示例性实施例包括带有集成天线的晶片尺寸封装结构，具体而言，晶片尺寸封装结构和方法以集成封装天线结构与半导体RFIC芯片，从而形成用于毫米波（mm波）和太赫兹（THz）应用的紧凑型集成无线电/无线通信系统。
在一个示例性实施例中，一种芯片封装包括RFIC芯片、天线结构和界面层。所述RFIC芯片包括具有活性表面和非活性表面的半导体衬底以及在所述半导体衬底的所述活性表面上形成的BEOL（后段制程）结构。所述天线结构包括天线衬底和在所述天线衬底的表面上形成的平面天线辐射器，其中所述天线衬底由低损耗半导体材料形成。所述界面层将所述天线结构连接到所述RFIC芯片的所述BEOL结构。所述低损耗半导体材料例如可以为高电阻率硅、硅石（silica）或石英。
在另一示例性实施例中，一种装置包括芯片封装和电路板，其中所述芯片封装安装在所述电路板上。所述芯片封装包括RFIC芯片、天线结构和界面层。所述RFIC芯片包括具有活性表面和非活性表面的半导体衬底以及在所述半导体衬底的所述活性表面上形成的BEOL（后段制程）结构。所述天线结构包括天线衬底和在所述天线衬底的表面上形成的平面天线辐射器，其中所述天线衬底由低损耗半导体材料形成。所述界面层将所述天线结构连接到所述RFIC芯片的所述BEOL结构。所述低损耗半导体材料例如可以为高电阻率硅、硅石或石英。所述装置进一步包括提供所述RFIC芯片和所述电路板之间的DC电源、接地、控制和I/O基带信号线的电互连。
通过结合附图阅读下面对示例性实施例的详细描述，本发明的上述和其它示例性实施例、方面和特性将得到阐释或变得显而易见。
附图说明
图1示意性地示出根据本发明的示例性实施例的包括天线结构和集成电路芯片的封装结构。
图2示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图3示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图4示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图5示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图6示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图7示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图8示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图9示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图10示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图11示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
图12示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。
具体实施方式
现在将参考晶片尺寸封装结构和方法进一步详细地介绍本发明的示例性实施例，所述晶片尺寸封装结构和方法集成封装天线结构与半导体RFIC（射频集成电路）芯片，从而形成用于毫米波（mm波）应用（例如，94GHz）和太赫兹（THz）应用（例如，300GHz至6THz）的紧凑型集成无线电/无线通信系统。一般而言，根据本发明的示例性实施例的封装结构包括使用硅或薄膜制造工艺制造的天线结构，此天线结构使用晶片尺寸制造技术与RFIC芯片集成封装。在下面将参考图1-12详细介绍的封装结构示例性实施例中，封装结构通常包括RFIC（射频集成电路）芯片、天线结构和界面层。RFIC芯片包括具有活性表面和非活性表面的半导体衬底，以及在半导体衬底的活性表面上形成的BEOL（后段制程）结构。天线结构包括天线衬底和在天线衬底的表面上形成的平面天线辐射器，其中天线衬底由一个或多个天线衬底层形成，其中天线衬底由低损耗半导体材料形成，例如高电阻率硅（或低损耗硅）、硅石、石英或其它适当的半导体材料。界面层将天线结构连接到RFIC芯片的BEOL结构。
将理解，附图所示的各层和/或区域并非按比例绘制，并且通常在集成芯片封装中使用的一种或多种层和/或区域类型可能不在给定图中明确示出。这并不暗示实际的集成芯片封装省略未明确示出的层和/或区域。而且，各图中相同或类似的参考标号用于表示相同或类似的特征、部件或结构，因此，对于每个附图，不再重复对相同或类似的特征、部件或结构的详细说明。
图1示意性地示出根据本发明的示例性实施例的包括天线结构和集成电路芯片的封装结构。具体而言，图1是封装结构100的示意性侧视图，此封装结构包括RFIC芯片110、界面层120、天线结构130和应用板140（或电路板）。RFIC芯片110包括半导体衬底112（例如，低电阻率硅衬底）和具有介电层和金属化层的多个交错层（例如，层L1、L2、L3和L4）的BEOL（后段制程）结构114。天线结构130一般包括至少一个衬底层132、在衬底132的顶表面上形成的平面天线134结构、穿过衬底132形成的多个通孔，以及多个在衬底132的顶表面上形成的接触衬垫138。
如图1的示例性实施例中描述的那样，天线辐射器134可以是电磁耦合贴片天线（patch antenna），其中天线接地面102和天线馈线104是形成为RFIC芯片110的BEOL结构114的一部分的金属化结构。具体而言，如图1所示，天线接地面102是在RFIC芯片110的BEOL结构114的第一层（底层）L1中形成的金属化结构，而天线馈线104是在RFIC芯片110的BEOL结构114的最后的层（顶层）L4上形成的金属化结构。天线馈线104例如可以是电磁耦合到贴片天线辐射器134的微带线或共平面波导线，其中接地面102还充当天线馈线104的接地面。
低损耗天线衬底132由低损耗半导体衬底材料形成，例如高电阻率硅（例如，>1000Ohm·cm）、硅石、石英或其它适合于晶片尺寸制造的材料。衬底132的介电常数和厚度将决定诸如天线辐射效率和带宽之类的天线性能参数。例如，对于94GHz工作频率，衬底132可以由厚度约为50微米的低损耗硅衬底形成。贴片辐射器134的尺寸和结构将决定天线的谐振频率，本领域的普通技术人员将理解这一点。
RFIC芯片110的衬底112包括在其活性表面上形成的有源电路元件。有源电路元件可以形成接收器、发射器或收发器电路，以及其它通常用于实现无线RFIC芯片的有源或无源电路元件。BEOL结构114的各层可以由诸如氧化硅之类的常用介电材料或绝缘材料、由铜或金或其它用于在晶片尺寸制造中实现BEOL结构的常用金属或导体材料形成。RFIC芯片110的整体厚度可以在约150微米或约700微米的范围内，具体取决于应用要求。该厚度例如由芯片与芯片封装或应用板如何接口决定。
天线衬底132通过界面层120附着到RFIC芯片110上，所述界面层包括多个借助底填充材料124加固的微金属柱或微金属球122/126。微金属柱或微金属球122/126可以包括用于将天线衬底132接合到RFIC芯片110的无源金属连接衬垫或连接环122，或者包括有源金属衬垫126，该有源金属衬垫126提供BEOL结构114的顶层L4的金属线路106和连接到天线衬底132顶表面上的接触衬垫138的金属通孔136之间的电连接。
衬底132顶表面上的接触衬垫138充当到应用板140（例如，印刷电路板）上的接触衬垫142的连接。接触衬垫142可以是接地衬垫、DC电源衬垫、输入/输出衬垫、控制信号衬垫等。应用板140上的接触衬垫142使用接合线144而线接合到天线衬底132上的接触衬垫138。在这方面，RFIC芯片/天线封装110/130通过线合线144连接到应用板140，其中所有mm波或THz频率信号包含在RFIC封装中，只有诸如DC电源、控制和基带信号之类的低频信号通过接合线144。
将理解，上面参考图1介绍的本发明的原理可以扩展到其它封装设计。例如，图2示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构。具体而言，图2是封装结构200的示意性侧视图，此封装结构与图1中的封装结构100类似，只是图2中的封装结构200包括形成电磁耦合层叠贴片天线结构的多层天线结构230。具体而言，天线结构230包括具有第一贴片辐射器134和通孔136（类似于图1）的第一衬底132以及具有通孔236和在其顶表面上形成的第二贴片辐射器234和接触衬垫238的第二衬底232。
在图2的示例性实施例中，使用两个贴片辐射器134/234来增加天线带宽（与图1中的单贴片结构相比），在特定应用中需要这样做。两种衬底132和232可由相同材料或不同材料形成。例如，第一衬底层132可以由玻璃（硅石）形成，而第二衬底232可由低损耗硅形成，从而提供两种具有不同介电常数（硅石具有小于硅的介电常数）的低损耗衬底。可使用本领域的普通技术人员公知的方法实现具有不同损耗和介电常数的材料以调谐层叠贴片天线结构的操作频率/带宽。
与图1中的封装结构类似，第二衬底232表面上的接触衬垫238充当到应用板140（例如，印刷电路板）上的接触衬垫142的连接。接触衬垫142可以是接地衬垫、DC电源衬垫、输入/输出衬垫、控制信号衬垫等。应用板140上的接触衬垫142使用接合线144线接合到天线衬底232上的接触衬垫238。在不同的天线衬底132和232中形成的通孔126和236被形成为相互对准，以提供BEOL结构114的顶层L4的金属线路106和天线衬底232顶表面上的接触衬垫238之间的电连接。
图1和2的示例性实施例示出具有电磁耦合贴片天线和层叠贴片天线结构的天线结构。这些设计可以扩展为包括其它类型的辐射器，例如平板槽天线结构或平板槽环天线结构。在此类实施例中，图1和2中的辐射器134和234实现为其中形成定义本领域公知的槽或槽环的孔的薄金属板。这些用于形成槽或槽环天线结构的金属板可进一步充当散热器以散发RFIC芯片110产生的热量。
而且，由于晶片尺寸制造技术用于制造根据本发明的原理的芯片封装，因此可以在封装设计中实现细栅距金属结构，从而还允许在封装中实现带有针馈（probe-feed）和孔馈（aperture-feed）的贴片天线。例如，图3示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构，此结构实现孔耦合天线设计。具体而言，图3是封装结构300的示意性侧视图，此封装结构与图2中的封装结构200类似，只是图3中的封装结构300包括形成孔耦合贴片天线的多层天线结构330。
具体而言，天线结构330包括第一衬底层331、天线接地面332、第二衬底层333和贴片辐射器334。接地面332包括多个孔335A和335B。与图1和2中的封装结构对照，天线接地面332形成为天线结构330的一部分，而非RFIC芯片110的BEOL114的一部分。如图3所示，在BEOL114的第一层L1上形成的接地面102充当天线馈线104的接地面。在图3的示例性实施例中，电磁能通过形成于接地面332中的孔335A在天线馈线104和天线辐射器334之间耦合。而且，形成于第一和第二天线衬底331和333中的通孔336和337穿过形成于天线接地面332中的孔335B，从而在BEOL结构114的顶层L4的金属线路106和天线衬底333顶表面上的接触衬垫338之间形成电连接。
通过在图3中的天线封装结构330内实施天线接地面332（与图1和2所示的在BEOL结构114中实施天线接地面102相比），用天线接地面332将天线辐射器334和天线馈线104隔离开。这样允许天线辐射器和馈电结构基本上相互独立地进行优化。图3中的孔耦合封装设计可以扩展到孔耦合层叠贴片天线设计（如下面参考图4所述）和针馈贴片天线设计（如下面参考图5所述）。
图4示意性地示出根据本发明的另一示例性实施例的封装结构，此结构实现孔耦合层叠贴片天线设计。具体而言，图4是封装结构400的示意性侧视图，此封装结构与图3中的封装结构300类似，只是图4中的封装结构400包括多层天线结构430，此天线结构包括形成于其表面上的带有第二贴片辐射器434的附加天线衬底层432、穿过衬底432形成并将下天线衬底层333和331中的下通孔337和336连接到形成于天线衬底层432顶表面上的导电衬垫438的附加通孔436。图4中的层叠贴片天线设计提供了改进的操作带宽，该设计包括位于天线衬底333上的第一贴片辐射器334，其中第二贴片辐射器343形成于天线衬底432上。上辐射器贴片434被形成为比下辐射器贴片334宽，从而允许贴片辐射器334/434和天线馈线104之间通过形成于天线接地面332中的孔335A进行有效耦合，并且允许调谐天线带宽。
图5示意性地示出根据本发明的另一示例性实施例的封装结构，此结构实现针馈贴片天线设计。具体而言，图5是封装结构500的示意性侧视图，此封装结构与图3中的封装结构300类似，只是图5中的封装结构500包括多层天线结构530，此天线结构包括穿过天线层331、332和333形成的垂直馈针532，该垂直馈针将天线馈线104连接到形成于天线衬底333的表面上的贴片辐射器334。连接到馈线104端部的垂直馈针532充当垂直过渡，其将穿过接地面332的孔335A进行延伸，从而将来自天线馈线104的能量耦合到贴片辐射器334。
图6示意性地示出根据本发明的另一示例性实施例的封装结构，此结构实现TSV（硅通孔）设计。具体而言，图6是封装结构600的示意性侧视图，此封装结构与图1中的封装结构100类似，只是图6中的封装结构600包括RFIC芯片610，该芯片具有多个穿过RFIC芯片610的半导体衬底112形成的导电硅通孔611、612和613。RFIC芯片610的底层640包括绝缘层641（钝化层）和多个形成于RFIC芯片610的非活性表面上的接触衬垫642。接触衬垫642可以使用焊料球（例如，C4连接）接合到形成于应用板40上的对应接触（未示出）。在图6的示例性实施例中，硅通孔611、612和613提供底层接触衬垫642和分别形成于BEOL114各层上的金属线路108、102和107之间的电连接。
具体而言，硅通孔612提供BEOL114的第一层L1上的接地面102和接触衬垫642之间的电连接，从而提供RFIC芯片610和应用板140之间的接地连接。硅通孔611提供形成于BEOL114的第三层L3上的金属线路108和接触衬垫642之间的电连接，从而提供RFIC芯片610和应用板140之间的DC电源、或者控制或I/O基带信号连接。类似地，硅通孔613提供形成于BEOL114的第二层L2上的金属线路107和接触衬垫642之间的电气连接，从而提供RFIC芯片610和应用板140之间的DC电源、或者控制或I/O基带信号连接。与图1中的天线封装层130对照，图6中的天线封装层630不包括天线衬底132内的任何导电通孔。相反，通过图6中的封装设计，所有DC电源、接地、控制和I/O基带信号线借助RFIC芯片610实现。
图1-6示出其中RFIC芯片和天线封装结构的足印（footprint）尺寸相同或基本相似的示例性实施例。在本发明的其它示例性实施例中，如下面参考图7-12介绍的那样，RFIC芯片和天线封装结构的足印尺寸不同，从而允许使用不同的封装和布线方法。例如，在其中RFIC芯片的足印尺寸大于天线封装的足印尺寸的应用中，低频接合线可以附着到RFIC芯片顶表面以及天线封装的顶表面上。
具体而言，图7示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构，其中RFIC芯片的足印尺寸大于天线结构。更具体地说，图7示出封装结构700的示意性侧视图，此封装结构包括RFIC芯片710以及尺寸小于RFIC芯片710的天线结构730。图7中的封装结构700与图2中的封装结构200类似，因为封装结构700包括形成电磁耦合层叠贴片天线结构的多层天线结构。具体而言，天线结构730包括带有第一贴片辐射器733和通孔735的第一衬底731以及带有通孔736和第二贴片辐射器734和形成于其顶面上的接触衬垫738的第二衬底732。天线衬底731/732的足印尺寸小于RFIC芯片710，以便RFIC芯片710顶表面的周边区域不被天线结构730覆盖。
在该设计中，附加接触衬垫148可以形成于RFIC芯片710上表面的暴露的周边区域上，并且接合线连接146可以在RFIC芯片710顶表面上的接触衬垫148和应用板上的接触衬垫142之间形成，从而提供RFIC芯片710和应用板140之间的DC直流电源，或者控制或I/O基带信号连接。如果RFIC芯片710顶表面上的暴露区域有限，则附加接合线连接144可以在天线衬底732顶表面上的接触衬垫738和应用板140上的接触衬垫142之间形成，从而提供附加DC电源，或者控制或I/O基带信号连接。在本发明的其它示例性实施例中，可在封装结构700上添加顶部包封（保护）层740以保护RFIC芯片710的暴露表面区域。
图8-11示出其中天线结构的足印尺寸大于RFIC芯片的足印尺寸的封装结构的各种示例性实施例。例如在实例中，天线结构的足印尺寸可以大于RFIC芯片的足印尺寸，其中天线结构包括多个形成阵列天线的辐射器，或者其中天线的工作频率相对较低（在这种情况下，针对所需的较低谐振频率构建较大的平板天线结构）。
例如，图8示意性地示出封装结构800的一个示例性实施例，其中RFIC芯片810的足印尺寸小于天线结构830的足印尺寸。一般而言，与图1类似，图8中的封装结构800包括电磁耦合贴片天线设计。天线结构830包括多个天线衬底831、832和833，其中贴片辐射器834形成于天线衬底833顶表面上。天线衬底831、832和833延伸超过RFIC芯片810的侧壁，从而允许天线封装830通过界面层820附着到应用板840上。
在本发明的一个示例性实施例中，界面820包括BGA（球栅阵列）界面，其包括多个包封在底填充材料824中的BGA连接822、826。有些BGA连接822是被实现为将天线结构830接合到应用板840表面的非电连接。其它BGA连接826仍充当应用板840和RFIC芯片810之间的电连接。例如，如图8所示，有些BGA连接826连接到形成为RFIC芯片810和天线结构830之间的界面层120的一部分的金属线路122，以及连接到通过天线830的各衬底层831和832中形成的过孔和金属线形成的金属线路835，从而提供RFIC芯片810和应用板840之间的DC直流电源，或者控制或I/O基带信号连接。
应用板840被形成为带有以插入的方式接收RFIC芯片810的开口841。而且，借助形成于应用板840中的开口841，可选的散热器850可以附着到RFIC芯片810的半导体衬底112的非活性表面上，以提供散发RFIC芯片810产生的热的装置。在本发明的其它示例性实施例中，例如图9所示，应用板940中可能不具有在其中形成的开口。在这种情况下，天线结构830和应用板940之间的BGA界面920包括BGA连接924、926和底填充层924，该底填充层的厚度（例如，对于多数应用而言350μm的厚度是足够）足以提供天线结构830和应用板940之间的适当接合/连接。
通过此处描述的封装设计方法，带有集成天线的RFIC封装可以通过BGA界面倒置附着到应用板上，该应用板中形成开口以提供天线辐射窗口。这些结构的示例性实施例在图10和11中示出。具体而言，图10示意性地示出封装结构1000的一个示例性实施例，其中RFIC芯片1010的足印尺寸小于天线结构1030的足印尺寸，这与图8中的结构类似，但是其中封装1000倒置。封装结构1000包括电磁耦合贴片天线设计。天线结构1030包括多个天线衬底1031、1032和1033，其中贴片辐射器1034形成于天线衬底1033的表面上。
天线1010通过界面层1020连接到RFIC芯片1010，界面层1020的结构类似于上述其它实施例中的界面层。可选的散热器1050可以附着到RFIC芯片1010的半导体衬底112的非活性表面上，以提供散发RFIC芯片1010产生的热的装置。
封装1000使用BGA界面1042/1043倒置附着到应用板1040上，其中天线结构1030的贴片辐射器1034与形成于应用板1040中的开口1041对准。此开口1041提供天线辐射器1034的窗口以发射和捕获电磁辐射。在本发明的一个示例性实施例中，界面1042/1043包括多个包封在底填充材料中的BGA连接。有些BGA连接1043是被实现为将天线结构1030接合到应用板1040表面的非电连接。其它BGA连接1042还充当应用板1040和RFIC芯片1010之间的电连接。例如，如图10所示，有些BGA连接1042连接到形成为RFIC芯片1010和应用板1040之间的天线衬底层1031、1032和1033的一部分的导电互连1035（包括一系列导电通孔和金属线路）。这些导电互连1035提供RFIC芯片1010和应用板1040之间的DC直流电源、或者控制或I/O基带信号连接。
图11示意性地示出封装结构1100的另一示例性实施例，其中RFIC芯片1110的足印尺寸小于天线结构1130的天线结构，这与图10中的结构类似，但是其中使用接合线提供RFIC芯片1110和应用板1140之间的DC直流电源、或者控制或I/O基带信号连接。如图1所示，封装结构1100包括电磁耦合贴片天线设计，其中天线结构1130包括多个天线衬底1131、1132和1133，其中贴片辐射器1134形成于天线衬底1133的表面上。
而且，天线衬底1131的暴露表面的周边区域上形成接触衬垫1136。接触衬垫1136连接到形成为RFIC芯片1110和接触衬垫1136之间的天线衬底层1131、1132和1133（或界面层1120）的一部分的导电互连1135（包括一系列导电通孔和金属线路）。接合线连接1146形成于天线衬底1131的暴露表面上的接触衬垫1136和应用板1140上的接触衬垫1144之间，从而提供RFIC芯片1110和应用板1140之间的DC直流电源、或者控制或I/O基带信号连接。而且，如图11所示，非活性BGA连接1143用于将天线结构1130连接到应用板1140。可选的散热器1150可以附着到RFIC芯片1110的半导体衬底112的非活性表面上，以提供散发RFIC芯片1110产生的热量的装置。
在本发明的其它示例性实施例中，根据本发明原理的示例性封装结构可以借助常规BGA或接点栅格阵列（LGA）封装概念实现。例如，图12示意性地示出根据本发明的另一示例性实施例的包括天线结构和集成电路芯片的封装结构，此结构使用BGA或LGA封装实现。具体而言，图12是封装结构1200的示意性侧视图，此封装结构包括RFIC芯片1210、天线结构1230和连接RFIC芯片1210与天线结构1230的界面层1220。RFIC芯片1210通过接合层1251接合到封装衬底1250。封装包封层1260环绕RFIC芯片1210和天线封装1230的侧面和顶部形成，其中包封层1260顶部区域中的开口允许天线1230发射和捕获辐射。多个接触衬垫1212形成于RFIC芯片1210上表面的暴露周边区域上。接合线连接1214形成于RFIC芯片1210上的接触衬垫1212和封装衬底1250上形成的接触衬垫1252之间。多个导电通孔1253形成于封装衬底1250中，从而形成接触衬垫1252和接触1242（形成于封装衬底1250的底表面和应用板1240之间）之间的电连接，借此提供RFIC芯片1210和应用板1240之间的DC直流电源、或者控制或I/O基带信号连接。
本领域的普通技术人员很容易理解与根据本发明实施例的集成芯片/天线封装结构关联的各种优点。例如，很容易使用公知的晶片尺寸制造和封装技术制造示例性封装结构，从而制造和封装天线结构与半导体RFIC芯片以形成用于毫米波和太赫兹应用的紧凑型集成无线电/无线通信系统。此外，根据本发明示例性实施例的集成芯片封装允许将天线与收发器芯片之类的IC芯片整体封装在一起，这样可提供收发器和天线之间具有低损耗的紧凑型设计。可实现各种类型的天线设计，例如其中包括贴片天线，槽天线、槽环天线、偶极天线和谐振腔天线。而且，使用根据本发明的集成天线/IC芯片封装节省大量空间、尺寸、成本和重量，这对于几乎任何商业或军事应用而言都是最佳选择。
尽管此处参考出于说明目的的附图描述了示例性实施例，但是将理解，本发明并不限于这些精确的实施例，在不偏离本发明范围的情况下，本领域的技术人员可以执行各种其它更改和修改。

Claims (21)

1.一种芯片封装，包括：
RFIC(射频集成电路)芯片，其包括具有活性表面和非活性表面的半导体衬底以及在所述半导体衬底的所述活性表面上形成的BEOL(后段制程)结构；
天线结构，其包括天线衬底和在所述天线衬底的表面上形成的平面天线辐射器，其中所述天线衬底由低损耗半导体材料形成；
界面层，用于将所述天线结构连接到所述RFIC芯片的所述BEOL结构；以及
天线馈线，其形成为所述RFIC芯片的所述BEOL结构一部分。
2.根据权利要求1的芯片封装，进一步包括在所述天线衬底上的所述表面上形成的接触衬垫以及穿过所述天线衬底形成的导电过孔，其中所述导电过孔形成所述RFIC芯片的所述BEOL结构和在所述天线衬底的所述表面上形成的所述接触衬垫之间的电互连。
3.根据权利要求1的芯片封装，进一步包括形成为所述RFIC芯片的所述BEOL结构一部分的天线接地面。
4.根据权利要求1的芯片封装，其中所述天线衬底为低损耗硅衬底。
5.根据权利要求1的芯片封装，其中所述天线衬底包括由两个或更多个天线衬底层的叠层。
6.根据权利要求5的芯片封装，其中至少一个天线衬底层为低损耗硅衬底以及至少另一天线衬底层为硅石衬底。
7.根据权利要求5的芯片封装，进一步包括在两个邻近天线衬底层之间设置的金属化图形。
8.根据权利要求7的芯片封装，其中所述金属化图形为在所述天线衬底的所述表面上形成的所述天线辐射器和在所述BEOL结构中形成的天线馈线之间设置的天线接地面。
9.根据权利要求7的芯片封装，其中所述金属化图形为第二天线辐射器。
10.根据权利要求7的芯片封装，其中所述金属化图形为电互连的至少一部分。
11.根据权利要求1的芯片封装，其中所述RFIC芯片的足印大于所述天线结构的足印。
12.根据权利要求1的芯片封装，其中所述RFIC芯片的足印小于所述天线结构的足印。
13.根据权利要求1的芯片封装，其中位于所述天线结构和所述BEOL结构之间的所述界面层包括将所述天线结构接合到所述BEOL结构的多个金属柱或环以及底填充材料。
14.根据权利要求1的芯片封装，其中所述低损耗半导体材料为高电阻率硅、硅石或石英。
15.一种用于无线电通信系统的装置，包括：
一种芯片封装，包括：
RFIC(射频集成电路)芯片，其包括具有活性表面和非活性表面的半导体衬底以及在所述半导体衬底的所述活性表面上形成的BEOL(后段制程)结构；
天线结构，其包括天线衬底和在所述天线衬底的表面上形成的平面天线辐射器，其中所述天线衬底由低损耗半导体材料形成；
界面层，用于将所述天线结构连接到所述RFIC芯片的所述BEOL结构；以及
天线馈线，其形成为所述RFIC芯片的所述BEOL结构一部分；
电路板，其中所述芯片封装安装在所述电路板上；以及
电互连结构，用于提供所述RFIC芯片和所述电路板之间的DC电源、接地、控制和I/O基带信号线。
16.根据权利要求15的装置，其中所述电互连结构包括：
在所述天线衬底的所述表面上形成的接触衬垫；
在所述电路板的所述表面上形成的接触衬垫；
在所述天线衬底和所述电路板的所述表面上的接触衬垫之间形成的接合线；以及
在所述天线衬底中形成的导电过孔和金属线路，其将所述天线衬底的所述表面上的所述接触衬垫连接到所述BEOL结构中的接触。
17.根据权利要求15的装置，其中所述电互连结构包括：
从所述活性表面到所述非活性表面穿过所述RFIC芯片的所述半导体衬底形成的导电过孔；以及
位于所述RFIC芯片的半导体子组的所述非活性表面上的接触衬垫，其形成到所述电路板上的接触衬垫的电接合。
18.根据权利要求15的装置，其中所述天线结构被接合到所述电路板，其中所述电路板具有开口，所述开口形成用于通过所述天线辐射器发射或捕获电磁辐射的窗口。
19.根据权利要求15的装置，其中所述天线结构被接合到所述电路板，其中所述电路板具有开口以形成用于插入所述RFIC芯片的窗口。
20.根据权利要求15的装置，其中所述RFIC芯片的所述半导体衬底的所述非活性表面被接合到所述电路板。
21.根据权利要求15的装置，其中所述低损耗半导体材料为高电阻率硅、硅石或石英。
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