CN103219364A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN103219364A
CN103219364A CN2013100015708A CN201310001570A CN103219364A CN 103219364 A CN103219364 A CN 103219364A CN 2013100015708 A CN2013100015708 A CN 2013100015708A CN 201310001570 A CN201310001570 A CN 201310001570A CN 103219364 A CN103219364 A CN 103219364A
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CN103219364B (zh
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高野和丰
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Mitsubishi Electric Corp
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Abstract

本发明提供能在不发生耐压下降或导通电阻增大的情况下提高雪崩耐量的半导体装置及其制造方法。在单元区域，在N－型漏极层（2）上设置有P－型基极层（5）。在中间区域，在N－型漏极层（2）上设置有（P）型基极层（6）。在P－型基极层（5）内设置有N+型源极区域（7）。栅极电极（8）隔着栅极绝缘膜（9）设置在被N－型漏极层（2）和N+型源极区域（7）夹持的沟道区域上。源极电极（10）连接于P－型基极层（5）和P型基极层（6）。栅极焊盘（11）在焊盘区域隔着绝缘膜（12）设置在N－型漏极层（2）上，与栅极电极（8）连接。P型基极层（6）的栅极焊盘（11）侧是杂质浓度梯度比P－型基极层（5）平缓的VLD（VariationLateralDoping）结构。

Description

半导体装置及其制造方法
技术领域
本发明涉及能够在不发生耐压下降或导通电阻增大的情况下提高雪崩耐量的半导体装置及其制造方法。
背景技术
为了实现节省能量或装置的小型化这样的市场要求，要求作为MOSFET或IGBT等半导体装置在导通状态以及开关时的过渡状态的低损失化。此处，当仅着眼于导通状态时，通过使作为主体部（bulk portion）的外延层的晶片指标（wafer specification）低电阻化，从而降低导通电阻，能够实现低损失化。但是，导通电阻和耐压处于折衷（tradeoff）的关系，若仅单纯地使晶片指标为低电阻，则元件耐压下降，达不到目的。因此，在低电阻的晶片指标中使单元的设计最优化来得到高的耐压，并且得到由该晶片指标的低电阻化带来的导通电阻下降的效果，由此，谋求折衷的改善。
伴随由单元设计的最优化带来的耐压提高，当发生由感应负载开关的关断浪涌引起的雪崩动作时，电流容易向单元以外的部位流入。为了在这样的状况下也得到高的耐量，提出了使栅极焊盘下的P型基极层形成得比边缘终端部（芯片外周）的P型基极层深的技术或使栅极焊盘下的P型基极层浮置的技术（例如，参照专利文献l）。
专利文献1：日本特开2011-97116号公报。
在关断时电压由于感应负载的反电动势而上升，当电压超过元件具有的耐压时，半导体装置进行雪崩动作。将此时装置能够流过（能够断开）的电流值或能量值称为雪崩耐量（avalanche capacity）。在由于单元区域的耐压提高而使雪崩电流容易流到单元区域以外的部位的情况下，存在如下问题，即，在栅极焊盘和单元区域之间所设置的P型基极层在雪崩动作时由于电流集中而被破坏。
发明内容
本发明是为了解决上述课题而提出的，其目的在于得到在不发生耐压下降或导通电阻增大的情况下能够提高雪崩耐量的半导体装置及其制造方法。
本发明提供一种半导体装置，具有：第一导电型的半导体层，设置在半导体衬底的单元区域、焊盘区域以及所述单元区域和所述焊盘区域之间的中间区域；第二导电型的第一基极层，在所述单元区域设置在所述半导体层上；第二导电型的第二基极层，在所述中间区域设置在所述半导体层上；第一导电型的导电区域，设置在所述第一基极层内；栅极电极，隔着栅极绝缘膜设置在被所述导电区域和所述半导体层夹持的沟道区域上；第一电极，与所述第一以及第二基极层连接；第二电极，与所述半导体层的下表面连接；栅极焊盘，在所述焊盘区域隔着绝缘膜设置在所述半导体层上并且与所述栅极电极连接；所述第二基极层的所述栅极焊盘侧是杂质浓度梯度比所述第一基极层平缓的VLD（Variation Lateral Doping：横向变掺杂）结构。
根据本发明，能够在不发生耐压下降或导通电阻增大的情况下提高雪崩耐量。
附图说明
图1是表示本发明的实施方式1的半导体装置的俯视图。
图2是沿着图l的A-A’的剖视图。
图3是沿着图1的B-B’的剖视图。
图4是沿着图1的C-C’的剖视图。
图5是表示中间区域的P型基极层的形成方法的图。
图6是表示中间区域的P型基极层的形成方法的图。
图7是表示中间区域的P型基极层的形成方法的图。
图8是表示中间区域的P型基极层的形成方法的图。
图9是表示边缘终端区域的电场分布的图。
图10是表示中间区域附近（栅极焊盘区域）的电场分布的图。
图11是表示比较例l的半导体装置的剖视图。
图12是表示模拟了使MOSFET进行L负载开关时的开关波形的结果的图。
图13是表示比较例2的半导体装置的剖视图。
图14是表示本发明的实施方式1的半导体装置的变形例1的剖视图。
图15是表示本发明的实施方式1的半导体装置的变形例2的剖视图。
图16是表示本发明的实施方式2的半导体装置的剖视图。
图17是表示实施方式2和比较例1的栅极焊盘下的电场强度的图。
图18是表示本发明的实施方式2的半导体装置的变形例的剖视图。
图19是表示本发明的实施方式3的半导体装置的剖视图。
其中，附图标记说明如下：
l  硅衬底（半导体衬底）
2  N－型漏极层（半导体层）
4  漏极电极（第二电极）
5  P－型基极层（第一基极层）
6、24  P型基极层（第二基极层）
7  N+型源极区域（导电区域）
8  栅极电极
9  栅极绝缘膜
10  源极电极（第一电极）
11  栅极焊盘
12  绝缘膜
13  栅极布线
14、15、16、23  P型基极层（第三基极层）
21  SiO2膜（掩模）。
具体实施方式
参照附图对本发明的实施方式的半导体装置及其制造方法进行说明。对相同或对应的结构要素标注相同的附图标记，有时省略重复说明。
实施方式1
图1是表示本发明的实施方式l的半导体装置的俯视图。图2是沿着图1的A-A’的剖视图。
硅衬底1具有单元区域、焊盘区域、中间区域以及边缘终端区域。中间区域配置在单元区域和焊盘区域之间。边缘终端区域配置在单元区域以及焊盘区域的外侧。
在硅衬底l内的整个区域设置有N－型漏极层2。在N－型漏极层2之下设置有N+型漏极层3，在该N+型漏极层3的下表面连接有漏极电极4。
在单元区域，在N－型漏极层2上设置有P－型基极层5。在中间区域，在N－型漏极层2上设置有P型基极层6。在P－型基极层5内设置有N+型源极区域7。栅极电极8隔着栅极绝缘膜9设置于被N+型源极区域7和N－型漏极层2夹持的沟道区域上。源极电极10连接于P－型基极层5以及P型基极层6。漏极电极4连接于N+型漏极层3的下表面。栅极焊盘11在焊盘区域隔着绝缘膜12设置在N－型漏极层2上。栅极焊盘11连接于栅极电极8。
作为本实施方式的特征，在栅极焊盘11的周围的中间区域呈环状设置的P型基极层6的栅极焊盘11侧（a）是杂质浓度梯度比P－型基极层5平缓的VLD（Variation Lateral Doping：横向变掺杂）结构。
图3是沿着图1的B-B’的剖视图。栅极布线13在焊盘区域（实际上是布线区域而不是焊盘区域，但是，此处为了便于说明这样称呼）隔着绝缘膜12设置在N－型漏极层2上。栅极布线13将栅极电极8和栅极焊盘11连接。P型基极层6的栅极布线13侧是杂质浓度梯度比P－型基极层5平缓的VLD结构。
图4是沿着图1的C-C’的剖视图。在边缘终端区域，在N－型漏极层2上设置有P型基极层14、15、16。P型基极层14、15、16是FLR（Field Limiting Ring：场限环）。在最外周设置有N+型沟道停止层17。在P型基极层15、16上分别连接有环形电极18、19。沟道停止电极20连接于N+型沟道停止层17。P型基极层14、15、16的外侧是杂质浓度梯度比P－型基极层5平缓的VLD结构。
接着，对中间区域的P型基极层6的形成方法进行说明。图5至图8是表示中间区域的P型基极层的形成方法的图。首先，如图5所示，在N－型漏极层2上形成SiO2膜21。接着，如图6所示，在SiO2膜21上形成抗蚀剂22，利用照相制版处理对抗蚀剂22进行构图。将该抗蚀剂22作为掩模进行蚀刻，对SiO2膜21进行构图。
构图后的SiO2膜21在中间区域具有朝向焊盘区域宽度变窄的多个开口。接着，如图7所示，通过SiO2膜21的多个开口将硼等杂质注入到N－型漏极层2，如图8所示，利用高温驱动（high-temperature driving）使杂质扩散，形成P型基极层6。将利用这样的晶片工艺所制作的杂质浓度梯度平缓的扩散形状称为VLD结构。
此外，边缘终端区域的P型基极层14、15、16的外侧也同样由VLD形成（例如，参照Semiconductor Devices and Power IC Handbook by Institute of Electrical Engineers of Japan, p. 62～63、日本特开2011-204710号公报）。
接着，对设置有VLD结构的P型基极层的两个区域的电场分布的差异进行说明。图9是表示边缘终端区域的电场分布的图。图10是表示中间区域附近（栅极焊盘区域）的电场分布的图。虚线表示等电位线。在边缘终端区域，在源极电极10和沟道停止电极20之间具有电位差，在横向保持器件耐压。另一方面，在中间区域附近（栅极焊盘区域），在源极电极10和栅极焊盘11之间没有电位差。
接着，与比较例1、2比较，对本实施方式的效果进行说明。图11是表示比较例1的半导体装置的剖视图。在比较例l中，中间区域的P型基极层6和焊盘区域的P型基极层23相连接，两者的厚度相同。在比较例l的情况下，在宽的P型基极层6、23正下方产生的由碰撞电离引起的雪崩电流（碰撞电离电流）流入源极接触部（b），存在发生电流集中并导致破坏的情况。
图12是表示模拟了使MOSFET进行L负载开关时的开关波形的结果的图。总电流是单元区域和中间区域的电流之和。比较例1和实施方式1的总电流相同，但是，在比较例l中，向中间区域的电流高，所以，发生向源极接触部的电流集中。另一方面，在实施方式1中，向单元区域的电流增加，所以，能够缓和向中间区域的电流集中。
此外，在比较例1中，为了减小碰撞电离电流，对杂质注入量或热处理进行控制而使P型基极层6、23变浅时，与它们同时形成的边缘终端区域的P型基极层14、15、16也变浅。因此，边缘终端区域的P型基极层14、15、16的浓度梯度变陡（圆弧部分的曲率即半径变小），担心边缘终端耐压的下降、进而担心雪崩耐量的下降或可靠性的恶化。
图13是表示比较例2的半导体装置的剖视图。在比较例2中，中间区域的P型基极层6和焊盘区域的P型基极层23分离。即，焊盘区域的P型基极层23浮置。由此，如果与比较例1相比，则能够缓和向中间区域的电流集中。但是，在比较例2中，P型基极层6的栅极焊盘11侧（a）的杂质浓度梯度陡（P型基极层6的圆弧部分的曲率小），所以，碰撞电离电流流入到源极接触部（b），存在发生电流集中并导致破坏的情况。
相对于此，在本实施方式中，利用VLD形成的P型基极层6的栅极焊盘11侧（a）是杂质浓度梯度比P－型基极层5平缓的VLD结构。由此，在雪崩动作时能够防止碰撞电离电流向源极接触部（b）的集中。因此，能够提高雪崩耐量。
另外，在本实施方式中，仅变更中间区域的结构，没有变更电流流过的有源区域即单元区域的结构。因此，不会发生耐压下降或导通电阻增大。
另外，不仅是栅极焊盘11的周围，在栅极布线13的周围的P型基极层6也应用VLD结构。由此，能够抑制在栅极布线13的周围的P型基极层6的碰撞电离，能够防止雪崩耐量成为栅极布线13的设计决定要素。
另外，优选在形成P型基极层6时使用的SiO2膜21的多个开口的最大宽度w不足P型基极层6的最深部的深度d的2倍。这样，当开口的宽度窄时，P型基极层6的深度浅，所以，能够增加N－型漏极层2，减小碰撞电离电流。另一方面，在形成作为FLR的P型基极层14、15、16时，使开口的最大宽度w为P型基极层6的最深部的深度d的2倍以上，使P型基极层14、1 5、16变深。
另外，优选同时形成中间区域的P型基极层6和边缘终端区域的P型基极层14、15、16。由此，能够在不增加掩模的情况下形成两者的VLD结构。
图14是表示本发明的实施方式1的半导体装置的变形例1的剖视图。P型基极层6的与栅极焊盘11相反的一侧也是杂质浓度梯度比P－型基极层5平缓的VLD结构。即，在单元侧也形成VLD结构。由此，能够更可靠地防止在雪崩动作时碰撞电离电流向源极接触部（b）的集中。
图15是表示本发明的实施方式1的半导体装置的变形例2的剖视图。除了实施方式1的结构外，在焊盘区域，在N－型漏极层2上设置有P型基极层23。由此，能够减少栅极焊盘11之下的电容。
实施方式2
图16是表示本发明的实施方式2的半导体装置的剖视图。除了实施方式1的结构外，在焊盘区域，在N－型漏极层2上设置有P型基极层23。中间区域的P型基极层6和焊盘区域的P型基极层23相连接。但是，与比较例1不同，P型基极层23比P型基极层6的最深部浅。
图17是表示实施方式2和比较例l的栅极焊盘下的电场强度的图。横轴表示电场强度，纵轴表示距硅衬底1的表面的深度。图中的三角形的面积相当于N－型漏极层2和P型基极层23分别保持的电压。在比较例l中，利用向N－型漏极层2扩展的耗尽层保持大部分的耐压。另一方面，在实施方式2中，耗尽层也向P型基极层23扩展，所以，P型基极层23的电压分担增加。由此，雪崩时的PN结附近的电场强度下降，能够降低碰撞电离电流。
另外，优选P型基极层23的杂质浓度为1.0～2.0E12ions/cm2。由此，成为在对PN结施加反向电压时耗尽层向PN双方的扩散层整体扩展的RESURF（Reduced Surface Field：降低表面电场）条件。因此，耗尽层向P型基极层23的整体扩展。由此，能够进一步降低碰撞电离电流。
另外，优选同时形成单元区域的P－型基极层5和焊盘区域的P型基极层23。由此，能够在不增加掩模的情况下形成这两个结构。
图18是表示本发明的实施方式2的半导体装置的变形例的剖视图。在图16中，P型基极层6的栅极焊盘11侧为VLD结构，但是，在该变形例中，P型基极层6不是VLD结构。在该情况下，P型基极层23比P型基极层6的最深部浅，由此，能够降低碰撞电离电流。
另外，VLD结构以条纹或微细的孔形状制作图案，所以，需要尺寸控制性好的细微加工装置。这样的尺寸控制性好的细微加工装置在变形例中不需要。
实施方式3
图19是表示本发明的实施方式3的半导体装置的剖视图。代替实施方式1的P型基极层6，在中间区域以及焊盘区域，在N－型漏极层2上设置有P型基极层24。P型基极层24的杂质浓度向栅极焊盘11的中心方向增加，在栅极焊盘11的中心部，浓度成为峰值。P型基极层24是杂质浓度梯度比P－型基极层5平缓的VLD结构。由此，能够降低雪崩动作时的碰撞电离电流。
此外，在实施方式1～3中，将本发明应用于n沟道功率MOSFET。但是，并不限定于此，本发明也能够应用于p沟道功率MOSFET、IGBT或SiC器件。

Claims (12)

1.一种半导体装置，其特征在于，具有：
第一导电型的半导体层，设置在半导体衬底的单元区域、焊盘区域以及所述单元区域和所述焊盘区域之间的中间区域；
第二导电型的第一基极层，在所述单元区域设置在所述半导体层上；
第二导电型的第二基极层，在所述中间区域设置在所述半导体层上；
第一导电型的导电区域，设置在所述第一基极层内；
栅极电极，隔着栅极绝缘膜设置在被所述导电区域和所述半导体层夹持的沟道区域上；
第一电极，与所述第一以及第二基极层连接；
第二电极，与所述半导体层的下表面连接；以及
栅极焊盘，在所述焊盘区域隔着绝缘膜设置在所述半导体层上并且与所述栅极电极连接，
所述第二基极层的所述栅极焊盘侧是杂质浓度梯度比所述第一基极层平缓的VLD结构。
2.如权利要求1所述的半导体装置，其特征在于，
还具有：第二导电型的第三基极层，在所述半导体衬底的所述单元区域以及所述焊盘区域的外侧所配置的边缘终端区域，设置在所述半导体层上，
所述第三基极层的外侧是杂质浓度梯度比所述第一基极层平缓的VLD结构。
3.如权利要求1或2所述的半导体装置，其特征在于，
还具有：栅极布线，在所述焊盘区域隔着所述绝缘膜设置在所述半导体层上，并且与所述栅极电极以及所述栅极焊盘连接，
所述第二基极层的所述栅极布线侧是杂质浓度梯度比所述第一基极层平缓的VLD结构。
4.如权利要求1或2所述的半导体装置，其特征在于，
所述第二基极层的与所述栅极焊盘相反的一侧也是杂质浓度梯度比所述第一基极层平缓的VLD结构。
5.一种半导体装置，其特征在于，具有：
第一导电型的半导体层，设置在半导体衬底的单元区域、焊盘区域以及所述单元区域和所述焊盘区域之间的中间区域；
第二导电型的第一基极层，在所述单元区域设置在所述半导体层上；
第二导电型的第二基极层，在所述中间区域设置在所述半导体层上；
第二导电型的第三基极层，在所述焊盘区域设置在所述半导体层上并且比所述第二基极层的最深部浅；
第一导电型的导电区域，设置在所述第一基极层内；
栅极电极，隔着栅极绝缘膜设置在被所述导电区域和所述半导体层夹持的沟道区域上；
第一电极，与所述第一以及第二基极层连接；
第二电极，与所述半导体层的下表面连接；以及
栅极焊盘，在所述焊盘区域隔着绝缘膜设置在所述半导体层上并且与所述栅极电极连接。
6.如权利要求5所述的半导体装置，其特征在于，
所述第三基极层的杂质浓度为1. 0～2.0E12ions/cm2。
7.如权利要求5或6所述的半导体装置，其特征在于，
所述第二基极层的所述栅极焊盘侧是杂质浓度梯度比所述第一基极层平缓的VLD结构。
8.一种半导体装置，其特征在于，具有：
第一导电型的半导体层，设置在半导体衬底的单元区域、焊盘区域以及所述单元区域和所述焊盘区域之间的中间区域；
第二导电型的第一基极层，在所述单元区域设置在所述半导体层上；
第二导电型的第二基极层，在所述中间区域以及所述焊盘区域设置在所述半导体层上；
第一导电型的导电区域，设置在所述第一基极层内；
栅极电极，隔着栅极绝缘膜设置在被所述导电区域和所述半导体层夹持的沟道区域上；
第一电极，与所述第一以及第二基极层连接；
第二电极，与所述半导体层的下表面连接；以及
栅极焊盘，在所述焊盘区域隔着绝缘膜设置在所述半导体层上并且与所述栅极电极连接，
所述第二基极层的杂质浓度向所述栅极焊盘的中心方向增加，
所述第二基极层是杂质浓度梯度比所述第一基极层平缓的VLD结构。
9.一种半导体装置的制造方法，制造权利要求1或2所述的半导体装置，其特征在于，包括如下工序：
在所述中间区域，在所述半导体层上形成掩模，该掩模具有朝向所述焊盘区域宽度变窄的多个开口；
通过所述掩模的所述多个开口向所述半导体层注入杂质，形成所述第二基极层。
10.如权利要求9所述的半导体装置的制造方法，其特征在于，
所述多个开口的最大宽度不足所述第二基极层的最深部的深度的2倍。
11.一种半导体装置的制造方法，制造权利要求2所述的半导体装置，其特征在于，
同时形成所述第二基极层和所述第三基极层。
12.一种半导体装置的制造方法，制造权利要求5或6所述的半导体装置，其特征在于，
同时形成所述第一基极层和所述第三基极层。
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