TWI608618B - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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TWI608618B
TWI608618B TW103130811A TW103130811A TWI608618B TW I608618 B TWI608618 B TW I608618B TW 103130811 A TW103130811 A TW 103130811A TW 103130811 A TW103130811 A TW 103130811A TW I608618 B TWI608618 B TW I608618B
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layer
concentration
buffer layer
parallel
conductivity type
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TW103130811A
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TW201521203A (zh
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Takahiro Tamura
Yasuhiko Onishi
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Fuji Electric Co Ltd
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Description

半導體裝置及其製造方法
本發明是有關半導體裝置(絕緣閘極型場效電晶體)及其製造方法。
作為使用在電力用半導體裝置的半導體元件，有MOSFET(Metal Oxide Semiconductor Field Effect Transistor：絕緣閘極型場效電晶體)或IGBT(Insulated Gate Bipolar Transistor：絕緣閘極型雙極電晶體)等為眾所周知。圖5是通常的反相電路圖。圖6是通常的IGBT(a)及MOSFET(b)的要部剖面圖。作為使用在圖5所示的反相電路1000用的高耐壓開關元件，有IGBT101廣泛普及。IGBT101是具有雙極電晶體的高耐壓．低導通電壓的特長，或雖比MOSFET低速，但可高速動作的優越特長，為支撐現在的電力電子學(power electronics)的重要的半導體元件。
但，圖6(a)的要部剖面圖所示的IGBT101是與同圖(b)所示的MOSFET301不同，由於具有逆耐壓接合(集極接合103)，因此通常在逆方向(將射極E 設為正極，將集極C設為負極的偏壓方向)無法流動電流。IGBT101由導通狀態形成順阻止狀態時，因電路內的電感成分，會有在逆方向產生高電壓的浪涌電壓的情形。一旦此浪涌電壓(surge voltage)被施加於IGBT101，則通常逆耐壓未保護的IGBT101是恐有破壊之虞，但使用在反相電路時，為了使IGBT101的每關斷(turn off)時產生的L負荷(感應負荷)電流還流，而形成藉由逆並聯的二極體401(參照圖5)來保護。符號102，302是n-型漂移層。
另一方面，承受對於反相器(inverter)的高頻化的要求提高，像前述那樣的IGBT101與通常的還流用二極體401的並列連接是在開關的高速化有限，因此有使用可高速開關的IGBT101及高速二極體的情形。高速二極體是使從順方向電流流至二極體的狀態遷移至逆阻止狀態時的逆回復所要的時間形成比通常的二極體短者，可縮小逆回復損失。
圖2是以往的超接合MOSFET的要部剖面圖(a)，及配合對應於(a)的基板的深度方向來取縱軸成深度的載子壽命(carrier lifetime)分布圖。而且，近年來，為了開關元件的更高速化，而檢討將IGBT101置換成圖2(a)所示的超接合MOSFET201。被檢討置換的超接合MOSFET201(參照圖2)是具備超接合(SJ：Super Junction)構造，其係將漂移層205設為在平行於基板主面的方向交替地重複且以狹窄的間隔(間距寬)來配置提 高雜質濃度的n型的領域(以下設為n型漂移領域)202a及p型的領域(以下設為p型間隔領域)202b之並列pn層。並且，漂移層是在並列pn層202的汲極側具備n型第1緩衝層204。基板內的載子壽命(carrier lifetime)未被控制時，如同圖(b)所示般，從基板表面到深度方向為一定(未控制)。在此超接合MOSFET201中，即使以能夠相稱於耐壓的方式將前述並列pn層202內的n型漂移領域202a形成比通常的雜質濃度還高濃度，還是可藉由縮小前述並列pn層202的間距寬來使並列pn層202的全部以低電壓空乏化，因此儘管單極型，還是具有高耐壓低導通電阻(n-resistance)的特徵。而且，除了可為來自單極裝置的高速開關以外，還因為內藏逆方向的二極體構造(圖2(a)的符號203及202a)，不需要重新連接圖5的反相電路的並列二極體401，亦具有可期待裝置的小型化的優點。而且，使用超接合MOSFET(SJ-MOSFET)201作為開關裝置(switching device)，使用內藏的二極體作為快速回復二極體，亦可謀求更高速化及低損失化。
有關如此的超接合MOSFET201的文獻是公開 記載，在漂移層205設置：由並列pn層所構成的SJ構造，及在其下層使雜質濃度兩階段地變化的n型緩衝層，藉此降低導通電阻，使內藏二極體的逆回復特性形成軟回復(soft recovery)波形者(例如參照下述專利文獻1)。有關具備不使汲極，源極間的洩漏電流增大地縮短逆回復時間的SJ-MOS構造之半導體裝置是已經為人所知 (例如參照下述專利文獻2)。並且，記載有藉由在具備SJ構造的蕭特基障壁二極體(schottky-barrier diode)連接SJ-MOSFET，可使適於軟體開關(Soft-Switching)方式的半導體裝置(例如，參照下述專利文獻3)。在具備SJ構造的蕭特基障壁二極體的全體設置壽命控制領域，降低逆電流，使逆回復特性提升(例如參照下述專利文獻4)。有關於為了使逆回復特性形成軟回復波形之壽命控制方法的記載(例如參照下述專利文獻5)。記載有關過剩少數載子的壽命控制方法(例如參照下述專利文獻6)。而且，揭示有關於比以往的元件更可使耐壓及關斷特性提升的半導體裝置的記述(例如參照下述專利文獻7)。
〔先行技術文獻〕 〔專利文獻〕
[專利文獻1]日本特開2003-101022號公報(圖11，段落0077~0079)
[專利文獻2]日本特再公表2010-24433號公報(摘要)
[專利文獻3]日本特開2006-24690號公報(摘要的課題及解決手段)
[專利文獻4]日本特開2008-258313號公報(摘要)
[專利文獻5]日本特開2007-59801號公報(摘要)
[專利文獻6]日本特開平7-226405號公報(課題)
[專利文獻7]日本特開2001-102577號公報(課題)
在前述圖2(a)所示的超接合MOSFET201中，於順阻止狀態，空乏層為低耐壓擴展於並列pn層內的各列(n型漂移領域202a及p型間隔領域202b)內完全空乏化。此時，內藏二極體(符號203-202a)是從順方向電流(還流電流)流動的狀態遷移至內藏二極體的pn接合的逆偏壓阻止狀態(亦即逆回復狀態)。然而，逆回復狀態的內藏二極體，由於超接合MOSFET201為單極構造，因此幾乎無少數載子，逆回復電流Irp小。而且，電流波形及電壓波形容易形成陡峭上升，所謂的硬回復波形。在後述的圖3也記載圖2的以往構造的超接合MOSFET的逆回復電流波形圖。一旦逆回復動作形成硬回復波形，則如圖3的以往構造的超接合MOSFET的逆回復波形圖所示般，產生振盪(Ringing)(振動波形)成為雜訊的發生原因會成問題(在此圖3中振動波形部分會形成重疊塗黑的狀態看不清楚)。另外，圖3的以往構造的波形是針對圖2(a)所示的以往構造的縱型超接合MOSFET201，將電源電壓設為400V，將順方向電流設為20A，且將逆方向電流的時間變化設為100A/μs，而模擬逆回復動作的電流波形的結果。
本發明是考慮以上說明的點而研發者，本發 明的目的是在於提供一種緩和逆回復動作時的硬回復波形之半導體裝置及其製造方法。而且，提供一種緩和硬回復波形，減少逆回復電流(Irp)及逆回復時間(trr)，可取得高速開關及低逆回復損失之半導體裝置及其製造方法。
為了解決上述的課題，達成本發明的前述目 的，此發明的半導體裝置是具有其次的特徵。在第1導電型的汲極層的第1主面上具有延伸於垂直方向之互相平行的複數的pn接合，且設有被該pn接合夾著的第1導電型的漂移領域與第2導電型的間隔領域會交替地接觸排列的並列pn層。在前述並列pn層的第1主面側設有MOS閘極構造。在前述並列pn層與前述汲極層之間設有第1導電型的第1緩衝層。前述第1緩衝層的雜質濃度是比前述漂移領域的雜質濃度還低濃度。前述並列pn層內的前述間隔領域的至少一個會被置換成比前述漂移領域的雜質濃度還低濃度的第1導電型領域。最好在前述第1緩衝層與前述汲極層之間具備雜質濃度比前述漂移領域還高濃度的第2緩衝層。前述第2緩衝層的雜質濃度是比前述漂移領域的雜質濃度還高濃度。最好前述並列pn層是具有格子狀的平面圖案。
為了解決上述的課題，達成本發明的目的，此發明的半導體裝置的製造方法是以下所述的半導體裝置 的製造方法，該半導體裝置係具備：第1導電型的高濃度緩衝層，其係雜質濃度比設在第1導電型的汲極層的第1主面上的漂移領域還高濃度；第1導電型的低濃度緩衝層，其係設在前述高濃度緩衝層上，比前述漂移領域的雜質濃度還低濃度；及並列pn層，其係設在前述低濃度緩衝層上，交替地重複配置第1導電型的漂移領域與第2導電型的間隔領域，前述間隔領域的至少一個被置換成比前述漂移領域的雜質濃度還低濃度的第1導電型領域，其特徵為：包含：藉由重金屬的添加或荷電粒子的照射來使前述並列pn層的載子壽命形成比前述高濃度緩衝層還短之工程。
又，為了解決上述的課題，達成本發明的目的，此發明的半導體裝置的製造方法是以下所述的半導體裝置的製造方法，該半導體裝置係具備：第1導電型的高濃度緩衝層，其係雜質濃度比設在第1導電型的汲極層的第1主面上的漂移領域還高濃度；第1導電型的低濃度緩衝層，其係設在前述高濃度緩衝層上，比前述漂移領域的雜質濃度還低濃度；及並列pn層，其係設在前述低濃度緩衝層上，交替地重複配置第1導電型的漂移領域與第2導電型的間隔領域， 前述間隔領域的至少一個被置換成比前述漂移領域的雜質濃度還低濃度的第1導電型領域，具有其次的特徵。
首先，進行：在前述汲極層的第1主面上形成雜質濃度比前述漂移領域還高濃度的第1導電型的高濃度緩衝層之工程。其次，進行：在前述高濃度緩衝層上形成比前述漂移領域的雜質濃度還低濃度的第1導電型的低濃度緩衝層之工程。其次，進行：在前述低濃度緩衝層上形成前述並列pn層之工程。其次，進行：從前述並列pn層側進行重金屬的添加或荷電粒子的照射，藉此使前述並列pn層的載子壽命形成比前述高濃度緩衝層的載子壽命還短之工程。
又，為了解決上述的課題，達成本發明的目的，此發明的半導體裝置的製造方法是以下所述的半導體裝置的製造方法，該半導體裝置係具備：第1導電型的高濃度緩衝層，其係雜質濃度比設在第1導電型的汲極層的第1主面上的漂移領域還高濃度；第1導電型的低濃度緩衝層，其係設在前述高濃度緩衝層上，比前述漂移領域的雜質濃度還低濃度；及並列pn層，其係設在前述低濃度緩衝層上，交替地重複配置第1導電型的漂移領域與第2導電型的間隔領域，前述間隔領域的至少一個被置換成比前述漂移領域的雜質濃度還低濃度的第1導電型領域， 具有其次的特徵。
首先，進行：在半導體基板的正面側形成前述並列pn層之工程。其次，進行：在前述半導體基板的正面側，於前述並列pn層上形成元件構造之工程。其次，進行：在前述半導體基板的背面側形成比前述漂移領域的雜質濃度還低濃度的第1導電型的低濃度緩衝層之工程。其次，進行：在前述半導體基板的背面側之比前述低濃度緩衝層還淺的位置形成雜質濃度比前述漂移領域還高濃度的第1導電型的高濃度緩衝層之工程。其次，進行：從前述高濃度緩衝層側進行重金屬的添加或荷電粒子的照射，藉此使前述並列pn層的載子壽命形成比前述高濃度緩衝層的載子壽命還短之工程。
若根據本發明，則可提供一種緩和逆回復動作時的硬回復波形的半導體裝置及其製造方法。而且，可提供一種高速動作及逆回復損失的減低可能的半導體裝置及其製造方法。
1‧‧‧n++型汲極層(高濃度第1導電型半導體基板)
2‧‧‧第2緩衝層
3‧‧‧第1緩衝層
4‧‧‧並列pn層
4a‧‧‧n型漂移領域
4b‧‧‧p型間隔領域
5‧‧‧p型基極領域
6‧‧‧pn接合
10a，10b‧‧‧pin二極體
50，201‧‧‧超接合MOSFET
101‧‧‧IGBT
103‧‧‧集極接合
301‧‧‧MOSFET
401‧‧‧二極體
1000‧‧‧反相電路
圖1是本發明的實施例1之並列pn層中的p型間隔領域被置換成雜質濃度比n型漂移領域還低濃度的n型領域之超接合MOSFET的要部剖面圖。
圖2是以往的超接合MOSFET的要部剖面圖(a)，及配合對應於(a)的基板的深度方向來取縱軸成深度的載子壽命分布圖。
圖3是對應於圖2的以往構造的超接合MOSFET及圖1的本發明的實施例1的超接合MOSFET之各個的逆回復電流波形圖。
圖4是本發明的實施例1的超接合MOSFET之各個不同的載子壽命分布圖。
圖5是通常的反相電路圖。
圖6是通常的IGBT(a)及MOSFET(b)的要部剖面圖。
圖7是表示在本發明的超接合MOSFET中，在平行於基板表面的面切斷後的並列pn層的平面圖案的要部剖面圖之一例。
圖8是圖7的B-B'虛線(a)及C-C'虛線(b)的要部剖面圖。
圖9是表示在本發明的超接合MOSFET中，在平行於基板表面的面切斷後的並列pn層的平面圖案的要部剖面圖的別的一例。
圖10是圖9的B-B'虛線(a)及C-C'虛線(b)的要部剖面圖。
以下，參照圖面來詳細說明有關本發明的半 導體裝置及其製造方法以及使二極體並聯的複合半導體裝置的實施例。本說明書及附圖中，就冠上n或p的層或領域是分別意思電子或正孔為多數載子。並且，在n或p附上的+及-是分別意思相對地雜質濃度高或低。另外，在以下的實施例的說明及附圖中，對於同樣的構成是附上同一的符號，省略重複的說明。並且，在實施例所說明的附圖，為了容易看或容易理解，而未以正確的尺度，尺寸比來描繪。本發明只要不超過其主旨範圍，並不限於以下說明的實施例的記載。
〔實施例1〕
圖1是本發明的實施例1之並列pn層中的p型間隔領域被置換成雜質濃度比n型漂移領域還低濃度的n型領域之超接合MOSFET的要部剖面圖。在圖1中顯示本發明的縱型超接合MOSFET50，51的元件活性部的要部剖面圖。圖1(a)，(b)所示的縱型超接合MOSFET50，51是具備超接合(SJ)構造，其係將漂移層設為在平行於基板主面的方向交替地重複配置提高雜質濃度的n型的領域(n型漂移領域)4a及p型的領域(p型間隔領域)4b之並列pn層4。亦即，縱型超接合MOSFET50，51是藉由構成並列pn層4的n型漂移領域4a及p型間隔領域4b，具有延伸於與基板主面垂直的方向(基板深度方向)且互相平行的複數的pn接合6。在圖1(a)顯示具備SJ構造的縱型超接合MOSFET50，該 SJ構造是將並列pn層4的一部分的p型間隔領域4b的複數領域設為比n型漂移領域4a的雜質濃度還低濃度的n-型領域4c。縱型超接合MOSFET50是在並列pn層4與n++型汲極層1之間，從並列pn層4側依序具備：與前述n-型領域4c同程度的雜質濃度的n-型第1緩衝層3，及比前述並列pn層4的n型漂移領域4a的雜質濃度還高濃度的n+型第2緩衝層2。
在圖1(b)顯示具備SJ構造的縱型超接合 MOSFET51，該SJ構造是將並列pn層4的一個p型間隔領域4b設為比n型漂移領域4a的雜質濃度還低濃度的n-型領域4c。縱型超接合MOSFET51是在並列pn層4的下端面與n++型汲極層1之間具備與前述n-型領域4c同程度的雜質濃度的n-型第1緩衝層3。並且，縱型超接合MOSFET50，51是在並列pn層4之對於n-型第1緩衝層3側相反的側具備由p型基極領域5，n+型源極領域7，p+型接觸領域8，閘極絕緣膜9及閘極電極11所構成的一般性的MOS閘極(由金屬-氧化膜-半導體所構成的絕緣閘極)構造，及源極電極12。汲極電極13是接觸於n++型汲極層1。活性領域(元件活性部)是在導通(ON)狀態時電流流動(擔負電流驅動)的領域。
前述圖1(a)，(b)所示的縱型超接合 MOSFET50，51皆是將並列pn層4內的p型間隔領域4b的一部分設為n-型領域4c，藉此具備pin二極體10a，10b及MOSFET領域20，該pin二極體10a，10b是具有 p型基極領域5，n-型領域4c，n-型第1緩衝層3，(n+型第2緩衝層2)。
本發明的縱型超接合MOSFET50，51是藉由 設為前述那樣的構成，不會有令耐壓降低的情形，可使pin二極體10a，10b作用。並且，藉由改變圖1所示的pin二極體10a，10b的數量，可調整軟回復化的程度。越增加pin二極體的數量，軟回復化的效果越大。並且，pin二極體10a，10b是以單體可確保耐壓的程度壓低n-型領域4c的雜質濃度，因此不會有配置場所的限制，n-型領域4c彼此間是亦可夾著n型漂移領域4a而相鄰。
並且，在圖1(a)的前述超接合MOSFET50 中，n+型第2緩衝層2是在超接合MOSFET50的逆回復動作時具有作為載子積存的機能，藉由拉長載子的排出時間，具有更拉長逆回復時間而形成軟回復波形的效果。
圖7是表示在本發明的超接合MOSFET50 中，在平行於基板表面的面切斷後的並列pn層4的平面圖案之要部剖面圖的一例。圖8是圖7的B-B'虛線(a)及C-C'虛線(b)的要部剖面圖。圖9是表示在本發明的超接合MOSFET50中，在平行於基板表面的面切斷後的並列pn層4的平面圖案之要部剖面圖的別的一例。圖10是圖9的B-B'虛線(a)及C-C'虛線(b)的要部剖面圖。在圖7中，A-A'虛線的剖面圖是對應於圖1(a)，B-B'虛線的剖面圖是對應於圖8(a)，C-C'虛線的剖面圖是對應於圖8(b)。在圖9中，A-A'虛線的剖面圖是 對應於圖1(a)，B-B'虛線的剖面圖是對應於圖10(a)，C-C'虛線的剖面圖是對應於圖10(b)。
圖7所示的並列pn層4的平面圖案是延伸於 與n型漂移領域4a及p型間隔領域4b所排列的方向正交的方向之條紋狀。並且，圖9所示的並列pn層4的平面圖案是p型間隔領域4b及n-型領域4c會被配置成格子狀，且以分別被n型漂移領域4a包圍的方式配置。如前述般n-型領域4c的配置數是可適當變更。並且，在圖7及圖9中，在元件周緣部是未形成n-型領域4c。在元件周緣部的並列pn層的表面是設有場絕緣膜18。並且，在元件周緣部的最外周是設有通道阻止層(channel stopper)領域14。在通道阻止層領域14設有被電性連接的通道阻止層電極16。
其次，在以下詳細說明有關耐壓600V等級的 縱型超接合MOSFET50的特性。在以下表示各層，領域的尺寸及雜質濃度等的概略。將並列pn層4的深度方向的厚度(以後所謂厚度是指基板的深度方向的距離)設為36.0μm，且並列pn層4的間距寬是設為12.0μm，n型漂移領域4a及p型間隔領域4b的寬是分別設為6.0μm，前述各領域的雜質濃度是設為3.0×1015cm-3。位於並列pn層4正下面(汲極側)的n-型第1緩衝層3的厚度是設為9μm，雜質濃度是設為比前述n型漂移領域4a還低濃度的1.0×1015cm-3。而且，其下的n+型第2緩衝層2是以空乏層在逆回復動作時也會擴展不斷的方式，厚度設定成 15μm，雜質濃度設定成比前述n型漂移領域4a還高的1.0×1016cm-3。並且，n++型汲極層1的雜質濃度是設為2.0×1018cm-3。
圖4是本發明的實施例1的超接合MOSFET 的各個不同的載子壽命分布圖。在圖4(b)~圖4(d)顯示圖4(a)的縱型超接合MOSFET50的載子壽命的概略的分布圖。任一的情況中皆是n+型第2緩衝層2的載子壽命不控制或相較於並列pn層4及第1緩衝層3不會變短。局部地縮短第2緩衝層2以外的任一或全部的領域的載子壽命而使能夠高速開關。基本的電子壽命是1.0×10-5秒，正孔壽命是3.0×10-6秒，縮短載子壽命時的最低值是將電子載子壽命設為1.0×10-7秒，將正孔載子壽命設為3.0×10-8秒。只要在n+型第2緩衝層2充分地保持載子，便可在逆回復動作時取得軟回復波形。因此，相較於其他的領域，n+型第2緩衝層2的載子壽命長的圖4(b)~圖4(d)的任一分布中也可取得高速開關及軟回復波形。
為了設為圖4(b)~(c)所示的載子壽命分 布，從基板的背面照射質子等，進行熱處理，藉此在(b)是並列pn層4的正面側的深度，在(c)是並列pn層4的背面側的深度，以分別能夠設為峰值的方式(形成最短的方式)，局部地控制壽命即可。並且，若使用白金(Pt)從基板背面側(汲極層側)離子注入，藉由熱處理來使擴散，作為壽命殺手，則白金是容易偏析至基板的正 面側，因此如(d)所示般可取得具有正面側的載子壽命為最短的傾斜之分布。
在此，為了使具有圖4(b)所示的載子壽命 分布之本發明的縱型超接合MOSFET50(圖4(a))的發明的效果明顯，而與具有前述載子壽命未調整的圖2(b)的載子壽命分布之以往的超接合MOSFET201(圖2(a))一起測定回復波形。將其結果顯示於圖3。圖3是對應於圖2的以往構造的超接合MOSFET及圖1的本發明的實施例1的超接合MOSFET之各個的逆回復電流波形圖。圖3是針對前述超接合MOSFET50，201，將電源電壓設為400V，將順方向電流設為20A，且將逆方向電流的時間變化設為100A/μs，而模擬逆回復動作的電流波形的結果。另外，圖4(a)的超接合MOSFET50是使用He(氦)從基板背面側(汲極層側)藉由離子注入及熱處理來控制壽命，作為壽命殺手。並且，設定以離並列pn層4的源極側的表面8μm的深度作為峰值的濃度分布剖面圖(concentration profile)。而且，將圖4(a)的超接合MOSFET50的活性領域之中pin二極體10a的面積設為與MOSFET領域20的面積相同。
由圖3來看，在以往的超接合MOSFET201 中，其逆回復電流的峰值Irp1，逆回復時間trr1皆大，顯示波形為陡峭上升的硬回復波形，形成振動大的波形。其理由是因為無第2緩衝層，且亦無內藏pin二極體，所以在進入順阻止狀態時，隨著在逆回復時空乏層擴展，載子 會容易枯渴。
另一方面，本發明的超接合MOSFET50(在 圖3顯示實施例)是具備比並列pn層中的漂移領域還高濃度的第2緩衝層，且具備內藏pin二極體，因此注入載子會藉由pin二極體而變多，且第2緩衝層具有作為逆回復動作時的載子積存的機能。所以，因為載子的總量增加，逆回復電流(Irp)會增加，逆回復時間變長，回復波形是形成軟性。
由以上的結果，在實施例1中是謀求超接合 MOSFET的軟回復波形化，且實現兼顧逆回復動作的高速化及損失減低的構造。並且，本發明的實施例1是在高濃度的n++型汲極層1上形成n+型第2緩衝層2及n型第1緩衝層3(針對超接合MOSFET51是只形成n型第1緩衝層3)之後，將並列pn層4重複進行多數次的磊晶成長及光微影技術，以同圖案依序堆起並列pn層4而形成所要的厚度之多段磊晶方式形成。並且，亦可取代多段磊晶方式，以溝埋入方式形成。以溝埋入方式形成時，首先，使n+型第2緩衝層2及n型第1緩衝層3以及所要的厚度的漂移層磊晶成長於高濃度n++型汲極層1上。然後，藉由各向異性蝕刻來形成相當於並列pn層的厚度之深度的垂直溝，使成為n-型領域4c的n-型矽層磊晶成長於此溝中而埋入，且使表面平坦化，使漂移層露出。然後再度形成相當於並列pn層的厚度之深度的垂直溝，使成為p型間隔領域4b的p型矽層磊晶成長而形成並列pn層4。在 以前述任一方式作成的並列pn層4的表面側形成MOS閘極構造，源極電極12及背面側的汲極電極13，藉此本發明的實施例1的超接合MOSFET的晶圓製程大致完成。 並且，前述的並列pn層4的形成方法，有關之後的晶圓製程方面，該等的製造方法也可利用以往周知的製造方法。
通常，在電力用二極體中，作為縮短載子壽 命的方法，一般是使用導入壽命殺手的方法，該壽命殺手是藉由Au(金)或Pt(白金)等的重金屬的添加或電子線或質子等的荷電粒子的照射等，硬在能帶隙內形成準位。因為藉由導入如此的壽命殺手，可在逆回復動作時促進二極體中的載子的消滅，使逆回復時的峰值電流Irp或逆回復時間trr減低，使逆回復時的損失減低。由於在超接合MOSFET中也內藏二極體，因此導入壽命殺手來設前述圖4(b)~圖4(d)所示的載子壽命分布，對於高速動作及逆回復損失的減低有效。
於是，本發明的超接合MOSFET50是在第1 緩衝層3的下部形成比並列pn層4的n型漂移領域4a還高濃度的第2緩衝層2。而且，將第1緩衝層3及並列pn層4的載子壽命調整成比此第2緩衝層2的載子壽命短。 藉由如此調整載子壽命，可更緩和地抑制回復波形的上升設為軟回復波形。
作為局部地控制壽命的方法，可藉由金或白金等的重金屬的添加或質子等的荷電粒子的照射來進行。 可從源極領域7側的表面藉由重金屬的離子注入及熱處理來添加至第1緩衝層3。並且，在形成源極電極12後，藉由研磨(grind)來研削基板的相反側(背面)，形成第1緩衝層3及第2緩衝層2，可從該第2緩衝層2的表面照射重金屬的離子或荷電粒子。並且，亦可組合該等的局部性的壽命控制及電子線照射那樣壽命形成一樣的控制。
調整第2緩衝層2的雜質濃度及厚度，在超 接合MOSFET50的順阻止狀態時也可藉由設為空乏層不會到達n++型汲極層1那樣的載子積存，即使在逆回復動作時也不會有漂移層內的載子枯渴的情形，使逆回復波形的上升形成緩和。
若總結在以上的實施例1所述的情形，則藉 由將超接合MOSFET50，51的間隔領域4b的一部分置換成與漂移領域4a同導電型且比漂移領域4a的雜質濃度低的濃度的領域4c，可謀求軟回復化。並且，在超接合MOSFET50中，由第1緩衝層3及第2緩衝層2的2層來構成緩衝層，以第1緩衝層3及並列pn層4的壽命會形成比第2緩衝層2更短的方式導入壽命殺手，藉此更可謀求軟回復化，同時可使逆回復時的峰值電流Irp或逆回復時間trr減低，減低逆回復時的損失。
1‧‧‧n++型汲極層(高濃度第1導電型半導體基板)
2‧‧‧第2緩衝層
3‧‧‧第1緩衝層
4‧‧‧並列pn層
4a‧‧‧n型漂移領域
4b‧‧‧p型間隔領域
4c‧‧‧n-型領域
5‧‧‧p型基極領域
6‧‧‧pn接合
7‧‧‧n+型源極領域
8‧‧‧p+型接觸領域
9‧‧‧閘極絕緣膜
10a，10b‧‧‧pin二極體
11‧‧‧閘極電極
12‧‧‧源極電極
13‧‧‧汲極電極
20‧‧‧MOSFET領域
50‧‧‧超接合MOSFET
51‧‧‧元件活性部的要部剖面圖

Claims (8)

  1. 一種半導體裝置，係於第1導電型的汲極層的第1主面上具有延伸於垂直方向之互相平行的複數的pn接合，且設有被該pn接合夾著的第1導電型的漂移領域與第2導電型的間隔領域係交替地接觸排列的並列pn層，且在前述並列pn層的第1主面側具有MOS閘極構造，在前述並列pn層與前述汲極層之間設有第1導電型的第1緩衝層，前述第1緩衝層的雜質濃度係比前述漂移領域還低濃度，其特徵為：前述並列pn層內的前述間隔領域的至少一個係被置換成比前述漂移領域的雜質濃度還低濃度的第1導電型領域。
  2. 如申請專利範圍第1項之半導體裝置，其中，在前述第1緩衝層與前述汲極層之間具備雜質濃度比前述漂移領域高濃度的第1導電型的第2緩衝層。
  3. 如申請專利範圍第2項之半導體裝置，其中，前述並列pn層的載子壽命比前述第2緩衝層更短。
  4. 如申請專利範圍第3項之半導體裝置，其中，前述第1緩衝層的載子壽命比前述第2緩衝層更短。
  5. 如申請專利範圍第3或4項之半導體裝置，其中，前述第2緩衝層未被調整壽命。
  6. 一種半導體裝置的製造方法，該半導體裝置係具備：第1導電型的高濃度緩衝層，其係雜質濃度比設在第 1導電型的汲極層的第1主面上的漂移領域還高濃度；第1導電型的低濃度緩衝層，其係設在前述高濃度緩衝層上，比前述漂移領域的雜質濃度還低濃度；及並列pn層，其係設在前述低濃度緩衝層上，交替地重複配置第1導電型的漂移領域與第2導電型的間隔領域，前述間隔領域的至少一個被置換成比前述漂移領域的雜質濃度還低濃度的第1導電型領域，其特徵為：包含：藉由重金屬的添加或荷電粒子的照射來使前述並列pn層的載子壽命形成比前述高濃度緩衝層還短之工程。
  7. 一種半導體裝置的製造方法，該半導體裝置係於第1導電型的汲極層的第1主面上具備交替地重複配置第1導電型的漂移領域與第2導電型的間隔領域之並列pn層，前述間隔領域的至少一個被置換成比前述漂移領域的雜質濃度還低濃度的第1導電型領域，其特徵係包含：在前述汲極層的第1主面上形成雜質濃度比前述漂移領域還高濃度的第1導電型的高濃度緩衝層之工程；在前述高濃度緩衝層上形成比前述漂移領域的雜質濃度還低濃度的第1導電型的低濃度緩衝層之工程；在前述低濃度緩衝層上形成前述並列pn層之工程；及 從前述並列pn層側進行重金屬的添加或荷電粒子的照射，藉此使前述並列pn層的載子壽命形成比前述高濃度緩衝層的載子壽命還短之工程。
  8. 一種半導體裝置的製造方法，該半導體裝置係於第1導電型的汲極層的第1主面上具備交替地重複配置第1導電型的漂移領域與第2導電型的間隔領域之並列pn層，前述間隔領域的至少一個被置換成比前述漂移領域的雜質濃度還低濃度的第1導電型領域，其特徵係包含：在半導體基板的正面側形成前述並列pn層之工程；在前述半導體基板的正面側，於前述並列pn層上形成元件構造之工程；在前述半導體基板的背面側形成比前述漂移領域的雜質濃度還低濃度的第1導電型的低濃度緩衝層之工程；及在前述半導體基板的背面側之比前述低濃度緩衝層更淺的位置形成雜質濃度比前述漂移領域還高濃度的第1導電型的高濃度緩衝層之工程；及從前述高濃度緩衝層側進行重金屬的添加或荷電粒子的照射，藉此使前述並列pn層的載子壽命形成比前述高濃度緩衝層的載子壽命還短之工程。
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