CN103219249A - 一种镀钯镀金的双镀层键合铜丝的制造方法 - Google Patents
一种镀钯镀金的双镀层键合铜丝的制造方法 Download PDFInfo
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Abstract
本发明公开了一种双镀层键合铜丝,所述铜丝具有三层结构,最内层为在高纯铜中添加了微量金属元素的铜芯,在该铜芯的表面镀有纯钯导电层,在纯钯导电层的表面镀有纯金导电层;其中所述微量金属元素为锡、镁和铝。
Description
技术领域
本发明属于半导体集成电路芯片封装领域,具体来说涉及一种半导体集成电路芯片键合用双镀层铜丝的制造方法。
背景技术
半导体集成电路制造完成后所得的芯片虽然已经具有特定的功能,但是要实现该功能,必须通过与外部电子元件的连接。而半导体集成电路芯片需要经过与封装体的键合工序,最终得到芯片封装,如此才能通过封装的引脚与外部电子元件连接。在芯片与封装体的键合工艺中,都通过键合线将芯片上的焊盘与封装体的引脚进行电连接。所以键合线是实现芯片功能必不可少的材料。现有技术中,中国授权专利CN102130067B公开了一种表面镀钯键合铜丝,这种镀钯键合铜丝由于采用价格相对低廉的钯作为镀层,因此相对于镀金键合铜丝来说,其制造成本以及应用成本相对更低,但是这种镀钯键合铜丝由于采用金属钯作为镀层,因此相对于镀金键合铜丝来说,其导电性能存在不足。中国授权实用新型专利CN201788710U公开了一种高导光亮复合镀银铜丝,其采用金属银作为铜丝的镀层,由于银的优良导电性能以及其相对适中的价格,因此其能在一定范围内取代镀钯键合铜丝。但是这种镀银键合铜丝同样存在不足,例如延展性不好,在加工过程中容易被破坏。
而且,无论是镀钯键合铜丝还是镀银键合铜丝,相对于纯金来说,由于钯或银的导电性能仍存在不足,例如电阻率较高,这导致其在体积非常小的芯片封装中所产生的热量无法忽视。因而有必要研究一种性能优异的替代键合丝。
发明内容:
本发明要解决的技术问题是提供一种具有双镀层的键合铜丝,以克服现有镀钯或镀银键合铜丝导电性能较差,并且延展性能不好的缺陷。
本发明提出的双镀层键合铜丝具有三层结构,最内层为在高纯铜中添加了微量金属元素的铜芯,在该铜芯的表面镀有纯钯导电层,在纯钯导电层的表面镀有纯金导电层;其中所述微量金属元素为锡、镁和铝。
其中,所述高纯铜的纯度大于99.9995%,以所述双镀层键合铜丝为100重量份,即100wt%计,其中铜芯中纯铜的含量为92.6~93.8wt%,微量元素总体含量为1wt%,纯钯导电层的含量为2.7~5.4wt%,纯金导电层的含量为1~2.5wt%。
其中,所述微量金属元素的总含量为1wt%,包括0.5wt%的锡、0.3wt%的镁以及0.2wt%的铝。
其中,所述纯钯的纯度大于99.99%,所述纯金的纯度大于99.99%。
附图说明:
图1为本发明提出的双镀层结构的键合铜丝。
具体实施方式:
下面通过具体实施方式对本发明提出的双镀层键合铜丝的制造方法进行详细说明。
实施例
如图1所示,本发明提出的双镀层键合铜丝包括铜芯1、镀钯层2、镀金层3。其中,铜芯1为采用纯度大于99.9995%的高纯铜为原料,通过添加锡、镁和铝进行单晶熔炼而成;镀钯层2采用纯度大于99.99%的金属钯,通过电镀工艺将其镀在铜芯的表面上;镀金层3采用纯度大于99.99%的金属金,通过电镀工艺将其电镀在镀钯层2的表面上。其中,以最终制得的含有镀钯层和镀金层的双镀层键合铜丝为100重量份计,即100wt%计,铜芯中纯铜的含量为92.6~93.8wt%,纯钯导电层的含量为2.7~5.4wt%、纯金导电层的含量为1~2.5wt%,锡的含量为0.5wt%、镁的含量为0.3wt%、铝的含量为0.2wt%。
下面介绍制造本发明双镀层键合铜丝的具体工艺方法,该方法以先后次序依次包括如下步骤:
(1)以最终制得的含有镀钯层和镀金层的双镀层键合铜丝为100重量份计,即100wt%计,将92.6~93.8wt%的纯度大于99.9995%的高纯铜置入熔炼炉熔化,并加入0.5wt%的锡、0.3wt%的镁、0.2wt%的铝,经过单晶熔炼拉伸成铜芯,铜芯的直径大约为8mm,并且该铜芯的纵向和横向晶粒数均为1个;
(2)将所述铜芯进行粗拔以制得直径大约为3-4mm的铜丝后,对所述铜丝进行退火,退火温度大约为450-500摄氏度,退火时间大约为20-60分钟,退火后进行水冷;
(3)电镀纯钯导电层:在退火后铜芯表面上电镀2.7~5.4wt%的纯钯,以形成纯钯导电层,所述纯钯的纯度大于99.99%;
(4)第一次精拔:将完成步骤(3)的电镀有纯钯导电层的铜丝,精拔成直径大约为1-2mm的镀钯铜丝;
(5)第一次热退火:对完成步骤(4)的镀钯铜丝进行热退火,其中热退火温度大约为450-500摄氏度,时间大约为20-60分钟;
(6)电镀纯金导电层:在镀钯铜丝的表面上电镀1~2.5wt%的纯金,以形成纯金导电层,所述纯金的纯度大于99.99%;
(7)第二次精拔:将完成步骤(5)的铜丝精拔成直径大约为15-25微米的双镀层键合铜丝;
(8)第二次热退火:对完成步骤(6)的双镀层键合铜丝进行热退火,其中热退火温度大约为450-500摄氏度,时间大约为20-60分钟;
(9)清洗:对完成步骤(7)的双镀层键合铜丝进行表面清洗,采用酸性溶液先对其进行一次清洗,然后采用去离子水进行二次清洗;
(10)将清洗干净的镀金键合铜丝烘干。
其中,步骤(4)中优选的直径大小为1.5mm,步骤(5)和(8)中优选的热退火温度大约为480摄氏度,时间大约为30分钟。
本发明提出的双镀层键合铜丝由于采用先镀钯后镀金的双镀层结构,因此其兼具了优良的延展性和优异的导电性。并且通过两次精拔的工艺,使得在铜丝的拉拔过程中逐渐变细,避免了一次拉拔工艺中,由于从较大直径(如本发明的8mm)一次拉拔成微细直径(如本发明的15-25微米)的过程中,容易使得铜丝被拉断的问题,因此可以减少生产过程中不必要的损耗。
以上实施方式已经对本发明进行了详细的介绍,但上述实施方式并非为了限定本发明的范围,本发明的保护范围由所附的权利要求限定。
Claims (5)
1.一种双镀层键合铜丝的制造方法,该方法以先后次序依次包括如下步骤:
(1)在高纯铜中加入微量金属元素锡、镁和铝,以制得铜芯;
(2)在所述铜芯的表面上电镀金属钯,已形成镀钯导电层;
(3)在镀钯导电层的表面上电镀金属金,以形成镀金导电层;
(4)对完成镀钯和镀金后的铜丝进行清洗,以形成具有镀钯导电层和镀金导电层的双镀层键合铜丝。
2.一种双镀层键合铜丝的制造方法,该方法以先后次序依次包括如下步骤:
(1)以最终制得的含有镀钯层和镀金层的双镀层键合铜丝为100重量份计,即100wt%计,将92.6~93.8wt%的纯度大于99.9995%的高纯铜置入熔炼炉熔化,并加入0.5wt%的锡、0.3wt%的镁、0.2wt%的铝,经过单晶熔炼拉伸成铜芯,铜芯的直径大约为8mm,并且该铜芯的纵向和横向晶粒数均为1个;
(2)将所述铜芯进行粗拔以制得直径大约为3-4mm的铜丝后,对所述铜丝进行退火,退火温度大约为450-500摄氏度,退火时间大约为20-60分钟,退火后进行水冷;
(3)电镀纯钯导电层:在退火后铜芯表面上电镀2.7~5.4wt%的纯钯,以形成纯钯导电层,所述纯钯的纯度大于99.99%;
(4)第一次精拔:将完成步骤(3)的电镀有纯钯导电层的铜丝,精拔成直径大约为1-2mm的镀钯铜丝;
(5)第一次热退火:对完成步骤(4)的镀钯铜丝进行热退火,其中热退火温度大约为450-500摄氏度,时间大约为20-60分钟;
(6)电镀纯金导电层:在镀钯铜丝的表面上电镀1~2.5wt%的纯金,以形成纯金导电层,所述纯金的纯度大于99.99%;
(7)第二次精拔:将完成步骤(5)的铜丝精拔成直径大约为15-25微米的双镀层键合铜丝;
(8)第二次热退火:对完成步骤(6)的双镀层键合铜丝进行热退火,其中热退火温度大约为450-500摄氏度,时间大约为20-60分钟;
(9)清洗:对完成步骤(7)的双镀层键合铜丝进行表面清洗,采用酸性溶液先对其进行一次清洗,然后采用去离子水进行二次清洗;
(10)将清洗干净的镀金键合铜丝烘干。
其中,步骤(4)中优选的直径大小为1.5mm,步骤(5)和(8)中优选的热退火温度大约为480摄氏度,时间大约为30分钟。
3.如权利要求2所述的双镀层键合铜丝,其特征在于:
所述高纯铜的纯度大于99.9995%,以所述双镀层键合铜丝为100重量份,即100wt%计,其中铜芯中纯铜的含量为92.6~93.8wt%,微量元素总体含量为1wt%,纯钯导电层的含量为2.7~5.4wt%,纯金导电层的含量为1~2.5wt%。
4.如权利要求2-3任意之一所述的双镀层键合铜丝,其特征在于:
所述微量金属元素的总含量为1wt%,包括0.5wt%的锡、0.3wt%的镁以及0.2wt%的铝。
5.如权利要求2-4任意之一所述的双镀层键合铜丝,其特征在于:
所述纯钯的纯度大于99.99%,所述纯金的纯度大于99.99%。
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