CN103219248B - 一种镀金键合铜丝的制造方法 - Google Patents

一种镀金键合铜丝的制造方法 Download PDF

Info

Publication number
CN103219248B
CN103219248B CN201310065496.6A CN201310065496A CN103219248B CN 103219248 B CN103219248 B CN 103219248B CN 201310065496 A CN201310065496 A CN 201310065496A CN 103219248 B CN103219248 B CN 103219248B
Authority
CN
China
Prior art keywords
copper
copper wire
gold
time
gold plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201310065496.6A
Other languages
English (en)
Other versions
CN103219248A (zh
Inventor
吕燕翔
居勤坤
史仁龙
万传友
彭芳美
周国忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LIYANG HONGXIANG MACHINERY MANUFACTURING Co Ltd
Original Assignee
LIYANG HONGXIANG MACHINERY MANUFACTURING Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LIYANG HONGXIANG MACHINERY MANUFACTURING Co Ltd filed Critical LIYANG HONGXIANG MACHINERY MANUFACTURING Co Ltd
Priority to CN201310065496.6A priority Critical patent/CN103219248B/zh
Publication of CN103219248A publication Critical patent/CN103219248A/zh
Application granted granted Critical
Publication of CN103219248B publication Critical patent/CN103219248B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/43848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

本发明公开了一种制造镀金键合铜丝的方法，以克服现有镀金键合铜丝生产成本高的缺陷，通过多次精拔的方法，减少铜丝断线的出现。本发明提出的镀金键合铜丝的制造方法总体来说是以纯度大于99.9995％的高纯铜丝为芯体，在该芯片的表面镀有纯金导电层，其中铜芯的含量为93.4~98.3wt%，纯金导电层的含量为1.7wt％~6.6wt％，其余为铜。

Description

一种镀金键合铜丝的制造方法
技术领域
本发明属于半导体集成电路芯片封装领域，具体来说涉及一种半导体集成电路芯片键合用镀金铜丝的制造方法。
背景技术
半导体集成电路制造完成后所得的芯片虽然已经具有特定的功能，但是要实现该功能，必须通过与外部电子元件的连接。而半导体集成电路芯片需要经过与封装体的键合工序，最终得到芯片封装，如此才能通过封装的引脚与外部电子元件连接。在芯片与封装体的键合工艺中，都通过键合线将芯片上的焊盘与封装体的引脚进行电连接。所以键合线是实现芯片功能必不可少的材料。因为纯金的导电性能优异，键合线多由纯金制成。在现有技术中镀金键合铜丝的制造方法一般都是粗拔后直接一次精拔成型的工艺，这种工艺由于仅采用一次精拔，铜丝由很大的直径一次被拉拔成很细的直径，直径的减小过程过于激烈，因此容易造成断线，而随着黄金资源的日益稀缺、价格持续攀升，制造过程中出现的铜丝断线将导致制造成本的大幅上升。
发明内容：
本发明要解决的技术问题是提供一种制造镀金键合铜丝的方法，以克服现有镀金键合铜丝生产成本高的缺陷，通过多次精拔的方法，减少铜丝断线的出现。
本发明提出的镀金键合铜丝的制造方法总体来说是以纯度大于99.9995％的高纯铜丝为芯体，在该芯片的表面镀有纯金导电层，其中铜芯的含量为93.4～98.3wt％，纯金导电层的含量为1.7wt％～6.6wt％，其余为铜。
下面具体介绍本发明的镀金键合铜丝的制造方法，其依次包括如下步骤：
本发明镀金键合铜丝的制造方法，按先后次序依次包括以下步骤：
(1)提取高纯铜：以国家标准1号纯铜为原料，提取纯度大于99.9995％的高纯铜；将高纯铜连铸得到直径大约为8mm的高纯铜棒，该高纯铜棒的纵向和横向晶粒数均为1个；
(2)将直径大约为8mm的高纯铜棒进行粗拔以制得直径大约为3-4mm的铜丝后，对所述铜丝进行退火，退火温度大约为450-500摄氏度，退火时间大约为20-60分钟，退火后进行水冷；
(3)电镀前的称重准备：按照重量百分比计，选取93.4～98.3wt％的铜作为铜芯，将1.7wt％～6.6wt％的纯金分成两份，其中第一份为1～4.5wt％，第二份为0.7-2.1wt％，其中，纯金的纯度为大于99.99％；
(4)第一次电镀纯金保护层：将退火后的按重量百分比计93.4～98.3wt％的铜作为铜芯，在所述铜芯的表面上电镀第一份1～4.5wt％的纯金；
(5)第一次精拔：将完成步骤(4)的电镀有纯金保护层的铜丝，精拔成直径大约为1-1.5mm的镀金键合铜丝；
(6)第一次热退火：对完成步骤(5)的镀金键合铜丝进行热退火，其中热退火温度大约为450-500摄氏度，时间大约为20-60分钟；
(7)第二次电镀纯金保护层：在完成步骤(6)的键合铜丝的表面上电镀第二份0.7-2.1wt％的纯金；
(8)第二次精拔：将完成步骤(7)的镀金键合铜丝精拔成直径大约为15-25微米的镀金键合铜丝；
(9)第二次热退火：对完成步骤(8)的镀金键合铜丝进行热退火，其中热退火温度大约为450-500摄氏度，时间大约为20-60分钟；
(10)清洗：对完成步骤(9)的镀金键合铜丝进行表面清洗，采用酸性溶液先对其进行一次清洗，然后采用去离子水进行二次清洗；
(11)将清洗干净的镀金键合铜丝烘干。
具体实施方式：
下面通过具体实施方式对本发明镀金键合铜丝的制造方法进行详细说明。
实施例1
(1)提取高纯铜：以国家标准1号纯铜为原料，提取纯度大于99.9995％的高纯铜；将高纯铜连铸得到直径大约为8mm的高纯铜棒，该高纯铜棒的纵向和横向晶粒数均为1个；
(2)将直径大约为8mm的高纯铜棒进行粗拔以制得直径大约为3-4mm的铜丝后，对所述铜丝进行退火，退火温度大约为450-500摄氏度，退火时间大约为20-60分钟，退火后进行水冷；
(3)电镀前的称重准备：按照重量百分比计，选取93.4～98.3wt％的铜作为铜芯，将1.7wt％～6.6wt％的纯金分成两份，其中第一份为1～4.5wt％，第二份为0.7-2.1wt％，其中，纯金的纯度为大于99.99％；
(4)第一次电镀纯金保护层：将退火后的按重量百分比计93.4～98.3wt％的铜作为铜芯，在所述铜芯的表面上电镀第一份1～4.5wt％的纯金；
(5)第一次精拔：将完成步骤(4)的电镀有纯金保护层的铜丝，精拔成直径大约为1-1.5mm的镀金键合铜丝；
(6)第一次热退火：对完成步骤(5)的镀金键合铜丝进行热退火，其中热退火温度大约为450-500摄氏度，时间大约为20-60分钟；
(7)第二次电镀纯金保护层：在完成步骤(6)的键合铜丝的表面上电镀第二份0.7-2.1wt％的纯金；
(8)第二次精拔：将完成步骤(7)的镀金键合铜丝精拔成直径大约为15-25微米的镀金键合铜丝；
(9)第二次热退火：对完成步骤(8)的镀金键合铜丝进行热退火，其中热退火温度大约为450-500摄氏度，时间大约为20-60分钟；
(10)清洗：对完成步骤(9)的镀金键合铜丝进行表面清洗，采用酸性溶液先对其进行一次清洗，然后采用去离子水进行二次清洗；
(11)将清洗干净的镀金键合铜丝烘干。
实施例2
下面介绍本发明提出的镀金键合铜丝的制造方法的最优实施例，所述方法按先后次序依次包括以下步骤：
(1)提取高纯铜：以国家标准1号纯铜为原料，提取纯度大于99.9995％的高纯铜；将高纯铜连铸得到直径大约为8mm的高纯铜棒，该高纯铜棒的纵向和横向晶粒数均为1个；
(2)将直径大约为8mm的高纯铜棒进行粗拔以制得直径大约为3-4mm的铜丝后，对所述铜丝进行退火，退火温度大约为450-500摄氏度，退火时间大约为20-60分钟，退火后进行水冷；
(3)电镀前的称重准备：按照重量百分比计，选取93.4～98.3wt％的铜作为铜芯，将1.7wt％～6.6wt％的纯金分成两份，其中第一份为1～4.5wt％，第二份为0.7-2.1wt％，其中，纯金的纯度为大于99.99％；
(4)第一次电镀纯金保护层：将退火后的按重量百分比计93.4～98.3wt％的铜作为铜芯，在所述铜芯的表面上电镀第一份1～4.5wt％的纯金；
(5)第一次精拔：将完成步骤(4)的电镀有纯金保护层的铜丝，精拔成直径大约为1.5mm的镀金键合铜丝；
(6)第一次热退火：对完成步骤(5)的镀金键合铜丝进行热退火，其中热退火温度大约为480摄氏度，时间大约为40分钟；
(7)第二次电镀纯金保护层：在完成步骤(6)的键合铜丝的表面上电镀第二份0.7-2.1wt％的纯金；
(8)第二次精拔：将完成步骤(7)的镀金键合铜丝精拔成直径大约为15-25微米的镀金键合铜丝；
(9)第二次热退火：对完成步骤(8)的镀金键合铜丝进行热退火，其中热退火温度大约为480摄氏度，时间大约为40分钟；
(10)清洗：对完成步骤(9)的镀金键合铜丝进行表面清洗，采用酸性溶液先对其进行一次清洗，然后采用去离子水进行二次清洗；
(11)将清洗干净的镀金键合铜丝烘干。
本发明镀金键合铜丝的制造方法采用粗拔-第一次电镀-第一次精拔-第二次电镀-第二次精拔的工艺，从而使得镀金保护层的材质更加均匀、致密、镀金层结合强度大幅提高。并且通过两次精拔的工艺，使得在铜丝的拉拔过程中逐渐变细，避免了一次拉拔工艺中，由于从较大直径(如本发明的8mm)一次拉拔成微细直径(如本发明的15-25微米)的过程中，容易使得铜丝被拉断的问题，因此可以减少生产过程中不必要的损耗。
以上实施方式已经对本发明进行了详细的介绍，但上述实施方式并非为了限定本发明的范围，本发明的保护范围由所附的权利要求限定。

Claims (1)

1.一种镀金键合铜丝的制造方法，按先后次序依次包括以下步骤：
(1)提取高纯铜：以国家标准1号纯铜为原料，提取纯度大于99.9995％的高纯铜；将高纯铜连铸得到直径为8mm的高纯铜棒，该高纯铜棒的纵向和横向晶粒数均为1个；
(2)将直径为8mm的高纯铜棒进行粗拔以制得直径为3-4mm的铜丝后，对所述铜丝进行退火，退火温度为450-500摄氏度，退火时间为20-60分钟，退火后进行水冷；
(3)电镀前的称重准备：按照重量百分比计，选取93.4～98.3wt％的铜作为铜芯，将1.7wt％～6.6wt％的纯金分成两份，其中第一份为1～4.5wt％，第二份为0.7-2.1wt％，其中，纯金的纯度为大于99.99％；
(4)第一次电镀纯金保护层：将退火后的按重量百分比计93.4～98.3wt％的铜作为铜芯，在所述铜芯的表面上电镀第一份1～4.5wt％的纯金；
(5)第一次精拔：将完成步骤(4)的电镀有纯金保护层的铜丝，精拔成直径为1-1.5mm的镀金键合铜丝；
(6)第一次热退火：对完成步骤(5)的镀金键合铜丝进行热退火，其中热退火温度为450-500摄氏度，时间为20-60分钟；
(7)第二次电镀纯金保护层：在完成步骤(6)的键合铜丝的表面上电镀第二份0.7-2.1wt％的纯金；
(8)第二次精拔：将完成步骤(7)的镀金键合铜丝精拔成直径为15-25微米的镀金键合铜丝；
(9)第二次热退火：对完成步骤(8)的镀金键合铜丝进行热退火，其中热退火温度为450-500摄氏度，时间为20-60分钟；
(10)清洗：对完成步骤(9)的镀金键合铜丝进行表面清洗，采用酸性溶液先对其进行一次清洗，然后采用去离子水进行二次清洗；
(11)将清洗干净的镀金键合铜丝烘干。
CN201310065496.6A 2013-03-01 2013-03-01 一种镀金键合铜丝的制造方法 Expired - Fee Related CN103219248B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310065496.6A CN103219248B (zh) 2013-03-01 2013-03-01 一种镀金键合铜丝的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310065496.6A CN103219248B (zh) 2013-03-01 2013-03-01 一种镀金键合铜丝的制造方法

Publications (2)

Publication Number Publication Date
CN103219248A CN103219248A (zh) 2013-07-24
CN103219248B true CN103219248B (zh) 2015-11-25

Family

ID=48816933

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310065496.6A Expired - Fee Related CN103219248B (zh) 2013-03-01 2013-03-01 一种镀金键合铜丝的制造方法

Country Status (1)

Country Link
CN (1) CN103219248B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107488824A (zh) * 2017-06-27 2017-12-19 深圳市远思达成科技有限公司 一种具有石墨烯薄膜的键合铜丝的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1949492A (zh) * 2006-11-03 2007-04-18 宁波康强电子股份有限公司 一种键合铜丝及其制备方法
TW201207129A (en) * 2010-08-05 2012-02-16 jin-yong Wang Cooper bonding wire used in encapsulation and manufacturing method thereof
CN102361026A (zh) * 2011-10-19 2012-02-22 广东佳博电子科技有限公司 一种具有防氧化功能的铜基键合丝
CN102509724A (zh) * 2011-10-19 2012-06-20 广东佳博电子科技有限公司 一种铜基键合丝及制备方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59155161A (ja) * 1983-02-23 1984-09-04 Daiichi Denko Kk 半導体素子のボンデイング用ワイヤ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1949492A (zh) * 2006-11-03 2007-04-18 宁波康强电子股份有限公司 一种键合铜丝及其制备方法
TW201207129A (en) * 2010-08-05 2012-02-16 jin-yong Wang Cooper bonding wire used in encapsulation and manufacturing method thereof
CN102361026A (zh) * 2011-10-19 2012-02-22 广东佳博电子科技有限公司 一种具有防氧化功能的铜基键合丝
CN102509724A (zh) * 2011-10-19 2012-06-20 广东佳博电子科技有限公司 一种铜基键合丝及制备方法

Also Published As

Publication number Publication date
CN103219248A (zh) 2013-07-24

Similar Documents

Publication Publication Date Title
CN103219249B (zh) 一种镀钯镀金的双镀层键合铜丝的制造方法
CN103219246B (zh) 一种镀钯镀银的双镀层键合铜丝的制造方法
CN109266874B (zh) 一种铜合金键合引线的制备方法
CN101667566B (zh) 一种银基覆金的键合丝线的制造方法
CN104388861B (zh) 一种多晶串联led用微细银金合金键合线的制造方法
CN103219312B (zh) 一种镀钯镀金的双镀层键合铜丝
CN103199073B (zh) 银钯合金单晶键合丝及其制造方法
CN106992164B (zh) 一种微电子封装用铜合金单晶键合丝及其制备方法
CN103779308A (zh) 金银钯合金单晶键合丝及其制造方法
CN109628793A (zh) 一种铜镀钯镀镍再镀金键合丝及其制备方法
CN104377185A (zh) 镀金银钯合金单晶键合丝及其制造方法
CN109449133A (zh) 一种铜镀纯镍键合丝及其制备方法
CN103219247B (zh) 一种镀银键合铜丝的制造方法
CN103219248B (zh) 一种镀金键合铜丝的制造方法
CN103219245B (zh) 一种镀钯键合铜丝的制造方法
CN202662472U (zh) 银镍/铜镍复合电触头
CN103219311B (zh) 一种镀钯镀银的双镀层键合铜丝
CN103560120B (zh) 一种化学法镀钯铜键合丝及其制备方法
CN103556140A (zh) 一种用于化学法制备镀钯铜键合丝的镀钯液
CN106244844A (zh) 一种半导体用的铜线及其制备方法
CN109628790A (zh) 一种高纯金银钯铂合金键合引线及其制备方法
CN103996668A (zh) 银镧钙合金键合丝及其制造方法
CN101621003A (zh) 高压二极管新型生产工艺
CN103117108B (zh) 一种含有乙酰柠檬酸三乙酯的导电浆料
CN104022095A (zh) 镀金银镧钙合金键合丝及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20151125

Termination date: 20160301