CN103219245B - 一种镀钯键合铜丝的制造方法 - Google Patents
一种镀钯键合铜丝的制造方法 Download PDFInfo
- Publication number
- CN103219245B CN103219245B CN201310065255.1A CN201310065255A CN103219245B CN 103219245 B CN103219245 B CN 103219245B CN 201310065255 A CN201310065255 A CN 201310065255A CN 103219245 B CN103219245 B CN 103219245B
- Authority
- CN
- China
- Prior art keywords
- palladium
- copper wire
- copper
- time
- plated bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
- H01L2224/432—Mechanical processes
- H01L2224/4321—Pulling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
- H01L2224/438—Post-treatment of the connector
- H01L2224/43848—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45644—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/45664—Palladium (Pd) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Abstract
本发明公开了一种制造镀钯键合铜丝的方法,以克服现有镀金键合铜丝生产成本高、电镀层硬度低不耐摩擦的缺陷,通过镀钯层替代镀金层,从而得到低成本的镀钯键合铜丝,并且通过多次精拔的方法,减少铜丝断线的出现。
Description
技术领域
本发明属于半导体集成电路芯片封装领域,具体来说涉及一种半导体集成电路芯片键合用镀钯铜丝的制造方法。
背景技术
半导体集成电路制造完成后所得的芯片虽然已经具有特定的功能,但是要实现该功能,必须通过与外部电子元件的连接。而半导体集成电路芯片需要经过与封装体的键合工序,最终得到芯片封装,如此才能通过封装的引脚与外部电子元件连接。在芯片与封装体的键合工艺中,都通过键合线将芯片上的焊盘与封装体的引脚进行电连接。所以键合线是实现芯片功能必不可少的材料。现有技术中,因为纯金的导电性能优异,键合线多由纯金制成。但随着黄金资源的日益稀缺、价格持续攀升,封装成本大幅上升。为此业内技术人员研发出镀金铜丝产品来替代金丝的产品。该镀金铜丝是通过在铜芯上镀金来形成,这种产品兼顾了金的优异导电性能,而且采用铜来作为芯体,从而可以减少金的用量,节约了成本。然而,镀金键合铜丝虽然价格低廉,且在拉伸、剪切强度和延展等方面的性能优于金丝,但随着芯片行业的快速小型化、多引脚高密度化,镀金键合铜丝越来越无法满足需求。这是因为铜的导电性能虽然良好,但相对于金来说,其电阻率较高,这导致其在体积非常小的芯片封装中所产生的热量无法忽视。因而有必要研究一种即经济又性能优异的替代键合丝。
针对上述问题,业内研发了一种镀钯键合铜丝,因为钯的成本要比金低得多,并且钯在高温、高湿或硫化物含量高的空气中性能稳定,能耐酸的侵蚀,因此镀钯键合铜丝的能够在既经济又高效的满足业内对键合丝的要求。例如中国授权专利CN101707194A公开了一种镀钯键合铜丝的制造方法,其中公开的镀钯键合铜丝的制造方法采用粗拔后直接一次精拔成型的工艺,这种工艺由于仅采用一次精拔,铜丝由很大的直径一次被拉拔成很细的直径,直径的减小过程过于激烈,因此容易造成断线。
发明内容:
本发明要解决的技术问题是提供一种制造镀钯键合铜丝的方法,以克服现有镀金键合铜丝生产成本高、电镀层硬度低不耐摩擦的缺陷,通过镀钯层替代镀金层,从而得到低成本的镀钯键合铜丝,并且通过多次精拔的方法,减少铜丝断线的出现。
本发明提出的镀钯键合铜丝的制造方法总体来说是以纯度大于99.9995%的高纯铜丝为芯体,在该芯片的表面镀有纯钯导电层,其中铜芯的含量为92.6~96.8wt%,纯钯导电层的含量为3.2wt%~7.4wt%,其余为铜。
下面具体介绍本发明的镀钯键合铜丝的制造方法,其依次包括如下步骤:
本发明镀钯键合铜丝的制造方法,按先后次序依次包括以下步骤:
(1)提取高纯铜:以国家标准1号纯铜为原料,提取纯度大于99.9995%的高纯铜;将高纯铜连铸得到直径大约为8mm的高纯铜棒,该高纯铜棒的纵向和横向晶粒数均为1个;
(2)将直径大约为8mm的高纯铜棒进行粗拔以制得直径大约为3-4mm的铜丝后,对所述铜丝进行退火,退火温度大约为450-500摄氏度,退火时间大约为20-60分钟,退火后进行水冷;
(3)电镀前的称重准备:按照重量百分比计,选取92.6~96.8wt%的铜作为铜芯,将2.7~8.9wt%的纯钯分成两份,其中第一份为1.8~5.6wt%,第二份为1.4-2.8wt%,其中,纯钯的纯度为大于99.99%;
(4)第一次电镀纯钯保护层:将退火后的按重量百分比计92.6~96.8wt%的铜作为铜芯,在所述铜芯的表面上电镀第一份1.8~5.6wt%的纯钯;
(5)第一次精拔:将完成步骤(4)的电镀有纯钯保护层的铜丝,精拔成直径大约为1-1.5mm的镀钯键合铜丝;
(6)第一次热退火:对完成步骤(5)的镀钯键合铜丝进行热退火,其中热退火温度大约为450-500摄氏度,时间大约为20-60分钟;
(7)第二次电镀纯钯保护层:在完成步骤(6)的键合铜丝的表面上电镀第二份1.4-2.8wt%的纯钯;
(8)第二次精拔:将完成步骤(7)的镀钯键合铜丝精拔成直径大约为15-25微米的镀钯键合铜丝;
(9)第二次热退火:对完成步骤(8)的镀钯键合铜丝进行热退火,其中热退火温度大约为450-500摄氏度,时间大约为20-60分钟;
(10)清洗:对完成步骤(9)的镀钯键合铜丝进行表面清洗,采用酸性溶液先对其进行一次清洗,然后采用去离子水进行二次清洗;
(11)将清洗干净的镀钯键合铜丝烘干。
具体实施方式:
下面通过具体实施方式对本发明镀钯键合铜丝的制造方法进行详细说明。
实施例1
(1)提取高纯铜:以国家标准1号纯铜为原料,提取纯度大于99.9995%的高纯铜;将高纯铜连铸得到直径大约为8mm的高纯铜棒,该高纯铜棒的纵向和横向晶粒数均为1个;
(2)将直径大约为8mm的高纯铜棒进行粗拔以制得直径大约为3-4mm的铜丝后,对所述铜丝进行退火,退火温度大约为450-500摄氏度,退火时间大约为20-60分钟,退火后进行水冷;
(3)电镀前的称重准备:按照重量百分比计,选取92.6~96.8wt%的铜作为铜芯,将2.7~8.9wt%的纯钯分成两份,其中第一份为1.8~5.6wt%,第二份为1.4-2.8wt%,其中,纯钯的纯度为大于99.99%;
(4)第一次电镀纯钯保护层:将退火后的按重量百分比计92.6~96.8wt%的铜作为铜芯,在所述铜芯的表面上电镀第一份1.8~5.6wt%的纯钯;
(5)第一次精拔:将完成步骤(4)的电镀有纯钯保护层的铜丝,精拔成直径大约为1-1.5mm的镀钯键合铜丝;
(6)第一次热退火:对完成步骤(5)的镀钯键合铜丝进行热退火,其中热退火温度大约为450-500摄氏度,时间大约为20-60分钟;
(7)第二次电镀纯钯保护层:在完成步骤(6)的键合铜丝的表面上电镀第二份1.4-2.8wt%的纯钯;
(8)第二次精拔:将完成步骤(7)的镀钯键合铜丝精拔成直径大约为15-25微米的镀钯键合铜丝;
(9)第二次热退火:对完成步骤(8)的镀钯键合铜丝进行热退火,其中热退火温度大约为450-500摄氏度,时间大约为20-60分钟;
(10)清洗:对完成步骤(9)的镀钯键合铜丝进行表面清洗,采用酸性溶液先对其进行一次清洗,然后采用去离子水进行二次清洗;
(11)将清洗干净的镀钯键合铜丝烘干。
实施例2
下面介绍本发明提出的镀钯键合铜丝的制造方法的最优实施例,所述方法按先后次序依次包括以下步骤:
(1)提取高纯铜:以国家标准1号纯铜为原料,提取纯度大于99.9995%的高纯铜;将高纯铜连铸得到直径大约为8mm的高纯铜棒,该高纯铜棒的纵向和横向晶粒数均为1个;
(2)将直径大约为8mm的高纯铜棒进行粗拔以制得直径大约为3-4mm的铜丝后,对所述铜丝进行退火,退火温度大约为450-500摄氏度,退火时间大约为20-60分钟,退火后进行水冷;
(3)电镀前的称重准备:按照重量百分比计,选取92.6~96.8wt%的铜作为铜芯,将2.7~8.9wt%的纯钯分成两份,其中第一份为1.8~5.6wt%,第二份为1.4-2.8wt%,其中,纯钯的纯度为大于99.99%;
(4)第一次电镀纯钯保护层:将退火后的按重量百分比计92.6~96.8wt%的铜作为铜芯,在所述铜芯的表面上电镀第一份1.8~5.6wt%的纯钯;
(5)第一次精拔:将完成步骤(4)的电镀有纯钯保护层的铜丝,精拔成直径大约为1mm的镀钯键合铜丝;
(6)第一次热退火:对完成步骤(5)的镀钯键合铜丝进行热退火,其中热退火温度大约为480摄氏度,时间大约为30分钟;
(7)第二次电镀纯钯保护层:在完成步骤(6)的键合铜丝的表面上电镀第二份1.4-2.8wt%的纯钯;
(8)第二次精拔:将完成步骤(7)的镀钯键合铜丝精拔成直径大约为18微米的镀钯键合铜丝;
(9)第二次热退火:对完成步骤(8)的镀钯键合铜丝进行热退火,其中热退火温度大约为480摄氏度,时间大约为30分钟;
(10)清洗:对完成步骤(9)的镀钯键合铜丝进行表面清洗,采用酸性溶液先对其进行一次清洗,然后采用去离子水进行二次清洗;
(11)将清洗干净的镀钯键合铜丝烘干。
本发明镀钯键合铜丝的制造方法采用粗拔-第一次电镀-第一次精拔-第二次电镀-第二次精拔的工艺,从而使得镀钯保护层的材质更加均匀、致密、镀钯层结合强度大幅提高。并且通过两次精拔的工艺,使得在铜丝的拉拔过程中逐渐变细,避免了一次拉拔工艺中,由于从较大直径(如本发明的8mm)一次拉拔成微细直径(如本发明的15-25微米)的过程中,容易使得铜丝被拉断的问题,因此可以减少生产过程中不必要的损耗。
以上实施方式已经对本发明进行了详细的介绍,但上述实施方式并非为了限定本发明的范围,本发明的保护范围由所附的权利要求限定。
Claims (1)
1.一种镀钯键合铜丝的制造方法,按先后次序依次包括以下步骤:
(1)提取高纯铜:以国家标准1号纯铜为原料,提取纯度大于99.9995%的高纯铜;将高纯铜连铸得到直径为8mm的高纯铜棒,该高纯铜棒的纵向和横向晶粒数均为1个;
(2)将直径为8mm的高纯铜棒进行粗拔以制得直径为3-4mm的铜丝后,对所述铜丝进行退火,退火温度为450-500摄氏度,退火时间为20-60分钟,退火后进行水冷;
(3)电镀前的称重准备:按照重量百分比计,选取92.6~96.8wt%的铜作为铜芯,将2.7~8.9wt%的纯钯分成两份,其中第一份为1.8~5.6wt%,第二份为1.4-2.8wt%,其中,纯钯的纯度为大于99.99%;
(4)第一次电镀纯钯保护层:将退火后的按重量百分比计92.6~96.8wt%的铜作为铜芯,在所述铜芯的表面上电镀1.8~5.6wt%的纯钯;
(5)第一次精拔:将完成步骤(4)的电镀有纯钯保护层的铜丝,精拔成直径为1-1.5mm的镀钯键合铜丝;
(6)第一次热退火:对完成步骤(5)的镀钯键合铜丝进行热退火,其中热退火温度为450-500摄氏度,时间为20-60分钟;
(7)第二次电镀纯钯保护层:在完成步骤(6)的键合铜丝的表面上电镀1.4-2.8wt%的纯钯;
(8)第二次精拔:将完成步骤(7)的镀钯键合铜丝精拔成直径为15-25微米的镀钯键合铜丝;
(9)第二次热退火:对完成步骤(8)的镀钯键合铜丝进行热退火,其中热退火温度为450-500摄氏度,时间为20-60分钟;
(10)清洗:对完成步骤(9)的镀钯键合铜丝进行表面清洗,采用酸性溶液先对其进行一次清洗,然后采用去离子水进行二次清洗;
(11)将清洗干净的镀钯键合铜丝烘干。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310065255.1A CN103219245B (zh) | 2013-03-01 | 2013-03-01 | 一种镀钯键合铜丝的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310065255.1A CN103219245B (zh) | 2013-03-01 | 2013-03-01 | 一种镀钯键合铜丝的制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103219245A CN103219245A (zh) | 2013-07-24 |
CN103219245B true CN103219245B (zh) | 2015-11-25 |
Family
ID=48816930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310065255.1A Expired - Fee Related CN103219245B (zh) | 2013-03-01 | 2013-03-01 | 一种镀钯键合铜丝的制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103219245B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107546133A (zh) * | 2017-09-11 | 2018-01-05 | 佛山慧创正元新材料科技有限公司 | 软性抗氧化铜丝的制备方法 |
CN109266874B (zh) * | 2018-09-19 | 2019-08-23 | 河南大仑电子科技有限公司 | 一种铜合金键合引线的制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101386930A (zh) * | 2007-09-15 | 2009-03-18 | 山东华宏微电子材料科技有限公司 | 键合铜线制造方法 |
CN101707194A (zh) * | 2009-11-11 | 2010-05-12 | 宁波康强电子股份有限公司 | 一种镀钯键合铜丝及其制造方法 |
CN102226991A (zh) * | 2011-06-12 | 2011-10-26 | 徐云管 | 铜钯合金单晶键合丝及其制造方法 |
TW201207129A (en) * | 2010-08-05 | 2012-02-16 | jin-yong Wang | Cooper bonding wire used in encapsulation and manufacturing method thereof |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101019811B1 (ko) * | 2005-01-05 | 2011-03-04 | 신닛테츠 마테리알즈 가부시키가이샤 | 반도체 장치용 본딩 와이어 |
-
2013
- 2013-03-01 CN CN201310065255.1A patent/CN103219245B/zh not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101386930A (zh) * | 2007-09-15 | 2009-03-18 | 山东华宏微电子材料科技有限公司 | 键合铜线制造方法 |
CN101707194A (zh) * | 2009-11-11 | 2010-05-12 | 宁波康强电子股份有限公司 | 一种镀钯键合铜丝及其制造方法 |
TW201207129A (en) * | 2010-08-05 | 2012-02-16 | jin-yong Wang | Cooper bonding wire used in encapsulation and manufacturing method thereof |
CN102226991A (zh) * | 2011-06-12 | 2011-10-26 | 徐云管 | 铜钯合金单晶键合丝及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN103219245A (zh) | 2013-07-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103219246B (zh) | 一种镀钯镀银的双镀层键合铜丝的制造方法 | |
CN101707194B (zh) | 一种镀钯键合铜丝的制造方法 | |
CN103219249B (zh) | 一种镀钯镀金的双镀层键合铜丝的制造方法 | |
CN109266874B (zh) | 一种铜合金键合引线的制备方法 | |
CN101314832B (zh) | 铁合金材料、由铁合金材料制成的半导体引线框架及其制备方法 | |
CN101667566B (zh) | 一种银基覆金的键合丝线的制造方法 | |
CN106086962A (zh) | 一种封装用镀金钯键合铜线的生产工艺 | |
CN103219312B (zh) | 一种镀钯镀金的双镀层键合铜丝 | |
CN103219245B (zh) | 一种镀钯键合铜丝的制造方法 | |
CN105428335A (zh) | 一种键合丝 | |
CN103219247B (zh) | 一种镀银键合铜丝的制造方法 | |
CN109628793A (zh) | 一种铜镀钯镀镍再镀金键合丝及其制备方法 | |
CN104377185A (zh) | 镀金银钯合金单晶键合丝及其制造方法 | |
CN103219311B (zh) | 一种镀钯镀银的双镀层键合铜丝 | |
CN103219248B (zh) | 一种镀金键合铜丝的制造方法 | |
CN104005027A (zh) | 一种含硅环氧树脂表面金属化的方法 | |
CN102931319B (zh) | 一种高导热led封装基板的制作方法 | |
CN201893333U (zh) | 新型集成电路框架结构 | |
CN104112705A (zh) | 一种引线框架镀铜方法及引线框架、引线框架排 | |
CN101621003A (zh) | 高压二极管新型生产工艺 | |
CN106521231A (zh) | 一种高强银铜合金导体及其制备工艺 | |
CN206283008U (zh) | 一种泡沫结构的片式连接器 | |
CN104022095A (zh) | 镀金银镧钙合金键合丝及其制造方法 | |
CN104134645B (zh) | 一种封装导线材料结构及其加工方法 | |
CN206379370U (zh) | Uv芯片导线架模组 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151125 Termination date: 20160301 |
|
CF01 | Termination of patent right due to non-payment of annual fee |