N-type is mixed the heterojunction solar battery device of hydrogen crystallization silicon passivation
Technical field
The present invention relates to a kind of N-type and mix the heterojunction solar battery device of hydrogen crystallization silicon passivation, belong to the heterojunction solar battery technical field.
Background technology
At present, with the N-type crystalline silicon as substrate, form the heterojunction battery device, what generally use is amorphous silicon membrane (a-Si:H) passivation crystalline silicon (substrate) surface of Intrinsical (intrinsic), add simultaneously doped n+-a-Si:H forms the back of the body (BSF), but because the resistivity of plain intrinsic amorphous silicon thin-film material is bigger, so series resistance is bigger, fill factor, curve factor FF is lower, and battery conversion efficiency is not high.
Summary of the invention
Technical problem to be solved by this invention is the defective that overcomes prior art, provide a kind of N-type to mix the heterojunction solar battery device of hydrogen crystallization silicon passivation, it can reduce the whole series resistance of solar cell, and then can improve fill factor, curve factor, thereby improves the conversion efficiency of solar cell.
In order to solve the problems of the technologies described above, technical scheme of the present invention is: a kind of N-type is mixed the heterojunction solar battery device of hydrogen crystallization silicon passivation, it comprises that N-type crystalline silicon substrate, intrinsic amorphous silicon passivation layer, heavy doping P type amorphous silicon layer, front transparent conductive film layer, front electrode layer, N-type mix hydrogen crystallized silicon layer, heavy doping N-type amorphous silicon layer, back side transparent conductive film layer and backplate layer, and the N-type crystalline silicon substrate has a positive and back side; The intrinsic amorphous silicon passivation layer deposition is on the front of N-type crystalline silicon substrate; Heavy doping P type amorphous silicon layer is deposited on the upper surface of intrinsic amorphous silicon passivation layer; The front nesa coating is deposited upon on the upper surface of heavy doping P type amorphous silicon layer; The front electrode layer is positioned on the upper surface of front transparent conductive film layer, and electrically connects by this front transparent conductive film layer and heavy doping P type amorphous silicon layer; N-type is mixed the hydrogen crystallized silicon layer and is deposited on the back side of N-type crystalline silicon substrate; Heavy doping N-type amorphous silicon layer is deposited on N-type and mixes on the lower surface of hydrogen crystallized silicon layer; Back side nesa coating is deposited upon on the lower surface of heavy doping N-type amorphous silicon layer; The backplate layer is positioned on the lower surface of back side transparent conductive film layer, and electrically connects by this back side transparent conductive film layer and heavy doping N-type amorphous silicon layer.
Further, described front transparent conductive film layer and/or back side transparent conductive film layer are silver-colored grid.
Further, described front transparent conductive film layer and/or back side transparent conductive film layer are ito thin film.
Further, the thickness of described N-type crystalline silicon substrate is 90 ~ 300 microns.
Further, the thickness of described intrinsic amorphous silicon passivation layer is 3 ~ 10 nanometers.
Further, the thickness of described heavy doping P type amorphous silicon layer is 10 ~ 20 nanometers.
Further, the thickness of described front transparent conductive film layer is 60 ~ 90 nanometers.
Further, to mix the thickness of hydrogen crystallized silicon layer be 3 ~ 15 nanometers to described N-type.
Further, the thickness of described heavy doping N-type amorphous silicon layer is 10 ~ 30 nanometers.
Further, the thickness of described back side transparent conductive film layer is 80 ~ 150 nanometers.
After having adopted technique scheme, the present invention has following beneficial effect:
1, N-type is mixed hydrogen crystallized silicon layer (n-c-Si:H), because the existence of doped with hydrogen atom, can the passivation silicon chip surface, and passivation effect obtains heterojunction battery high open circuit voltage (Voc) thereby keep preferably.
2, because N-type is mixed in the hydrogen crystallized silicon layer and mixed phosphorus atoms, cause the resistance of this passivation layer to reduce, can reduce the series resistance of whole solar cell, improve fill factor, curve factor FF, promote the conversion efficiency of heterojunction battery.
3, N-type is mixed the growth technique of hydrogen crystallized silicon layer and conventional PECVD deposition n-a-Si:H basically identical, only needs to adjust the gas mixing ratio of hydrogen and silane, does not increase operation, does not additionally increase cost, and technology is simple.
Description of drawings
Fig. 1 mixes the structural representation of the heterojunction solar battery device of hydrogen crystallization silicon passivation for N-type of the present invention;
Fig. 2 mixes the manufacture craft flow chart of the heterojunction solar battery device of hydrogen crystallization silicon passivation for N-type.
Embodiment
Content of the present invention is easier to be expressly understood in order to make, and according to specific embodiment also by reference to the accompanying drawings, the present invention is further detailed explanation below,
As shown in Figure 1, a kind of N-type is mixed the heterojunction solar battery device of hydrogen crystallization silicon passivation, it comprises that N-type crystalline silicon substrate 1, intrinsic amorphous silicon passivation layer 2, heavy doping P type amorphous silicon layer 3, front transparent conductive film layer 4, front electrode layer 5, N-type mix hydrogen crystallized silicon layer 6, heavy doping N-type amorphous silicon layer 7, back side transparent conductive film layer 8 and backplate layer 9, and it has a positive and back side N-type crystalline silicon substrate 1; Intrinsic amorphous silicon passivation layer 2 is deposited on the front of N-type crystalline silicon substrate 1; Heavy doping P type amorphous silicon layer 3 is deposited on the upper surface of intrinsic amorphous silicon passivation layer 2; Front transparent conductive film layer 4 is deposited on the upper surface of heavy doping P type amorphous silicon layer 3; Front electrode layer 5 is positioned on the upper surface of front transparent conductive film layer 4, and electrically connects by this front transparent conductive film layer 4 and heavy doping P type amorphous silicon layer 3; N-type is mixed hydrogen crystallized silicon layer 6 and is deposited on the back side of N-type crystalline silicon substrate 1; Heavy doping N-type amorphous silicon layer 7 is deposited on N-type and mixes on the lower surface of hydrogen crystallized silicon layer 6; Back side transparent conductive film layer 8 is deposited on the lower surface of heavy doping N-type amorphous silicon layer 7; Backplate layer 9 is positioned on the lower surface of back side transparent conductive film layer 8, and electrically connects by this back side transparent conductive film layer 8 and heavy doping N-type amorphous silicon layer 7.
Front electrode layer 5 and/or backplate layer 9 are silver-colored grid.
Front transparent conductive film layer 4 and/or back side transparent conductive film layer 8 are ito thin film.
The thickness of N-type crystalline silicon substrate 1 is 90 ~ 300 microns.
The thickness of intrinsic amorphous silicon passivation layer 2 is 3 ~ 10 nanometers.
The thickness of heavy doping P type amorphous silicon layer 3 is 10 ~ 20 nanometers.
The thickness of front transparent conductive film layer 4 is 60 ~ 90 nanometers.
The thickness that N-type is mixed hydrogen crystallized silicon layer 6 is 3 ~ 15 nanometers.
The thickness of heavy doping N-type amorphous silicon layer 7 is 10 ~ 30 nanometers.
The thickness of back side transparent conductive film layer 8 is 80 ~ 150 nanometers.
Operation principle of the present invention is as follows:
The aluminum back surface field of heterojunction battery partly is N-type crystalline silicon substrate 1(n-c-Si) and heavy doping N-type amorphous silicon layer 7(n+-a-Si:H) between, insert one deck N-type and mix hydrogen crystallized silicon layer 6(n-c-Si:H) as backside passivation layer, N-type in this heterojunction battery device structure mixes hydrogen crystallized silicon layer 6 because the existence of the hydrogen atom that mixes, can the passivation silicon chip surface, passivation effect obtains heterojunction battery high open circuit voltage (Voc) thereby keep preferably; In addition, because N-type is mixed in the hydrogen crystallized silicon layer 6 and mixed phosphorus atoms, cause the resistance of backside passivation layer to reduce, thereby can reduce whole solar cell series resistance, improve fill factor, curve factor FF, realize the lifting of heterojunction solar cell conversion efficiency.
A kind of manufacture craft flow process of this heterojunction solar battery device is as follows:
Adopt the about 200 microns N-type crystalline silicon of thickness through RCA cleaning, making herbs into wool and the hydrofluoric acid treatment of standard, front in N-type crystalline silicon substrate 1 deposits one deck intrinsic amorphous silicon passivation layer 2 by pecvd process, the about 3-10nm of thickness, passivation N-type crystalline silicon substrate surface, reduce recombination-rate surface, obtain the good interface characteristic; Deposit one deck heavy doping P type amorphous silicon layer 3 again, thickness is 10-20nm, mixes hydrogen crystallized silicon layer 6 at the back side of N-type crystalline silicon substrate 1 by pecvd process deposition N-type again, and typical thickness is 3-15nm, deposit one deck heavy doping N-type amorphous silicon layer 7 (n-a-Si:H) at last, thickness is 10-30nm.After the aforementioned body battery structure is finished, by methods such as sputter or evaporations, upper and lower surface at said structure adopts ito thin film to deposit front transparent conductive film layer 7 and back side transparent conductive film layer 8 respectively, use the low-temperature silver slurry in the upper and lower surface silk screen printing again, obtain silver-colored grid through low temperature sintering technology, finish the making of this heterojunction battery.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.