CN103187394B - 具有无源器件的封装件及其形成方法 - Google Patents

具有无源器件的封装件及其形成方法 Download PDF

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CN103187394B
CN103187394B CN201210419270.7A CN201210419270A CN103187394B CN 103187394 B CN103187394 B CN 103187394B CN 201210419270 A CN201210419270 A CN 201210419270A CN 103187394 B CN103187394 B CN 103187394B
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dielectric layer
ubm
passive device
layer
ppi
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CN103187394A (zh
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余振华
侯上勇
叶德强
陈硕懋
叶炅翰
林仪柔
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种器件，包括衬底、位于衬底上方的金属焊盘，以及具有位于金属焊盘上方部分的钝化层。钝化后互连(PPI)线设置在钝化层上方并且电耦合至金属焊盘。凸块底部金属(UBM)设置在PPI线上方并且电耦合至PPI线。无源器件包括位于与UBM相同水平面处的部分。无源器件的部分由与UBM相同的材料形成。本发明还提供了具有无源器件的封装件及其形成方法。

Description

具有无源器件的封装件及其形成方法
相关申请的交叉参考
本申请要求以下于2011年12月29日提交的名称为“FO-WLP ExtraCu-PPI Process and System Electrical Shielding Solution”的申请序列号为61/581,279的临时提交的美国专利申请的优先权，其全部内容结合于此作为参考。
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及具有无源器件的封装件及其形成方法。
背景技术
随着半导体技术的不断发展，半导体管芯变得越来越小。同时，需要将更多功能集成在半导体管芯中。相应地，半导体管芯需要具有封装在更小的区域中的更大数量的I/O焊盘，并且随着时间的推移，I/O焊盘的密度迅速上升。因此，半导体管芯的封装变得更加困难，从而对封装的成品率产生了负面影响。
传统封装技术可以分为两种类型。在第一种封装件中，在切割之前封装晶圆上管芯。这种封装技术具有一些有利的特征，如高产量和低成本。此外，需要较少的底部填充物或模塑料。然而，这种封装技术也具有缺陷。如上面提到的，管芯的尺寸越来越小，相应封装件只能是扇入型封装件，其中，每个管芯的I/O焊盘都限定直接位于相应管芯的表面上方的区域。对于有限的管芯面积，由于I/O焊盘间距的限制，限制了I/O焊盘的数量。如果减小焊盘的间距，可能出现焊桥。另外地，在固定焊球尺寸要求下，焊球必须具有一定的尺寸，从而反过来限制了可以封装在管芯表面上方的焊球数量。
在另一种封装件中，在封装管芯之前就从晶圆上切割管芯，并仅封装“已知好管芯”。这种封装技术的有利特征是形成扇出封装件的可能，从而意味着管芯上的I/O焊盘可以被再分布到比管芯更大的区域，因此可能增加封装在管芯表面的I/O焊盘的数量。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种器件，包括：衬底；金属焊盘，位于所述衬底上方；钝化层，包括位于所述金属焊盘上方的部分；钝化后互连(PPI)线，位于所述钝化层上方并且与所述金属焊盘电耦合；凸块底部金属(UBM)，位于所述PPI线上方并且与所述PPI线电耦合；以及无源器件，包括与所述UBM处于相同水平的部分，所述无源器件的该部分由与所述UBM相同的材料形成。
在该器件中，从基本上由电阻器、电容器、电感器、变压器、共面波导、带状线以及它们的组合所组成的组中选择所述无源器件。
在该器件中，所述无源器件的该部分包括钛层以及位于所述钛层上方的铜层。
该器件进一步包括围绕所述衬底并与所述衬底处于相同水平的聚合物，所述聚合物进一步包括与所述金属焊盘处于相同水平的部分，以及所述无源器件包括位于所述聚合物上方并与所述聚合物对准的部分，
在该器件中，所述聚合物包括模塑料。
该器件进一步包括：金属柱，位于所述金属焊盘上方并与所述金属焊盘连接，所述金属柱、所述钝化层和所述聚合物的顶面基本上彼此平齐；介电层，位于所述金属柱、所述聚合物和所述钝化层上方；以及通孔，位于所述介电层中，所述通孔位于所述PPI线和所述金属柱之间并且互连所述PPI线和所述金属柱。
在该器件中，所述无源器件进一步包括位于所述介电层中的部分。
该器件进一步包括：焊料区，位于所述UBM上方并与所述UBM接触；封装元件，与所述焊料区接合；以及底部填充物，包围所述焊料区，所述底部填充物与所述无源器件接触。
根据本发明的另一方面，提供了一种器件，包括：管芯，包括：半导体衬底；金属焊盘，位于所述半导体衬底上方；钝化层，包括位于所述金属焊盘上方的部分；以及金属柱，位于所述金属焊盘上方并延伸到所述钝化层中；模塑料，包围所述管芯；第一介电层，位于所述金属柱、所述钝化层和所述模塑料上方；钝化后互连(PPI)线，位于所述第一介电层上方，并且通过所述金属柱和所述第一介电层中的通孔电耦合至所述金属焊盘；第二介电层，包括位于所述PPI线上方的部分；凸块底部金属(UBM)，位于所述PPI线上方并与所述PPI线电耦合，所述UBM延伸到所述第二介电层中；焊料区，位于所述UBM上方并与所述UBM连接；以及无源器件，包括位于所述第一介电层中的第一部分以及位于第二介电层上方的第二部分。
在该器件中，所述模塑料包括：与所述半导体衬底的底面平齐的底面；以及与所述钝化层和所述金属柱的顶面平齐的顶面。
在该器件中，所述无源器件包括位于所述模塑料上方并与所述模塑料对准的部分。
在该器件中，从基本上由电阻器、电容器、电感器、变压器、共面波导、带状线以及它们的组合所组成的组中选择所述无源器件。
在该器件中，所述无源器件进一步包括位于所述第二介电层中的部分。
在该器件中，所述第一介电层和所述第二介电层包括聚酰亚胺。
根据本发明的又一方面，提供了一种方法，包括：将管芯附接在载具上方，所述管芯包括：半导体衬底；金属焊盘，位于所述半导体衬底上方；钝化层，包括位于所述金属焊盘上方的部分；以及金属柱，位于所述金属焊盘上方并延伸到所述钝化层中；通过聚合物模制所述管芯，所述聚合物包围所述管芯；将第一介电层形成在所述金属柱、所述钝化层和所述聚合物上方；将第一开口形成在所述第一介电层中，通过所述第一开口中的一个开口暴露所述金属柱；将钝化后互连(PPI)线形成在所述钝化层上方，并通过所述金属柱以及位于所述第一开口中的所述一个开口中的通孔电耦合至所述金属焊盘；形成第二介电层，所述第二介电层包括位于所述PPI线上方的部分；将凸块底部金属(UBM)形成在所述PPI线上方并与所述PPI线电耦合；将焊料区形成在所述UBM上方并与所述UBM连接；以及在形成所述UBM时，同时形成无源器件的第一部分。
在该方法中，所述第一开口包括位于所述聚合物上方并与所述聚合物对准的部分，以及在形成所述PPI线时，金属材料被填充在所述第一开口的部分中以形成所述无源器件的第二部分。
该方法进一步包括图案化所述第二介电层以形成第二开口，在填充所述UBM时，填充所述第二开口以形成所述无源器件的额外部分。
该方法进一步包括：将电介质掩模层形成在所述无源器件和所述UBM层上方；以及图案化所述电介质掩模层以暴露所述焊料区，通过所述电介质掩模层的剩余部分覆盖所述无源器件。
该方法进一步包括：将所述焊料区接合至封装元件；以及将底部填充物散布在所述第二介电层和所述封装元件之间的间隙中，其中，所述底部填充物与所述无源器件接触。
该方法进一步包括：在形成所述第一介电层的步骤之前，实施研磨步骤以使所述金属柱、所述钝化层和所述聚合物的顶面平齐。
附图说明
为了更好地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图11是根据各种示例性实施例制造封装件的中间阶段的横截面图；
图12至图14是根据各种可选实施例制造封装件的中间阶段的横截面图；以及
图15A至图19示出了一些示例性的集成无源器件(IPD)。
具体实施方式
以下详细讨论了本公开内容的实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明理念。所讨论的具体实施例是说明性的，并没有限定本公开内容的范围。
根据实施例提供包括集成无源器件(IPD)的封装结构及其形成方法。示出了制造封装件的中间阶段。还讨论了实施例的变型例。在所有的各个附图和说明性的实施例中，相同的参考标号用于指定相同的元件。
参考图1，提供管芯100。管芯100包括衬底20，该衬底可以是半导体衬底。管芯100可以包括集成电路器件23及形成在其中的上覆互连结构(未示出)。集成电路器件23可以包括诸如晶体管的有源器件。接合焊盘22形成在管芯100中，并且可以通过互连结构电耦合至集成电路器件23。接合焊盘22可以由铝、铜、镍或者它们的组合形成。钝化层24和26形成在接合焊盘22上方。在一些实施例中，接合焊盘22的顶面基本上与钝化层24的底面24B的部分平齐。可以从阻焊剂、聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、JSR、模塑料等中选择钝化层24和26的材料。钝化层24和26的边缘可以与衬底20的相应边缘竖直地对准。钝化层24和26可以分别地被称为钝化-1和钝化-2。
金属柱28形成在钝化层24中，并且电耦合至接合焊盘22。在一些实施例中，金属柱28具有与接合焊盘22的顶面接触的底面。金属柱28可以包括铜，因此在通篇描述中可选地被称为铜柱28。然而，诸如镍和/或铝的其他导电材料也可以用于形成铜柱28。在一些实施例中，铜柱28的顶面28A基本上与钝化层26的顶面26A平齐。在其他实施例中，铜柱28的顶面28A低于顶面26A，因此铜柱28位于钝化层26中，其中，钝化层26的较薄部分覆盖铜柱28。
参考图2，粘合层32设置(例如，层压)在载具30上。粘合层32可以由粘着剂形成。管芯100通过粘合层32安装在载具30上。虽然示出了单个管芯100，但是可以有置于载具30上方的多个彼此相同的管芯100。在管芯100包括半导体衬底20的实施例中，半导体衬底20的底面20B与粘合层32接触。在相邻的管芯100之间保留间隙。
图3示出了在管芯100上方模制的聚合物34。聚合物34可以是模塑料，因此，此后被称为模塑料34，但是该聚合物也可以由其他材料形成。模塑料34可以包括填充在管芯100之间的间隙中的有机材料，诸如环氧树脂。也可以通过模塑料34覆盖管芯100的顶面。然后，实施固化工艺以固化模塑料34。
此外，如图3所述，在模塑料34上方实施诸如研磨的平坦化，直到暴露铜柱28以及可能的钝化层26。相应地，钝化层26的顶面26A、铜柱28的顶面28A以及模塑料34的顶面34A可以基本上彼此平齐。在铜柱28内嵌在钝化层26的实施例中，还研磨钝化层26的层。作为研磨的结果，可以没有位于管芯100上方的模塑料34。在图3的结构的俯视图中，管芯100由模塑料34包围。
参考图4，介电层36形成在模塑料34、钝化层26及铜柱28上方。例如，可以使用聚酰亚胺、PBO、BCB、JSR形成介电层36。开口38形成在介电层36中，并通过开口38暴露铜柱28。在一些实施例中，当形成开口38时，同时形成开口40。开口40可以位于模塑料34上方并且与模塑料34对准，和/或位于钝化层26上方并且与钝化层26对准。
参考图5，形成铜钝化后互连(PPI)结构。铜PPI结构包括形成在开口38中的通孔42，以及位于介电层36上方的PPI线44。通孔42将铜柱28电耦合至PPI线44。PPI线44可以在模塑料34上方延伸并与模塑料34对准，以形成扇出结构。在形成通孔42和PPI线44时，还形成PPI部件46和部件48，其中PPI部件46位于介电层36中，并且PPI部件48位于介电层36上方。PPI部件46和48中的每一个都可以是金属线或金属通孔。在一些实施例中，PPI部件46和48具有彼此对准的相应边缘，以便PPI部件46和48共同形成厚导电部件。在可选实施例中，PPI部件46和48的边缘未对准，因此PPI部件46和48在俯视图中具有不同形状和/或在俯视图中具有不同尺寸。通孔42、PPI线44以及PPI部件46和48可以包括铜和/或其他导电材料，诸如铝。示例性的形成工艺包括形成和图案化光刻胶50，以及在光刻胶50的开口中电镀部件42、44、46和48。然后去除光刻胶50。
接下来，参考图6，介电层52形成在介电层36和部件42、44、46和48上方。可以使用与介电层36相同的材料形成介电层52。例如，介电层52可以包括聚酰亚胺、PBO、BCB、JSR等。介电层36和52可以由相同材料或不同材料形成。开口54形成在介电层52中，以便暴露PPI线44。开口54可以位于模塑料34或钝化层36上方并与模塑料34或钝化层36对准。在一些实施例中，当形成开口54时，同时形成开口56。通过开口56暴露PPI部件48中的一些。接下来，形成凸块底部金属(UBM)层58，以延伸到开口54和56中，从而与PPI线44和PPI部件48接触。在一些示例性实施例中，UBM层58包括钛层58A和位于钛层58A上方的铜层58B。
在图7中，形成和图案化光刻胶60，以便暴露UBM层58的一些部分，而覆盖一些其他部分。可以实施电镀工艺以在UBM层58的暴露部分上方电镀金属材料，该金属材料可以包括铜、镍、钯、锡、铝、它们的合金或它们的组合。电镀的材料包括部分62A和62B。部分62A位于PPI部件48上方并与PPI部件48连接。部分62B位于PPI线44上方并与PPI线44连接。
参考图8，去除光刻胶60。实施蚀刻以去除当实施电镀时通过光刻胶60覆盖的UBM层58的部分。UBM层58的剩余部分包括位于金属材料部分62A下方的第一部分，以及位于金属材料部分62B下方的第二部分。在通篇描述中，金属材料部分62A和UBM层58的第一部分共同被称为UBM再分布线(RDL)66。金属材料部分62B和UBM层58的第二部分共同称为UBM 64。UBM RDL 66和下面的PPI部件46和48形成IPD 200，IPD 200可以是电阻器、电容器、电感器、变压器、平衡-不平衡转换器(balun)、带状线、共面波导等。IPD 200可以位于模塑料34上方并与模塑料34对准。可选地，IPD 200可以位于管芯100上方并与管芯100对准，其中虚线矩形68示出了可以形成IPD 200的位置。
图9示出了是介电层的掩模层70的形成。在一些实施例中，掩模层70由可以将IPD 200从外部环境的有害物质隔离的材料形成。例如，掩模层70可以由聚酰亚胺、PBO、BCB或类似材料形成。通过图案化掩模层70形成开口72。通过开口72暴露UBM 64。接下来，如图10所示，可以是焊球的焊料区74形成在UBM 64上方。在通篇描述中，形成在粘合层32上方的结构共同被称为晶圆76，该晶圆包括多个管芯100和相应连接的IPD器件200。在后续步骤中，晶圆76可以与载具30分离，并且可以从晶圆76剥离粘合层32。可以沿着划线77实施管芯切割，以将晶圆76切割为多个封装件78。在图11中示出了示例性封装件78。
图12至图14示出了根据可选实施例形成封装件的中间阶段的横截面图。除非另有说明，否则这些实施例中的元件的材料及形成方法基本上与通过在图1至图11所示的实施例中的相同的参考标号表示的相同元件相同。因此，在图1至图11所示的实施例的讨论中可以找到示出在图12至图14所述的相同元件的细节。
这些实施例的初始步骤基本上与在图1至图8中所示的步骤的相同。接下来，如图12所示，在没有形成覆盖IPD 200的掩模层的情况下，形成焊料区74。将是粘合层32上方的结构的部分的晶圆76切割为多个封装件78。参考图13，封装件78中的一个接合至封装元件300，封装元件300可以是中介层、封装衬底、另一个封装件、印刷电路板(PCB)等。
接下来，如图14所示，底部填充物80散布在封装元件300和封装件78之间的间隙中，然后固化该底部填充物80。底部填充物80保护无源器件200防止外部环境中的湿气或其他有害物质的损害。
图15A至图19示出了一些如图11至图14所示的示例性的IPD 200。图15A至图19中的IPD 200的形成方法可以通过参考图1至图11找到。在每个IPD 200中，当形成UBM RDL 66、下导电层、PPI线44，以及通孔42同，同时形成为相同层的上导电层。
图15A示出了是金属氧化物金属(MOM)电容器的IPD 200的俯视图。IPD 200包括第一多个电容器指状元件66(上层)，互连形成电容器的一个电容器极板；以及电容器指状元件46/48(下层)，互连形成电容器的另一个电容器极板。图15B示出了透视图。指状元件66及46/48可以通过形成电容器绝缘体部分的介电层52的部分(图15A和图15B未示出，请参看图11至图14)彼此间隔开。
图16A和图16B分别地示出了IPD 200的透视图和横截面图，IPD 200是共面波导，并且包括信号线82和位于信号线82相对侧并与信号线82平行的接地线84。参考图16B，信号线82和接地线84中的每一条都可以包括上部66以及下部46/48，堆叠上部66以及下部46/48以形成较厚线。通过堆叠部分66和46/48，减小了线82和84的线电阻，并且改善了共面波导200的性能。
图17示出了是带状线的IPD 200的透视图，该IPD200包括用作接地面的PPI部件46/48。UBM RDL 66用作信号线，UBM RDL 66通过介电层52的上部(图11和图14)与接地面46/48分离。图18示出了带状线。与图17所示的结构相反，在该实施例中，信号线是PPI部件46/48的一部分，而接地线是UBM RDL 66的一部分。图19示出了变压器或平衡-不平衡转换器200，其中，变压器/平衡-不平衡转换器200中的线圈可以包括堆叠的部件46/48，而UBM 66可以用作线圈之间的连接件。
通过使用UBM RDL形成IPD，更好地使用封装区域。提高了IPD的性能。形成IPD不要求额外的掩模和光刻步骤。
根据实施例，器件包括衬底、位于衬底上方的金属焊盘以及具有位于金属焊盘上方部分的钝化层。钝化后互连(PPI)线置于钝化层上方并且电耦合至金属焊盘。凸块底部金属(UBM)设置在PPI线上方并与PPI线电耦合。无源器件包括位于与UBM相同的水平面处的部分。无源器件的部分由与UBM相同的材料形成。
根据其他实施例，器件包括管芯，该管芯包括半导体衬底、位于半导体衬底上方的金属焊盘、包括位于金属焊盘上方部分的钝化层以及位于金属焊盘上方并且延伸到钝化层中的金属柱。模塑料包围管芯。第一介电层位于金属柱、钝化层以及模塑料上方。PPI线位于第一介电层上方并且通过金属柱和位于第一介电层中的通孔电耦合至金属焊盘。第二介电层具有位于PPI线上方的部分。UBM位于PPI线上方并与PPI线电耦合，其中，UBM延伸到第二介电层中。焊料层位于UBM上方并与UBM连接。无源器件包括位于第一介电层中的第一部分，以及位于第二介电层上方的第二部分。
根据又一个实施例，方法包括在载具上方附接管芯。管芯包括半导体衬底、位于半导体衬底上方的金属焊盘、包括位于金属焊盘上方部分的钝化层以及位于金属焊盘上方并延伸到钝化层中的金属柱。用聚合物模制管芯，其中，聚合物包围管芯。方法进一步包括在金属柱、钝化层以及聚合物上方形成第一介电层，以及在第一介电层内形成第一开口。通过第一开口中的一个开口暴露金属柱。PPI线形成在钝化层上方并通过金属柱和位于第一开口的一个开口中的通孔电耦合至金属焊盘。形成第二介电层，并且包括位于PPI线上方的部分。形成UBM以位于PPI线上方并与PPI线电耦合。焊料区形成在UBM上方并与UBM连接。在形成UBM时，同时形成无源器件的部分。
尽管已经详细地描述了本实施例及其优点，但是应该理解，可以在不背离所附权利要求限定的本实施例的主旨和范围的情况下，做各种不同的改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本公开内容的范围内。

Claims (20)

1.一种器件，包括：
衬底；
金属焊盘，位于所述衬底上方；
钝化层，包括位于所述金属焊盘上方的部分；
金属柱，位于所述金属焊盘上方并与所述金属焊盘连接；
介电层，位于所述金属柱和所述钝化层上方；以及
钝化后互连(PPI)线，位于所述钝化层上方并且与所述金属焊盘电耦合；
通孔，位于所述介电层中，所述通孔位于所述PPI线和所述金属柱之间并且互连所述PPI线和所述金属柱；
凸块底部金属(UBM)，位于所述PPI线上方并且与所述PPI线电耦合；以及
无源器件，包括与所述UBM处于相同水平的部分，所述无源器件的该部分由与所述UBM相同的材料形成。
2.根据权利要求1所述的器件，其中，从基本上由电阻器、电容器、电感器、变压器、共面波导、带状线以及它们的组合所组成的组中选择所述无源器件。
3.根据权利要求1所述的器件，其中，所述无源器件的该部分包括钛层以及位于所述钛层上方的铜层。
4.根据权利要求1所述的器件，进一步包括围绕所述衬底并与所述衬底处于相同水平的聚合物，所述聚合物进一步包括与所述金属焊盘处于相同水平的部分，以及所述无源器件包括位于所述聚合物上方并与所述聚合物对准的部分，
5.根据权利要求4所述的器件，其中，所述聚合物包括模塑料。
6.根据权利要求4所述的器件，所述金属柱、所述钝化层和所述聚合物的顶面基本上彼此平齐；所述介电层，位于所述聚合物上方。
7.根据权利要求6所述的器件，其中，所述无源器件进一步包括位于所述介电层中的部分。
8.根据权利要求1所述的器件，进一步包括：
焊料区，位于所述UBM上方并与所述UBM接触；
封装元件，与所述焊料区接合；以及
底部填充物，包围所述焊料区，所述底部填充物与所述无源器件接触。
9.一种器件，包括：
管芯，包括：
半导体衬底；
金属焊盘，位于所述半导体衬底上方；
钝化层，包括位于所述金属焊盘上方的部分；以及
金属柱，位于所述金属焊盘上方并延伸到所述钝化层中；
模塑料，包围所述管芯；
第一介电层，位于所述金属柱、所述钝化层和所述模塑料上方；
钝化后互连(PPI)线，位于所述第一介电层上方，并且通过所述金属柱和所述第一介电层中的通孔电耦合至所述金属焊盘；
第二介电层，包括位于所述PPI线上方的部分；
凸块底部金属(UBM)，位于所述PPI线上方并与所述PPI线电耦合，所述UBM延伸到所述第二介电层中；
焊料区，位于所述UBM上方并与所述UBM连接；以及
无源器件，包括位于所述第一介电层中的第一部分以及位于第二介电层上方的第二部分。
10.根据权利要求9所述的器件，其中，所述模塑料包括：
与所述半导体衬底的底面平齐的底面；以及
与所述钝化层和所述金属柱的顶面平齐的顶面。
11.根据权利要求9所述的器件，其中，所述无源器件包括位于所述模塑料上方并与所述模塑料对准的部分。
12.根据权利要求9所述的器件，其中，从基本上由电阻器、电容器、电感器、变压器、共面波导、带状线以及它们的组合所组成的组中选择所述无源器件。
13.根据权利要求9所述的器件，其中，所述无源器件进一步包括位于所述第二介电层中的部分。
14.根据权利要求9所述的器件，其中，所述第一介电层和所述第二介电层包括聚酰亚胺。
15.一种方法，包括：
将管芯附接在载具上方，所述管芯包括：
半导体衬底；
金属焊盘，位于所述半导体衬底上方；
钝化层，包括位于所述金属焊盘上方的部分；以及
金属柱，位于所述金属焊盘上方并延伸到所述钝化层中；
通过聚合物模制所述管芯，所述聚合物包围所述管芯；
将第一介电层形成在所述金属柱、所述钝化层和所述聚合物上方；
将第一开口形成在所述第一介电层中，通过所述第一开口中的一个开口暴露所述金属柱；
将钝化后互连(PPI)线形成在所述钝化层上方，并通过所述金属柱以及位于所述第一开口中的所述一个开口中的通孔电耦合至所述金属焊盘；
形成第二介电层，所述第二介电层包括位于所述PPI线上方的部分；
将凸块底部金属(UBM)形成在所述PPI线上方并与所述PPI线电耦合；
将焊料区形成在所述UBM上方并与所述UBM连接；以及
在形成所述UBM时，同时形成无源器件的第一部分。
16.根据权利要求15所述的方法，其中，所述第一开口包括位于所述聚合物上方并与所述聚合物对准的部分，以及在形成所述PPI线时，金属材料被填充在所述第一开口的部分中以形成所述无源器件的第二部分。
17.根据权利要求15所述的方法，进一步包括图案化所述第二介电层以形成第二开口，在填充所述UBM时，填充所述第二开口以形成所述无源器件的额外部分。
18.根据权利要求15所述的方法，进一步包括：
将电介质掩模层形成在所述无源器件和所述UBM层上方；以及
图案化所述电介质掩模层以暴露所述焊料区，通过所述电介质掩模层的剩余部分覆盖所述无源器件。
19.根据权利要求15所述的方法，进一步包括：
将所述焊料区接合至封装元件；以及
将底部填充物散布在所述第二介电层和所述封装元件之间的间隙中，其中，所述底部填充物与所述无源器件接触。
20.根据权利要求15所述的方法，进一步包括：在形成所述第一介电层的步骤之前，实施研磨步骤以使所述金属柱、所述钝化层和所述聚合物的顶面平齐。
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Families Citing this family (255)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US9960106B2 (en) * 2012-05-18 2018-05-01 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368454B2 (en) * 2013-10-10 2016-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with shielding layer in post-passivation interconnect structure
US9466581B2 (en) 2013-10-18 2016-10-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device and manufacturing method thereof
US9488779B2 (en) * 2013-11-11 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method of forming laser chip package with waveguide for light coupling
US9583420B2 (en) 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
US10026671B2 (en) 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US9768090B2 (en) 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9293442B2 (en) 2014-03-07 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9824990B2 (en) 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9881857B2 (en) 2014-06-12 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9449947B2 (en) 2014-07-01 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package for thermal dissipation
US9754928B2 (en) 2014-07-17 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. SMD, IPD, and/or wire mount in a package
US9613910B2 (en) 2014-07-17 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Anti-fuse on and/or in package
US9715131B2 (en) * 2014-09-11 2017-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package including dielectric waveguide
CN105575959B (zh) * 2014-11-21 2018-06-15 威盛电子股份有限公司 集成电路装置
US9812337B2 (en) 2014-12-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package pad and methods of forming
US10032651B2 (en) 2015-02-12 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US9564416B2 (en) 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10032704B2 (en) 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US10497660B2 (en) 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US10115647B2 (en) 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US9595482B2 (en) 2015-03-16 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for die probing
US10368442B2 (en) 2015-03-30 2019-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method of forming
US9786519B2 (en) 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9653406B2 (en) 2015-04-16 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive traces in semiconductor devices and methods of forming same
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9659805B2 (en) 2015-04-17 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and methods forming the same
CN109742064B (zh) * 2015-04-27 2021-06-11 精材科技股份有限公司 晶片封装体及其制造方法
US10340258B2 (en) 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9748212B2 (en) 2015-04-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shadow pad for post-passivation interconnect structures
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US9484227B1 (en) 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
US9741586B2 (en) 2015-06-30 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating package structures
US9818711B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
US10276541B2 (en) 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same
US10170444B2 (en) 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9793231B2 (en) 2015-06-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under bump metallurgy (UBM) and methods of forming same
US9842826B2 (en) 2015-07-15 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9373605B1 (en) 2015-07-16 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. DIE packages and methods of manufacture thereof
US9391028B1 (en) 2015-07-31 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US9847269B2 (en) 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US9570410B1 (en) 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
US10269767B2 (en) 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
US11018025B2 (en) 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
US10141288B2 (en) 2015-07-31 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface mount device/integrated passive device on package or device structure and methods of forming
US9564345B1 (en) 2015-08-18 2017-02-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9768145B2 (en) 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US9685411B2 (en) 2015-09-18 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US9881850B2 (en) 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US9917072B2 (en) 2015-09-21 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process
US10049953B2 (en) 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US9929112B2 (en) 2015-09-25 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10068844B2 (en) 2015-09-30 2018-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US9704825B2 (en) 2015-09-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US10720788B2 (en) 2015-10-09 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging devices having wireless charging coils and methods of manufacture thereof
US10304700B2 (en) 2015-10-20 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9640498B1 (en) 2015-10-20 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (InFO) package structures and methods of forming same
US9691723B2 (en) 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
US9953892B2 (en) 2015-11-04 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Polymer based-semiconductor structure with cavity
US9524959B1 (en) 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
US9953963B2 (en) 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9793245B2 (en) 2015-11-16 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9786614B2 (en) 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US9898645B2 (en) 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US9735118B2 (en) 2015-12-04 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Antennas and waveguides in InFO structures
US9893042B2 (en) 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10074472B2 (en) 2015-12-15 2018-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. InFO coil on metal plate with slot
US10165682B2 (en) 2015-12-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Opening in the pad for bonding integrated passive device in InFO package
US9666530B1 (en) * 2015-12-28 2017-05-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device
US10050013B2 (en) 2015-12-29 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
US9850126B2 (en) 2015-12-31 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US9984998B2 (en) 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US9881908B2 (en) 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package on package structure and methods of forming same
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US9620465B1 (en) 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
US9768303B2 (en) 2016-01-27 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for FinFET device
US10269702B2 (en) 2016-01-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info coil structure and methods of manufacturing same
DE102016118802B4 (de) 2016-01-29 2022-12-08 Taiwan Semiconductor Manufacturing Co. Ltd. Drahtloses Ladepaket mit in Spulenmitte integriertem Chip und Herstellungsverfahren dafür
US9761522B2 (en) 2016-01-29 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging package with chip integrated in coil center
DE102016102109A1 (de) * 2016-01-29 2017-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Integriertes fan-out-gehäuse mit dielektrischem wellenleiter
US9904776B2 (en) 2016-02-10 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor pixel array and methods of forming same
US9911629B2 (en) 2016-02-10 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated passive device package and methods of forming same
US10797038B2 (en) 2016-02-25 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and rework process for the same
US9754805B1 (en) 2016-02-25 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging method and structure
US9842815B2 (en) 2016-02-26 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10062648B2 (en) 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US9847320B2 (en) 2016-03-09 2017-12-19 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of fabricating the same
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US9859229B2 (en) 2016-04-28 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9935024B2 (en) 2016-04-28 2018-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor structure
US9935080B2 (en) 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
US9947552B2 (en) 2016-04-29 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US9997464B2 (en) 2016-04-29 2018-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy features in redistribution layers (RDLS) and methods of forming same
US9922895B2 (en) 2016-05-05 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
US9806059B1 (en) 2016-05-12 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10797025B2 (en) 2016-05-17 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced INFO POP and method of forming thereof
US9870997B2 (en) 2016-05-24 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10157807B2 (en) 2016-05-26 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor packages and manufacturing mehtods thereof
US10269481B2 (en) 2016-05-27 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked coil for wireless charging structure on InFO package
US9852957B2 (en) 2016-05-27 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Testing, manufacturing, and packaging methods for semiconductor devices
US9941216B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive pattern and integrated fan-out package having the same
US9941248B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures, pop devices and methods of forming the same
US10032722B2 (en) 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof
US9793246B1 (en) 2016-05-31 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Pop devices and methods of forming the same
US9812381B1 (en) * 2016-05-31 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9985006B2 (en) 2016-05-31 2018-05-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10504827B2 (en) * 2016-06-03 2019-12-10 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US11056436B2 (en) 2016-06-07 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out structure with rugged interconnect
US10354114B2 (en) 2016-06-13 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor in InFO structure and formation method
US10050024B2 (en) 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10475769B2 (en) 2016-06-23 2019-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10431738B2 (en) 2016-06-24 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US10229901B2 (en) 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
US9812426B1 (en) 2016-06-29 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, semiconductor device, and method of fabricating the same
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US9653391B1 (en) 2016-06-30 2017-05-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor packaging structure and manufacturing method thereof
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US10163800B2 (en) 2016-07-08 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy feature in passivation layer
US9793230B1 (en) 2016-07-08 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming
US9824902B1 (en) 2016-07-12 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US11469215B2 (en) 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9661794B1 (en) 2016-07-13 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing package structure
US9825007B1 (en) 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9799615B1 (en) 2016-07-20 2017-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures having height-adjusted molding members and methods of forming the same
US9691708B1 (en) 2016-07-20 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US10062654B2 (en) 2016-07-20 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US10276542B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US9984960B2 (en) 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10276506B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package
US10541226B2 (en) * 2016-07-29 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US10163860B2 (en) 2016-07-29 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure
US10083949B2 (en) 2016-07-29 2018-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Using metal-containing layer to reduce carrier shock in package formation
US10134708B2 (en) 2016-08-05 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with thinned substrate
US10340206B2 (en) 2016-08-05 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dense redistribution layers in semiconductor packages and methods of forming the same
US10297551B2 (en) 2016-08-12 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing redistribution circuit structure and method of manufacturing integrated fan-out package
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US10658334B2 (en) 2016-08-18 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die
CN109920739A (zh) * 2016-08-19 2019-06-21 华为技术有限公司 一种半导体封装结构及其制造方法
US10120971B2 (en) 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
US9741690B1 (en) 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US10128182B2 (en) 2016-09-14 2018-11-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US9922896B1 (en) 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile
US10529697B2 (en) 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US9922964B1 (en) 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US9859245B1 (en) 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US9837359B1 (en) 2016-09-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9911672B1 (en) 2016-09-30 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, method for fabricating integrated fan-out packages, and method for fabricating semiconductor devices
US10515899B2 (en) 2016-10-03 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with bump
US10157846B2 (en) 2016-10-13 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package involving cutting process
US10163801B2 (en) 2016-10-14 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US10014260B2 (en) 2016-11-10 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163813B2 (en) 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
US10692813B2 (en) 2016-11-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with dummy bumps connected to non-solder mask defined pads
US9837366B1 (en) 2016-11-28 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US10103125B2 (en) 2016-11-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10177078B2 (en) 2016-11-28 2019-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package structure
US10304793B2 (en) 2016-11-29 2019-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10128193B2 (en) 2016-11-29 2018-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10037963B2 (en) 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US10163824B2 (en) 2016-12-02 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10290596B2 (en) 2016-12-14 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a passivation layer and method of making the same
US9972581B1 (en) 2017-02-07 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Routing design of dummy metal cap and redistribution line
US10854568B2 (en) 2017-04-07 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10522449B2 (en) 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
DE102017123449B4 (de) 2017-04-10 2023-12-28 Taiwan Semiconductor Manufacturing Co. Ltd. Gehäuse mit Si-substratfreiem Zwischenstück und Ausbildungsverfahren
CN107146785A (zh) * 2017-06-21 2017-09-08 中芯长电半导体（江阴）有限公司 具有3d堆叠天线的扇出型封装结构及其制备方法
US10269589B2 (en) 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a release film as isolation film in package
DE102018109028B4 (de) 2017-06-30 2023-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit Abschirmstruktur zur Verringerung von Übersprechen und Verfahren zur Herstellung derselben
US10170341B1 (en) 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Release film as isolation film in package
DE102017012352B4 (de) 2017-06-30 2024-01-18 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren mit einem Trennfilm als Isolierfilm im Gehäuse und Gehäuse
US10867924B2 (en) 2017-07-06 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
US10522526B2 (en) 2017-07-28 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. LTHC as charging barrier in InFO package formation
US10290571B2 (en) 2017-09-18 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with si-substrate-free interposer and method forming same
US10629540B2 (en) 2017-09-27 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10790244B2 (en) 2017-09-29 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10269773B1 (en) 2017-09-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10727217B2 (en) 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device that uses bonding layer to join semiconductor substrates together
US10636758B2 (en) 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
DE102018124695A1 (de) 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US10529650B2 (en) 2017-11-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11031342B2 (en) 2017-11-15 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10535636B2 (en) * 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US10784203B2 (en) 2017-11-15 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10522501B2 (en) 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
CN107887366A (zh) * 2017-12-04 2018-04-06 中芯长电半导体（江阴）有限公司 扇出型天线封装结构及其制备方法
KR101982061B1 (ko) 2017-12-19 2019-05-24 삼성전기주식회사 반도체 패키지
US10468339B2 (en) 2018-01-19 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US11488881B2 (en) 2018-03-26 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11062915B2 (en) 2018-03-29 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures for semiconductor packages and methods of forming the same
US10631392B2 (en) 2018-04-30 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. EUV collector contamination prevention
US10510595B2 (en) 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US10658287B2 (en) * 2018-05-30 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a tapered protruding pillar portion
US10340249B1 (en) 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10886231B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming RDLS and structure formed thereof
US11049805B2 (en) 2018-06-29 2021-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11004803B2 (en) 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
US10825696B2 (en) 2018-07-02 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Cross-wafer RDLs in constructed wafers
US10515848B1 (en) 2018-08-01 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10658348B2 (en) 2018-09-27 2020-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices having a plurality of first and second conductive strips
US10832985B2 (en) 2018-09-27 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor package and method
DE102019101999B4 (de) 2018-09-28 2021-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung mit mehreren polaritätsgruppen
US10861841B2 (en) 2018-09-28 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with multiple polarity groups
US11164754B2 (en) 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same
US10665520B2 (en) 2018-10-29 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217538B2 (en) 2018-11-30 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11121089B2 (en) 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11011451B2 (en) 2018-12-05 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217546B2 (en) 2018-12-14 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded voltage regulator structure and method forming same
US11538735B2 (en) 2018-12-26 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming integrated circuit packages with mechanical braces
US10978382B2 (en) 2019-01-30 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11145560B2 (en) 2019-04-30 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacturing
US10950519B2 (en) 2019-05-31 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11088094B2 (en) 2019-05-31 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Air channel formation in packaging process
US11133282B2 (en) 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
US11380620B2 (en) 2019-06-14 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including cavity-mounted device
US11004758B2 (en) 2019-06-17 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11133258B2 (en) 2019-07-17 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package with bridge die for interconnection and method forming same
US11387191B2 (en) 2019-07-18 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US10879114B1 (en) 2019-08-23 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive fill
US11532533B2 (en) 2019-10-18 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11387222B2 (en) 2019-10-18 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11211371B2 (en) 2019-10-18 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
DE102020114141B4 (de) 2019-10-18 2024-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltungspackage und verfahren
US11227837B2 (en) 2019-12-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11227795B2 (en) 2020-01-17 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11515224B2 (en) 2020-01-17 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with enlarged through-vias in encapsulant
US11682626B2 (en) 2020-01-29 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Chamfered die of semiconductor package and method for forming the same
US11393746B2 (en) 2020-03-19 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcing package using reinforcing patches
TWI777467B (zh) * 2020-03-30 2022-09-11 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11948930B2 (en) 2020-04-29 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacturing the same
US11929261B2 (en) 2020-05-01 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US11942417B2 (en) 2020-05-04 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor package and method
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
US11532524B2 (en) 2020-07-27 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit test method and structure thereof
US11652037B2 (en) 2020-07-31 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacture
US11454888B2 (en) 2020-09-15 2022-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11868047B2 (en) 2020-09-21 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. Polymer layer in semiconductor device and method of manufacture
US11830821B2 (en) 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW448522B (en) * 2000-06-03 2001-08-01 Siliconware Precision Industries Co Ltd Structure body of semiconductor chips with stacked connection in a flip chip manner and its manufacturing method
CN101410973A (zh) * 2003-07-11 2009-04-15 快捷韩国半导体有限公司 晶片级芯片尺寸封装及其制造和使用方法
CN102194711A (zh) * 2010-02-25 2011-09-21 新科金朋有限公司 半导体器件和在fo-wlcsp中形成ipd的方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5643804A (en) 1993-05-21 1997-07-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a hybrid integrated circuit component having a laminated body
US5874770A (en) 1996-10-10 1999-02-23 General Electric Company Flexible interconnect film including resistor and capacitor layers
US6291264B1 (en) * 2000-07-31 2001-09-18 Siliconware Precision Industries Co., Ltd. Flip-chip package structure and method of fabricating the same
US6534374B2 (en) 2001-06-07 2003-03-18 Institute Of Microelectronics Single damascene method for RF IC passive component integration in copper interconnect process
US6551863B2 (en) * 2001-08-30 2003-04-22 Micron Technology, Inc. Flip chip dip coating encapsulant
US6781229B1 (en) * 2001-12-19 2004-08-24 Skyworks Solutions, Inc. Method for integrating passives on-die utilizing under bump metal and related structure
US6878633B2 (en) 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
JP4576558B2 (ja) 2005-03-15 2010-11-10 カシオ計算機株式会社 回路基板への半導体装置の実装方法及び液晶表示装置の製造方法
TWI296845B (en) 2006-05-17 2008-05-11 Via Tech Inc Multilayer winding inductor
US7524731B2 (en) 2006-09-29 2009-04-28 Freescale Semiconductor, Inc. Process of forming an electronic device including an inductor
US8133762B2 (en) 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US8124490B2 (en) * 2006-12-21 2012-02-28 Stats Chippac, Ltd. Semiconductor device and method of forming passive devices
US7919868B2 (en) * 2007-08-15 2011-04-05 Qimonda Ag Carrier substrate and integrated circuit
US7986023B2 (en) 2007-09-17 2011-07-26 Infineon Technologies Ag Semiconductor device with inductor
US8084859B2 (en) 2007-10-12 2011-12-27 Panasonic Corporation Semiconductor device
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW448522B (en) * 2000-06-03 2001-08-01 Siliconware Precision Industries Co Ltd Structure body of semiconductor chips with stacked connection in a flip chip manner and its manufacturing method
CN101410973A (zh) * 2003-07-11 2009-04-15 快捷韩国半导体有限公司 晶片级芯片尺寸封装及其制造和使用方法
CN102194711A (zh) * 2010-02-25 2011-09-21 新科金朋有限公司 半导体器件和在fo-wlcsp中形成ipd的方法

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