CN102194711A - 半导体器件和在fo-wlcsp中形成ipd的方法 - Google Patents

半导体器件和在fo-wlcsp中形成ipd的方法 Download PDF

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CN102194711A
CN102194711A CN2011100460849A CN201110046084A CN102194711A CN 102194711 A CN102194711 A CN 102194711A CN 2011100460849 A CN2011100460849 A CN 2011100460849A CN 201110046084 A CN201110046084 A CN 201110046084A CN 102194711 A CN102194711 A CN 102194711A
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conductive layer
insulating barrier
semiconductor element
layer
semiconductor
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CN102194711B (zh
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林耀剑
R.C.弗里
P.C.马里穆图
刘凯
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件和在FO-WLCSP中形成IPD的方法。一种半导体晶片包含半导体管芯。第一导电层形成在管芯上。电阻层形成在管芯和第一导电层上。第一绝缘层形成在管芯和电阻层上。晶片被单体化以分离管芯。该管芯被安装到临时载体。密封剂沉积在该管芯和载体上。该载体和第一绝缘层以及密封剂的一部分被除去。第二绝缘层形成在密封剂和第一绝缘层上。第二导电层形成在第一和第二绝缘层上。第三绝缘层形成在第二绝缘层和第二导电层上。第三导电层形成在第三绝缘层和第二导电层上。第四绝缘层形成在第三绝缘层和第三导电层上。

Description

半导体器件和在FO-WLCSP中形成IPD的方法
技术领域
本发明总体上涉及半导体器件，并且更具体地涉及半导体器件和在扇出型晶片级芯片规模封装（FO-WLCSP）中形成集成无源器件（IPD）的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占用空间（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占用空间的半导体器件封装。
半导体制造的另一个目标是制造较高性能半导体器件。器件性能的提高可以通过形成能够在较高速度下工作的有源部件来实现。在高频应用中，例如射频（RF）无线通信，集成无源器件（IPD）常常被包含在半导体器件内。IPD的实例包括电阻器、电容器和电感器。典型RF系统需要在一个或多个半导体封装中的多个IPD来执行所需的电功能。
IPD通常形成在用于结构支撑的临时载体上的封装的互连结构内的管芯外部。完全制造的外部IPD和管芯具有高成本。在临时载体上的IPD钝化中已经发现了粘附问题。此外，IPD需要比基带半导体管芯更多的垂直空间，并且因此在并排的IPD管芯和基带管芯之间强加了高纵横比间隙。
发明内容
存在对在形成IPD过程中简化制造过程和降低成本的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供包含多个半导体管芯的半导体晶片，在半导体管芯上形成第一导电层，在半导体管芯和第一导电层上形成电阻层，在半导体管芯和电阻层上形成第一绝缘层，将半导体晶片单体化以分离半导体管芯，将半导体管芯安装到临时载体，在半导体管芯和临时载体上沉积密封剂，除去临时载体和密封剂以及第一绝缘层的一部分，在密封剂和第一绝缘层上形成第二绝缘层，在第一绝缘层和第二绝缘层上形成第二导电层，在第二绝缘层和第二导电层上形成第三绝缘层，在第三绝缘层和第二导电层上形成第三导电层，以及在第三绝缘层和第三导电层上形成第四绝缘层。
在另一实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供包含多个半导体管芯的半导体晶片，在半导体管芯上形成电容器，将半导体晶片单体化以分离半导体管芯，将半导体管芯安装到载体，在半导体管芯和载体上沉积密封剂，除去载体，在密封剂和半导体管芯上形成第一绝缘层，在第一绝缘层和电容器上形成第一导电层，在第一绝缘层和第一导电层上形成第二绝缘层，在第二绝缘层和第一导电层上形成第二导电层，以及在第二绝缘层和第二导电层上形成第三绝缘层。
在另一实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供半导体管芯，在半导体管芯上形成电容器，在半导体管芯上沉积密封剂，以及在密封剂和半导体管芯上形成互连结构。互连结构包括与半导体管芯的占用空间相距预定距离形成的电感器。
在另一实施例中，本发明是一种半导体器件，该半导体器件包括半导体管芯和形成在半导体管芯上的电容器。密封剂沉积在半导体管芯上。互连结构形成在密封剂和半导体管芯上。互连结构包括与半导体管芯的占用空间相距预定距离形成的电感器。
附图说明
图1示出具有安装到其表面的不同类型封装的PCB；
图2a-2c示出安装到所述PCB的半导体封装的更多细节；
图3a-3n示出在FO-WLCSP中形成IPD的过程；
图4示出在FO-WLCSP中形成IPD的另一实施例；
图5示出来自图4的IPD和FO-WLCSP的底视图；
图6示出在单体化之前在MIM电容器的介电层中形成的通路和导电层；以及
图7示出并排的IPD管芯和基带管芯。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electroless plating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区（saw street）或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（land grid array，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quad flat non-leaded package，QFN）70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料（例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag））的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60 利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
相对于图1和2a-2c，图3a-3n示出在半导体管芯上形成IPD结构的过程。图3a示出具有基本衬底材料的半导体晶片120，所述基本衬底材料例如是用于结构支撑的硅、锗、砷化镓、磷化铟或碳化硅。如上所述，多个半导体管芯或部件124形成在晶片120上，被划片街区（saw street）126分开。
图3b示出半导体晶片120的一部分的截面图。每个半导体管芯124具有有源表面128，其包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面128内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
利用PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或介电层130形成在半导体管芯124的有源表面128上。绝缘层130可以是一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、聚酰亚胺、苯并环丁烯（benzocyclobutene，BCB）、聚苯并恶唑（polybenzoxazole，PBO）或其它适当的介电材料。在一个实施例中，绝缘层130是热氧化物。绝缘层130用于平面化半导体晶片120的表面以改善随后的沉积和光刻处理步骤的阶梯覆盖（step coverage）。可选的导电通路135可以被形成为通过绝缘层130。
使用图案化和PVD、CVD、电解电镀、无电极电镀（electroless plating）工艺、或其它合适的金属沉积工艺在绝缘层130上形成导电层132。导电层132可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。
使用PVD、CVD或其它合适的沉积工艺在绝缘层130和导电层132上形成可选的电阻层134。电阻层134a形成在绝缘层130上，并且电阻层134b形成在导电层132上。在一个实施例中，电阻层134可以是硅化钽（TaxSiy）或其它金属硅化物、TaN、镍铬（NiCr）、钛（Ti）、氮化钛（TiN）、钛钨（TiW）、或掺杂的多晶硅，其具有在5和100欧姆每平方（Ohm/sq）之间的电阻率。导电层132和电阻层134a通过导电通路135电连接到半导体管芯124的有源表面128上的电路。
在图3c中，使用图案化和PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或介电层136形成在整个有源表面128上，包括绝缘层130和电阻层134。绝缘层136可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO或其它适当的介电材料。
在图3d中，利用锯条或激光切割装置138将半导体晶片120单体化成单个半导体管芯144。
在图3e中，衬底或载体140包含临时或牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或用于结构支撑的其它合适的低成本、刚性材料。可以在载体140上形成可选界面层142作为临时双面粘合带或结合膜。采用拾取和放置操作，且以绝缘层136为首，将图3a-3d中描述的组件144安装到载体140，如图3e-3f所示。
图3g示出利用浆料印刷（paste printing）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器（applicator）沉积在半导体管芯124和载体140上的密封剂或模塑料146。密封剂146可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂146不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
图3h示出利用研磨器147从半导体管芯124的与有源表面128相对的后表面148除去体材料和密封剂146的一部分的可选步骤。在该可选的研磨工艺之后，半导体管芯124的后表面148与密封剂146的顶表面为共平面的。
继续图3g，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模来除去载体140和界面层142。该除去工艺还消除了密封剂146和绝缘层130的一部分，如图3i所示。
在第一光刻工艺中，通过PVD、CVD、印刷、旋涂、喷涂或热氧化将绝缘或钝化层150形成在绝缘层136和密封剂146上，如图3j所示。绝缘层150可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有合适的绝缘特性的其它材料。在一个实施例中，绝缘层150是聚合物电介质。通过刻蚀工艺除去绝缘层150的一部分来图案化绝缘层150以暴露绝缘层136和电阻层134a和134b。绝缘层150可以用作用于后续处理步骤的掩模。
在图3k中，使用图案化和PVD、CVD、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层136和绝缘层150上形成导电层152，以形成单个部分或部152a-152c。导电层152可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。取决于单个半导体管芯的连接性，导电层152a-152c的各个部分可以是电学上共通的（common）或者是电学上隔离的。
在第二光刻工艺中，使用图案化和PVD、CVD、印刷、旋涂、喷涂或热氧化在绝缘层150和导电层152上形成绝缘或钝化层154。绝缘层154可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有合适的绝缘特性的其它材料。在一个实施例中，绝缘层154是聚合物电介质。通过刻蚀工艺除去绝缘层154的一部分来图案化绝缘层154以暴露导电层152并且可选地形成通路以暴露电阻层134a和134b。
在图3l中，使用图案化和PVD、CVD、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在导电层152、绝缘层154和电阻层134上形成导电层156，以形成单个部分或部156a-156i。导电层156可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。取决于单个半导体管芯的连接性，导电层156a-156i的各个部分可以是电学上共通的或者是电学上隔离的。
在第三光刻工艺中，使用旋涂、PVD、CVD、印刷、烧结或热氧化在绝缘层154和导电层156上形成绝缘或钝化层158。绝缘层158可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有合适的绝缘特性的其它材料。在一个实施例中，绝缘层158是聚合物电介质。通过刻蚀工艺除去绝缘层158的一部分来图案化绝缘层158以暴露导电层156a、156h和156i。
使用PVD、CVD、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在导电层156a、156h和156i上形成可选的导电层160。导电层160可以是一层或多层的Ti、TiW、NiV、Cr、CrCu、Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。在一个实施例中，导电层160是包含具有粘附层、阻挡层、和种子或润湿层的多层金属堆叠的凸块下金属化（UBM）。粘附层形成在导电层156a、156h和156i上，并且可以是Ti、TiN、TiW、Al、或铬（Cr）。阻挡层形成在粘附层上并且可以由Ni、镍钒（NiV）、铂（Pt）、钯（Pd）、TiW、或铬铜（CrCu）制成。阻挡层阻止Cu扩散到管芯的有源区中。种子层可以是Cu、Ni、NiV、Au、或Al。种子层形成在阻挡层上并且用作导电层156a、156h和156i与随后的焊料凸块或其它互连结构之间的中间导电层。UBM 160提供到导电层156a、156h和156i的低电阻互连，还提供对焊料扩散的阻挡以及用于焊料可湿性的种子层。
在图3m中，使用蒸发、电解电镀、无电极电镀、球滴（ball drop）或丝网印刷工艺在UBM 160上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，和其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到UBM 160。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块162。在一些应用中，凸块162二次回流以改善到UBM 160的电接触。所述凸块也可以被压缩结合到UBM 160。凸块162表示一种可以形成在UBM 160上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。导电层152和156、凸块162以及绝缘层150、154和158构成FO-WLCSP 166的装配互连结构164。
图3i-3n中描述的结构构成多个无源电路元件或IPD。在一个实施例中，导电层156g和152b、绝缘层136、电阻层134b和导电层132构成金属绝缘体金属（MIM）电容器168。在导电层156g和156h之间的电阻层134a是该无源电路中的电阻器元件。导电层156b-156e的各个部分在平面图中可以是缠绕的或者是绕成线圈的，以产生或展示出电感器170的期望特性。导电层156b-156e形成在距离半导体管芯124的占位面积至少50微米处，以减小与MIM电容器168的器件间干扰。图3n示出FO-WLCSP 166的底视图。
IPD结构168-170提供高频应用所需的电特性，所述高频应用例如是谐振器、高通滤波器、低通滤波器、带通滤波器、对称Hi-Q谐振变压器、匹配网络和调谐电容器。IPD可以用作前端无线RF部件，其可以布置在天线和收发器之间。电感器可以是hi-Q平衡-不平衡变换器（balun）、变压器或线圈，在高达100吉赫下工作。在一些应用中，多个平衡-不平衡变换器形成在同一衬底上，允许多带工作。例如，两个或更多个平衡-不平衡变换器在四频中（in a quad-band）用于移动电话或用于移动（GSM）通信的其它全球系统，每个平衡-不平衡变换器专用于四频器件的操作频带。典型RF系统需要在一个或多个半导体封装中的多个IPD和其它高频电路来执行所需的电功能。
形成在半导体管芯124上的IPD结构168简化了制造过程并降低了成本。在沉积密封剂146之前，MIM电容器168和电阻器134b形成在半导体管芯124上。其它IPD，例如电感器170形成在密封之后，这通过减少下述所需的光刻层数目而节省了制造成本：一层用于回蚀绝缘层150并形成导电层152，一层用于回蚀绝缘层154并形成导电层156，以及一层用于回蚀绝缘层158并形成凸块162。此外，通过在半导体管芯124上仅形成MIM电容器和电阻器134b，并且形成在并排的IPD管芯和基带管芯之间的间隙的纵横比可以被减小，参见图7。
图4示出从图3j继续的替换实施例，使用图案化和PVD、CVD、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层136和绝缘层150上形成导电层172，以形成单个部分或部172a-172f。导电层172可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。取决于单个半导体管芯的连接性，导电层172a-172f的各个部分可以是电学上共通的或者是电学上隔离的。例如，导电层172b电连接到电阻层134b，并且导电层172d-172e电连接到电阻层134a。
使用图案化和PVD、CVD、印刷、旋涂、喷涂或热氧化在绝缘层150和导电层172上形成绝缘或钝化层174。绝缘层174可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有合适的绝缘特性的其它材料。在一个实施例中，绝缘层174是聚合物电介质。通过刻蚀工艺除去绝缘层174的一部分来图案化绝缘层174以暴露导电层172。
使用图案化和PVD、CVD、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在导电层172和绝缘层174上形成导电层176，以形成单个部分或部176a-176i。导电层176可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。取决于单个半导体管芯的连接性，导电层176a-176i的各个部分可以是电学上共通的或者是电学上隔离的。例如，导电层176a和176d电连接到导电层172a，导电层176f电连接到导电层172b，导电层176g电连接到导电层172c-172d，导电层176h电连接到导电层172e-172f，导电层176i电连接到导电层172f。
使用旋涂、PVD、CVD、印刷、烧结或热氧化在绝缘层174和导电层176上形成绝缘或钝化层178。绝缘层178可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有合适的绝缘特性的其它材料。在一个实施例中，绝缘层178是聚合物电介质。通过刻蚀工艺除去绝缘层178的一部分来图案化绝缘层178以暴露导电层176a、176h和176i。
使用PVD、CVD、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在导电层176a、176h和176i上形成可选的导电层180。导电层180可以是一层或多层的Ti、TiW、NiV、Cr、CrCu、Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。在一个实施例中，类似于导电层160，导电层180是包含具有粘附层、阻挡层、和种子或润湿层的多层金属堆叠的UBM。
使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在UBM 180上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，和其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到UBM 180。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块182。在一些应用中，凸块182二次回流以改善到UBM 180的电接触。所述凸块也可以被压缩结合到UBM 180。凸块182表示一种可以形成在UBM 180上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。导电层172和176、凸块182以及绝缘层150、174和178构成FO-WLCSP 186的装配互连结构184。
图4中描述的结构构成多个无源电路元件或IPD。在一个实施例中，导电层172c和176g、绝缘层136、电阻层134b和导电层132构成MIM电容器187。在导电层172d和172e之间的电阻层134a是该无源电路中的电阻器元件。导电层176b-176e的各个部分在平面图中可以是缠绕的或者是绕成线圈的，以产生或展示出电感器188的期望特性。图5示出FO-WLCSP 186的底视图。
图6示出类似于图4的替换实施例，其中在单体化之前刻蚀绝缘层136。使用图案化和PVD、CVD、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层136的被除去的部分中形成导电层190，以形成单个部分或部190a-190f。导电层190可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。取决于单个半导体管芯的连接性，导电层190a-190f的各个部分可以是电学上共通的或者是电学上隔离的。例如，导电层190a电连接到电阻层134b，并且导电层190c-190d电连接到电阻层134a。
图7示出包含模拟或数字电路的半导体管芯194，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、或形成在其有源表面内的其它电路元件，以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。被实施为导电层156的电感器170、半导体管芯124和MIM电容器168利用迹线196电连接到半导体管芯194。半导体管芯194和WLCSP 166并排安装在封装200内且迹线196通往外部引脚202。形成在半导体管芯124上的IPD结构168简化了制造过程并降低了成本。在沉积密封剂146之前，MIM电容器168和电阻器134b形成在半导体管芯124上。其它IPD，例如电感器170形成在密封之后，这通过减少下述所需的光刻层数目而节省了制造成本：一层用于回蚀绝缘层150并形成导电层152，一层用于回蚀绝缘层154并形成导电层156，以及一层用于回蚀绝缘层158并形成凸块162。此外，通过在半导体管芯124上仅形成MIM电容器和电阻器134b，并且形成在并排的IPD管芯和基带管芯之间的间隙的纵横比可以被减小。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (25)

1. 一种制造半导体器件的方法，包括：
提供包含多个半导体管芯的半导体晶片；
在半导体管芯上形成第一导电层；
在半导体管芯和第一导电层上形成电阻层；
在半导体管芯和电阻层上形成第一绝缘层；
将半导体晶片单体化以分离半导体管芯；
将半导体管芯安装到临时载体；
在半导体管芯和临时载体上沉积密封剂；
除去临时载体和密封剂以及第一绝缘层的一部分；
在密封剂和第一绝缘层上形成第二绝缘层；
在第一绝缘层和第二绝缘层上形成第二导电层；
在第二绝缘层和第二导电层上形成第三绝缘层；
在第三绝缘层和第二导电层上形成第三导电层；以及
在第三绝缘层和第三导电层上形成第四绝缘层。
2. 根据权利要求1的方法，进一步包括除去密封剂的一部分和半导体管芯的后表面。
3. 根据权利要求1的方法，进一步包括在电阻层上形成第三导电层。
4. 根据权利要求1的方法，进一步包括在电阻层上形成第二导电层。
5. 根据权利要求1的方法，进一步包括：
在单体化半导体晶片之前除去第一绝缘层的一部分以暴露电阻层；以及
在电阻层上形成第四导电层。
6. 根据权利要求1的方法，进一步包括在形成第一导电层和电阻层之前在半导体晶片的表面上形成第五绝缘层。
7. 一种制造半导体器件的方法，包括：
提供包含多个半导体管芯的半导体晶片；
在半导体管芯上形成电容器；
将半导体晶片单体化以分离半导体管芯；
将半导体管芯安装到载体；
在半导体管芯和载体上沉积密封剂；
除去载体；
在密封剂和半导体管芯上形成第一绝缘层；
在第一绝缘层和电容器上形成第一导电层；
在第一绝缘层和第一导电层上形成第二绝缘层；
在第二绝缘层和第一导电层上形成第二导电层；以及
在第二绝缘层和第二导电层上形成第三绝缘层。
8. 根据权利要求7的方法，其中形成电容器包括：
在半导体管芯上形成第三导电层；
在半导体管芯和第三导电层上形成电阻层；
在半导体管芯和电阻层上形成第四绝缘层；以及
在第四绝缘层上形成第一导电层。
9. 根据权利要求8的方法，进一步包括：
在单体化半导体晶片之前除去第四绝缘层的一部分以暴露电阻层；以及
在电阻层上形成第四导电层。
10. 根据权利要求7的方法，进一步包括在电阻层上形成第二导电层。
11. 根据权利要求7的方法，进一步包括在电阻层上形成第一导电层。
12. 根据权利要求7的方法，进一步包括在形成第一导电层和电阻层之前在半导体晶片的表面上形成第五绝缘层。
13. 根据权利要求7的方法，进一步包括在第二导电层上形成凸块。
14. 一种制造半导体器件的方法，包括：
提供半导体管芯；
在半导体管芯上形成电容器；
在半导体管芯上沉积密封剂；以及
在密封剂和半导体管芯上形成互连结构，所述互连结构包括与半导体管芯的占用空间相距预定距离形成的电感器。
15. 根据权利要求14的方法，其中形成互连结构包括：
在密封剂和半导体管芯上形成第一绝缘层；
在第一绝缘层和电容器上形成第一导电层；
在第一绝缘层和第一导电层上形成第二绝缘层；
在第二绝缘层和第一导电层上形成第二导电层，第二导电层具有形成在离半导体管芯的占位面积预定距离处并且被缠绕以用作电感器的部分；以及
在第二绝缘层和第二导电层上形成第三绝缘层。
16. 根据权利要求15的方法，其中第二导电层的被缠绕以用作电感器的所述部分距离半导体管芯至少50微米。
17. 根据权利要求15的方法，进一步包括在电阻层上形成第二导电层。
18. 根据权利要求15的方法，进一步包括在电阻层上形成第一导电层。
19. 根据权利要求15的方法，进一步包括在第二导电层上形成凸块。
20. 根据权利要求15的方法，其中形成电容器包括：
在半导体管芯上形成第三导电层；
在半导体管芯和第三导电层上形成电阻层；
在半导体管芯和电阻层上形成第四绝缘层；以及
在第四绝缘层上形成第一导电层。
21. 一种半导体器件，包括：
半导体管芯；
形成在半导体管芯上的电容器；
沉积在半导体管芯上的密封剂；以及
形成在密封剂和半导体管芯上的互连结构，所述互连结构包括与半导体管芯的占用空间相距预定距离形成的电感器。
22. 根据权利要求21的半导体器件，其中所述互连结构包括：
在密封剂和半导体管芯上形成第一绝缘层；
在第一绝缘层和电容器上形成第一导电层；
在第一绝缘层和第一导电层上形成第二绝缘层；
在第二绝缘层和第一导电层上形成第二导电层，第二导电层具有形成在离半导体管芯的占位面积预定距离处并且被缠绕以用作电感器的部分；以及
在第二绝缘层和第二导电层上形成第三绝缘层。
23. 根据权利要求22的半导体器件，其中形成电容器包括：
在半导体管芯上形成第三导电层；
在半导体管芯和第三导电层上形成电阻层；
在半导体管芯和电阻层上形成第四绝缘层；以及
在第四绝缘层上形成第一导电层。
24. 根据权利要求22的半导体器件，进一步包括形成在第二导电层上的凸块。
25. 根据权利要求22的半导体器件，其中第二导电层的被缠绕以用作电感器的所述部分距离半导体管芯至少50微米。
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US10475779B2 (en) 2008-12-12 2019-11-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
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CN102194711B (zh) 2016-02-24
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