CN103187372B - 芯片封装结构 - Google Patents
芯片封装结构 Download PDFInfo
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- CN103187372B CN103187372B CN201210567748.0A CN201210567748A CN103187372B CN 103187372 B CN103187372 B CN 103187372B CN 201210567748 A CN201210567748 A CN 201210567748A CN 103187372 B CN103187372 B CN 103187372B
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- thermoelectric element
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 51
- 230000017525 heat dissipation Effects 0.000 claims abstract description 42
- 239000000084 colloidal system Substances 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 11
- 238000012856 packing Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 239000002041 carbon nanotube Substances 0.000 claims description 6
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 6
- 238000004146 energy storage Methods 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 229910000765 intermetallic Inorganic materials 0.000 claims description 3
- 230000005619 thermoelectricity Effects 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910002665 PbTe Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 2
- 238000013519 translation Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910010380 TiNi Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910008340 ZrNi Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 1
- 239000010930 yellow gold Substances 0.000 description 1
- 229910001097 yellow gold Inorganic materials 0.000 description 1
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Abstract
本发明公开一种芯片封装结构,其包括载板、第一、二芯片、凸块、第一、二菊链线路、异质热电元件对、第一、二散热元件与封装胶体。第一芯片配置于载板上。第一芯片的第一背面朝向载板的第一表面,第一芯片的第一有源面上具有第一接垫。第二芯片配置于第一芯片上并与载板电连接。第二芯片的第二有源面朝向第一有源面且具有第二接垫。凸块连接第一、二接垫。第一、二菊链线路分别配置于第一、二有源面上。异质热电元件对通过第一、二菊链线路串联连接且与外部元件构成封闭回路。第一、二散热元件分别配置于载板的第二表面与第二芯片的第二背面上。
Description
技术领域
本发明涉及一种芯片封装结构,且特别是涉及一种具有热电转换功能的芯片封装结构。
背景技术
一般而言,集成电路(integratedcircuit,IC)制造完成后需经过封装制作工艺来保护芯片免于外力破坏,并且将芯片上的电极通过载板扩大电极间距而引接至外部装置(例如:印刷电路板、显示面板等)。球格阵列封装(BallGridArray,BGA)、薄膜倒装(chip-on-film,COF)封装皆为常见的封装技术。
电子产品的功能不断地扩充而体积及重量则不断地缩小,促使芯片功能需求持续增加,相对应地I/O端点数目增加,而芯片尺寸则持续在缩小,芯片与载板之间的间距也随之缩小。然而,芯片功能增加伴随而来的还有运作过程中产生的热也增加,而热对于元件效能的影响也趋于明显。
因此,如何回收且重新利用芯片运作过程中所产生的热来进行热电转换已成为近年来产业研发的重点技术之一。
发明内容
本发明的目的在于提供一种芯片封装结构,其具有热电转换功能。
为达上述目的,本发明提出一种芯片封装结构,其包括载板、第一芯片、第二芯片、多个凸块、第一菊链线路、第二菊链线路、多个异质(hetero)热电元件对、第一散热元件、第二散热元件以及封装胶体。载板具有彼此相对的第一表面与第二表面。第一芯片配置于载板上。第一芯片具有第一有源面与第一背面。第一背面朝向第一表面,且第一有源面上具有多个第一接垫。第二芯片配置于第一芯片上,并与载板电连接。第二芯片具有第二有源面与第二背面。第二有源面朝向第一有源面,且第二有源面上具有多个第二接垫。凸块连接第一接垫与第二接垫,且作为第一芯片与第二芯片的电性传输接点。第一菊链线路配置于第一有源面上,且与第一芯片电性分离。第二菊链线路配置于第二有源面上,且与第二芯片电性分离。异质热电元件对配置于第一芯片与第二芯片之间,并通过第一菊链线路与第二菊链线路而串联连接,且这些异质热电元件对与外部元件构成封闭回路。第一散热元件配置于载板的第二表面上。第二散热元件配置于第二芯片的第二背面上。第一散热元件与第二散热元件具有不同的散热效率。封装胶体包覆载板、第一芯片与第二芯片。
本发明另提出一种芯片封装结构,其包括载板、第一芯片、第二芯片、第三芯片、多个凸块、多个第一导通孔、第一菊链线路、第二菊链线路、第三菊链线路、第四菊链线路、第二导通孔、多个异质热电元件对、第一散热元件、第二散热元件以及封装胶体。载板具有彼此相对的第一表面与第二表面。第一芯片配置于载板上。第一芯片具有第一有源面与第一背面。第一背面朝向第一表面,且第一有源面上具有多个第一接垫。第二芯片配置于第一芯片上。第二芯片具有第二有源面与第二背面。第二有源面朝向第一有源面,且第二有源面具有多个第二接垫,而第二背面具有多个第三接垫。第三芯片配置于第二芯片上,并与载板电连接。第三芯片具有第三有源面与第三背面。第三有源面朝向第二背面,且第三有源面上具有多个第四接垫。凸块连接第一接垫与第二接垫,以及连接第三接垫与第四接垫。第一导通孔配置于第二芯片中,并连接第二接垫与第三接垫。第一菊链线路配置于第一有源面上,且与第一芯片电性分离。第二菊链线路配置于第二有源面上,且与第二芯片电性分离。第三菊链线路配置于第二背面上,且与第二芯片电性分离。第四菊链线路配置于第三有源面上,且与第三芯片电性分离。第二导通孔配置于第二芯片中,并连接第二菊链线路与第三菊链线路。异质热电元件对配置于第一芯片与第二芯片之间以及配置于第二芯片与第三芯片之间,并通过第一菊链线路、第二菊链线路、第二导通孔、第三菊链线路与第四菊链线路而串联连接,且这些异质热电元件对与外部元件构成封闭回路。第一散热元件配置于载板的该第二表面上。第二散热元件配置于第三芯片的第三背面上。第一散热元件与第二散热元件具有不同的散热效率。封装胶体包覆载板、第一芯片、第二芯片与第三芯片。
为让本发明的上述特征能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1为本发明第一实施例所绘示的芯片封装结构的剖面示意图;
图2为本发明第二实施例所绘示的芯片封装结构的剖面示意图;
图3为本发明第三实施例所绘示的芯片封装结构的剖面示意图;
图4为本发明第四实施例所绘示的芯片封装结构的剖面示意图。
主要元件符号说明
10、20、30、40:芯片封装结构
100:载板
100a:第一表面
100b:第二表面
102:第一芯片
102a:第一有源面
102b:第一背面
102c:第一接垫
104:第二芯片
104a:第二有源面
104b:第二背面
104c:第二接垫
104d:第三接垫
105、304、402:打线
106、404:凸块
108:第一菊链线路
109、111、408、412:绝缘层
110:第二菊链线路
112:异质热电元件对
112a:第一热电元件
112b:第二热电元件
114:第一散热元件
115:外部元件
116:第二散热元件
118:封装胶体
200、300、302:内连线
202:线路层
400:第三芯片
400a:第三有源面
400b:第三背面
400c:第四接垫
406:第一导通孔
407:第三菊链线路
410:第四菊链线路
414:第二导通孔
416:第三导通孔
418:线路层
具体实施方式
第一实施例
图1为依照本发明第一实施例所绘示的芯片封装结构的剖面示意图。请参照图1,芯片封装结构10包括载板100、第一芯片102、第二芯片104、凸块106、第一菊链线路108、第二菊链线路110、异质热电元件对112、第一散热元件114、第二散热元件116以及封装胶体118。载板100具有彼此相对的第一表面100a与第二表面100b。载板100可以是硅芯片、碳化硅芯片、氮化镓经片、有机载板、无机载板或金属载板。载板100用以承载配置于其上的芯片与其他构件。
第一芯片102具有彼此相对的第一有源面102a与第一背面102b。第一芯片102以第一背面102b朝向第一表面100a的方式配置于载板100上。第一有源面102a上具有多个第一接垫102c。本发明对第一芯片102的种类并不作任何限制。在本实施例中,第一芯片102例如为高功率芯片或高发热芯片。
第二芯片104具有彼此相对的第二有源面104a与第二背面104b。第二芯片104以第二有源面104a朝向第一有源面100a的方式配置于第一芯片102上,亦即第二芯片104以倒装(flipchip)的方式配置于第一芯片102上。第二有源面104a上具有多个第二接垫104c。此外,在本实施例中,第二芯片104通过打线105而电连接至载板100。本发明对第二芯片104的种类并不作任何限制。在本实施例中,第二芯片104例如为高功率芯片或高发热芯片。
凸块106连接第一接垫102c与第二接垫104c,用以电连接第一芯片102与第二芯片104。第一菊链线路108配置于第一有源面102a上。在本实施例中,第一菊链线路108与第一有源面102a之间配置有绝缘层109,以使第一菊链线路108与第一芯片102电性分离。第二菊链线路110配置于第二有源面104a上。在本实施例中,第二菊链线路110与第二有源面104a之间配置有绝缘层111,以使第二菊链线路110与第二芯片104电性分离。也就是说,第一菊链线路108并非第一芯片102中用以传导电流的线路层,且第二菊链线路110并非第二芯片104中用以传导电流的线路层。
异质热电元件对112配置于第一芯片102与第二芯片104之间,并通过第一菊链线路108与第二菊链线路110而串联连接。此外,这些异质热电元件对112与外部元件115构成封闭回路。详细地说,在本实施例中,多个异质热电元件对112通过第一菊链线路108与第二菊链线路110而彼此串联连接成一个热电模块,且此热电模块的两个端点分别经由打线113而连接至外部元件115。外部元件115例如为储能元件,以储存热电模块所产生的电能。上述储能元件可以是电池或电容器等可储存电能的元件。
以下进一步说明本实施例中的异质热电元件对112。每一个异质热电元件对112包括第一热电元件112a与第二热电元件112b。第一热电元件112a与第二热电元件112b具有不同的席贝克(Seebeck)系数。通过第一芯片102与第二芯片104之间的温度差异,由异质热电元件对112、第一菊链线路108与第二菊链线路110所构成的热电模块产生席贝克效应、珀耳帖(Peltier)效应或汤姆生(Thomson)效应以达到热电转换的效果。第一热电元件112a与第二热电元件112b的材料各自例如为金属(例如镍、铋、锑)、合金(例如银铜合金、铜镍合金)、介金属化合物(例如Cu3Sn、Ag3Sn、Ni3Sn4或AuSn4)、半导体介金属(PbTe、Bi2Te3)、纳米碳管、金属玻璃或陶瓷(氮化钛或碳化钛)。本发明对于第一热电元件112a的材料与第二热电元件112b的材料的组合并不做任何限制,只要第一热电元件112a的材料与第二热电元件112b的材料的符合热电转换特性的定义即可。此外,在其他实施例中,经由材料的选择,第一热电元件112a可为P型热电元件与N型热电元件中的一者,而第二热电元件112b则为P型热电元件与N型热电元件中的另一者。P型热电元件的材料例如为BiTe或Cu0.5Ag0.5InTe2。N型热电元件的材料例如为PbTe、ZrNi3Sn4或TiNi3Sn4。
第一散热元件114配置于载板100的第二表面100b上。第二散热元件116配置于第二芯片104的第二背面104b上。第一散热元件114与第二散热元件116具有不同的散热效率。本发明对第一散热元件114与第二散热元件116的种类并不做任何限定。第一散热元件114与第二散热元件116可具有不同的材料、尺寸、散热方式,以达成分别具有不同的散热效率。由于第一散热元件114与第二散热元件具有不同的散热效率,使得异质热电元件对112的两端(分别为邻近第一芯片102与第二芯片104的部分)之间可以具有大的温差梯度,以延长达到热平衡的时间,因而可持续产生电能。
封装胶体118包覆载板100、第一芯片102与第二芯片104,以保护载板100、第一芯片102、第二芯片104以及位于第一芯片102与第二芯片104之间的各个构件。
第二实施例
图2为依照本发明第二实施例所绘示的芯片封装结构的剖面示意图。在图2中,与图1相同构件将以相同的标号表示,于此不另行说明。请参照图2,在本实施例中,芯片封装结构20与芯片封装结构10的差异在于:在芯片封装结构20中,第二芯片104通过内连线200而电连接至载板100。此外,内连线200中的线路层202位于第二芯片104上,除了用以电连接第二芯片104与载板100之外,还可取代芯片封装结构10中的第二散热元件116。
第三实施例
图3为依照本发明第三实施例所绘示的芯片封装结构的剖面示意图。在图3中,与图1相同构件将以相同的标号表示,于此不另行说明。请参照图3,在本实施例中,芯片封装结构30与芯片封装结构10的差异在于:在芯片封装结构30中,第二芯片104通过内连线300而电连接至载板100。此外,由异质热电元件对112、第一菊链线路108与第二菊链线路110所构成的热电模块的两个端点分别经由内连线302以及打线304而连接至外部元件115。需要注意的是,内连线302并未穿过第二芯片104与第二散热元件116,而是绕过第二芯片104与第二散热元件116,并在封装胶体118外部通过打线304而电连接至外部元件115。
第四实施例
图4为依照本发明第四实施例所绘示的芯片封装结构的剖面示意图。在图4中,与图1相同构件将以相同的标号表示,于此不另行说明。请参照图4,在本实施例中,芯片封装结构40与芯片封装结构10的差异在于:在芯片封装结构40中,具有三个堆叠的芯片。当然,本发明并不限于此,在其他实施例中也可以是具有更多个堆叠的芯片。在芯片封装结构40中,第二芯片104上还配置有第三芯片400。详细地说,第二芯片104的第二背面104b上具有多个第三接垫104d。第三芯片400具有彼此相对的第三有源面400a与第三背面400b。第三芯片400以第三有源面400a朝向第二背面104b的方式配置于第二芯片104上,亦即第三芯片400以倒装的方式配置于第二芯片104上。此外,在本实施例中,第二芯片104并未通过打线105电连接至载板100,而是第三芯片400通过打线402而电连接至载板100。当然,在其他实施例中,第三芯片400也可通过内连线而电连接至载板100(如第三实施例所述)。第三有源面400a上具有多个第四接垫400c。凸块404连接第三接垫104d与第四接垫400c。第一导通孔406配置于第二芯片104中,并连接第二接垫104c与第三接垫104d。
此外,第三菊链线路407配置于第二背面104b上。在本实施例中,第三菊链线路407与第二背面104b之间配置有绝缘层408,以使第三菊链线路407与第二芯片104电性分离。第四菊链线路410配置于第三有源面400a上。在本实施例中,第四菊链线路410与第三有源面400a之间配置有绝缘层412,以使第四菊链线路410与第三芯片400电性分离。第二导通孔414配置于第二芯片104中,并连接第二菊链线路110与第三菊链线路407。异质热电元件对112除了配置于第一芯片102与第二芯片104之间外,也配置于第二芯片104与第三芯片400之间,并通过第三菊链线路407与第四菊链线路410而串联连接。第三导通孔416配置于第三芯片400中,并连接第四菊链线路410与线路层418。由此,多个异质热电元件对112通过第一菊链线路108、第二菊链线路110、第三菊链线路407与第四菊链线路410而彼此串联连接成一个热电模块,且此热电模块的两个端点分别经由第三导通孔416、线路层418与打线113而连接至外部元件115。当然在其他实施例中,热电模块的两个端点也可皆仅经由打线而连接至外部元件115(如第二实施例所述)。
第二散热元件116配置于第三芯片400的第三背面400b上。封装胶体118包覆载板100、第一芯片102、第二芯片104与第三芯片400,以保护载板100、第一芯片102、第二芯片104、第三芯片400以及位于第一芯片102与第二芯片104之间以及第二芯片104与第三芯片400之间的各个构件。
特别一提的是,在上述各个实施例中,第一热电元件112a、第二热电元件112b以及凸块106、404皆是采用先印刷(printing)或喷印((inject)膏状原料于第一菊链线路108,再将第二芯片104以倒装(flipchip)的方式配置于第一芯片102上,接着进行高温烧结的方式来形成第一热电元件112a、第二热电元件112b及凸块106、404。
基于上述,在本发明的芯片封装结构中,于芯片之间配置异质热电元件对,且利用二个具有不同散热效率的散热元件来制造异质热电元件对二侧的温度差异,并使异质热电元件对与外部元件构成封闭回路。因此,本发明可以有效地使用芯片运作过程中所产生的热来进行热电转换。
虽然已结合以上实施例举例说明了本发明,然而其并非用以限定本发明,任何所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应以附上的权利要求所界定的为准。
Claims (19)
1.一种芯片封装结构,包括:
载板,具有彼此相对的第一表面与第二表面;
第一芯片,配置于该载板上,该第一芯片具有第一有源面与第一背面,该第一背面朝向该第一表面,且该第一有源面上具有独立区域的多个第一接垫及绝缘层;
第二芯片,配置于该第一芯片上,并与该载板电连接,该第二芯片具有第二有源面与第二背面,该第二有源面朝向该第一有源面,且该第二有源面上具有独立区域的多个第二接垫及一绝缘层;
多个凸块,连接该多个第一接垫与该多个第二接垫,作为第一芯片与第二芯片电性导通功能;
第一菊链线路,配置于该第一有源面的绝缘层上;
第二菊链线路,配置于该第二有源面的绝缘层上;
多个异质热电元件对,配置于该第一芯片与该第二芯片之间,并通过该第一菊链线路与该第二菊链线路而串联连接,且该多个异质热电元件对与一外部元件构成一封闭回路,每一异质热电元件对包括第一热电元件与第二热电元件,且该第一热电元件与该第二热电元件具有不同的席贝克系数;
第一散热元件,配置于该载板的该第二表面上;
第二散热元件,配置于该第二芯片的该第二背面上,其中该第一散热元件与该第二散热元件具有不同的散热效率;以及
封装胶体,包覆该载板、该第一芯片与该第二芯片。
2.如权利要求1所述的芯片封装结构,其中该第一热电元件与该第二热电元件的材料各自包括金属、合金、介金属化合物、纳米碳管、金属玻璃或陶瓷。
3.如权利要求1所述的芯片封装结构,其中该第一热电元件为P型热电元件与N型热电元件中的一者,而该第二热电元件为P型热电元件与N型热电元件中的另一者。
4.如权利要求1所述的芯片封装结构,其中该第二芯片通过一打线而与该载板电连接。
5.如权利要求1所述的芯片封装结构,其中该第二芯片通过一内连线而与该载板电连接。
6.如权利要求5所述的芯片封装结构,其中该第二散热元件为该内连线的一部分。
7.如权利要求1所述的芯片封装结构,其中该多个异质热电元件对与该外部元件通过一外部连线而构成该封闭回路。
8.如权利要求1所述的芯片封装结构,其中该多个异质热电元件对与该外部元件通过一内连线与一外部连线而构成该封闭回路。
9.如权利要求1所述的芯片封装结构,其中该第一芯片及第二芯片包括高功率芯片、高发热芯片。
10.如权利要求1所述的芯片封装结构,其中该外部元件包括储能元件。
11.一种芯片封装结构,包括:
载板,具有彼此相对的一第一表面与一第二表面;
第一芯片,配置于该载板上,该第一芯片具有第一有源面与第一背面,该第一背面朝向该第一表面,且该第一有源面上具有独立区域的多个第一接垫及一绝缘层;
第二芯片,配置于该第一芯片上,该第二芯片具有第二有源面与第二背面,该第二有源面朝向该第一有源面,且该第二有源面具有独立区域的多个第二接垫及一绝缘层,而该第二背面具有独立区域的多个第三接垫及一绝缘层;
第三芯片,配置于该第二芯片上,并与该载板电连接,该第三芯片具有第三有源面与第三背面,该第三有源面朝向该第二背面,且该第三有源面上具有独立区域的多个第四接垫及一绝缘层;
多个凸块,连接该多个第一接垫与该多个第二接垫,作为第一芯片与第二芯片电性导通功能,以及连接该多个第三接垫与该多个第四接垫,作为第二芯片与第三芯片电性导通功能;
多个第一导通孔,配置于该第二芯片中,并连接该多个第二接垫与该多个第三接垫;
第一菊链线路,配置于该第一有源面的绝缘层上;
第二菊链线路,配置于该第二有源面的绝缘层上;
第三菊链线路,配置于该第二背面的绝缘层上;
第四菊链线路,配置于该第三有源面的绝缘层上;
第二导通孔,配置于该第二芯片中,并连接该第二菊链线路与该第三菊链线路;
多个异质热电元件对,配置于该第一芯片与该第二芯片之间以及配置于该第二芯片与该第三芯片之间,并通过该第一菊链线路、该第二菊链线路、该第二导通孔、该第三菊链线路与该第四菊链线路而串联连接,且该多个异质热电元件对与一外部元件构成一封闭回路,每一异质热电元件对包括第一热电元件与第二热电元件,且该第一热电元件与该第二热电元件具有不同的席贝克系数;
第一散热元件,配置于该载板的该第二表面上;
第二散热元件,配置于该第三芯片的该第三背面上,其中该第一散热元件与该第二散热元件具有不同的散热效率;以及
封装胶体,包覆该载板、该第一芯片、该第二芯片与该第三芯片。
12.如权利要求11所述的芯片封装结构,其中该第一热电元件与该第二热电元件的材料各自包括金属、合金、介金属化合物、纳米碳管、金属玻璃或陶瓷。
13.如权利要求11所述的芯片封装结构,其中该第一热电元件为P型热电元件与N型热电元件中的一者,而该第二热电元件为P型热电元件与N型热电元件中的另一者。
14.如权利要求11所述的芯片封装结构,其中该第三芯片通过一打线而与该载板电连接。
15.如权利要求11所述的芯片封装结构,其中该第三芯片通过一内连线而与该载板电连接。
16.如权利要求15所述的芯片封装结构,其中该第二散热元件为该内连线的一部分。
17.如权利要求11所述的芯片封装结构,其中该多个异质热电元件对与该外部元件通过一连线而构成该封闭回路。
18.如权利要求11所述的芯片封装结构,其中该第一芯片、第二芯片及第三芯片包括高功率芯片、高发热芯片。
19.如权利要求11所述的芯片封装结构,其中该外部元件包括储能元件。
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