CN103178782A - Frequency sweeping signal generator - Google Patents
Frequency sweeping signal generator Download PDFInfo
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- CN103178782A CN103178782A CN2011104316372A CN201110431637A CN103178782A CN 103178782 A CN103178782 A CN 103178782A CN 2011104316372 A CN2011104316372 A CN 2011104316372A CN 201110431637 A CN201110431637 A CN 201110431637A CN 103178782 A CN103178782 A CN 103178782A
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Abstract
The invention provides a frequency sweeping signal generator which comprises a processor, a storage, a user interface module, a clock circuit, a digital-to-analogue conversion module, an analog circuit module and a Field Programmable Gate Array (FPGA) chip. The FPGA chip comprises a frequency sweeping state machine, an offset multiplier, a phase accumulator and a frequency marker comparator. The frequency sweeping state machine can provide different frequency sweeping states. The offset multiplier is connected with a frequency sweeping curve storage and obtains the incremental portion of frequency sweeping frequency words through calculation. The phase accumulator is used for accumulating carrier frequency words and outputting the accumulating result. The frequency marker comparator is used for generating frequency marking signals. The FPGA is adopted as the core part of the signal generator to generate frequency sweeping signals, and the signal generator is reasonable, small in software load, fast in response and few in FPGA resource consumption. Simultaneously, the frequency sweeping signal generator is added with some functions meeting market requirements and is rich in frequency sweeping modes.
Description
Technical field
The present invention relates to signal generator, relate in particular to a kind of swept signal generator.
Background technology
The frequency of swept signal generator output signal repeats continuous variation in time according to certain rules, within the specific limits, in electronic measurements, impedance operator and the transmission characteristic of network is measured through being commonly used to.In the tradition swept signal generator, be used for producing the oscillator discrete component realization commonly used of swept-frequency signal.For example: adopt voltage variable capacitance diode in the LC oscillator, adopt the thyrite realization to the control of frequency of oscillation in the RC oscillator, utilize the inductance frequency sweep in magnetic modulation frequency sweep method.All there is the shortcoming that control precision is low, frequency stability is poor in this class circuit.
Along with the development of microelectric technique, Direct Digital frequency synthesis (Direct Digital Synthesis, DDS) technology is more and more extensive in the application in frequency synthesis field.DDS is a kind of frequency synthesis technique from the directly synthetic required waveform of phase place concept.Signal generator based on the DDS technology has the plurality of advantages such as relative bandwidth is wide, frequency switching time is short, frequency resolution is high, output phase is continuous, can produce the more modulation signal, control is flexible.Some advantages of DDS technology are apparent, so it is a kind of very desirable solution of present swept signal generator.
A kind of swept signal generator based on the DDS technology is arranged in prior art, and this swept signal generator adopts programmable logic array (FPGA) as core component, adopts the DDS technology to produce swept-frequency signal.FPGA realizes principle as shown in Figure 1, and DDS mainly is divided into two-way: the one tunnel produces swept-frequency signal medium frequency incremental portion; One the tunnel produces swept-frequency signal medium frequency base unit weight part.
The production process of swept-frequency signal medium frequency incremental portion: having realized that a frequency sweep frequency word RAM reads address generator, is exactly in fact an accumulator.Constantly read the address of depositing frequency sweep frequency word RAM with cumulative generation of certain speed.Carry out necessary parameter adjustment after reading.Carry out afterwards phase-accumulated; The namely swept-frequency signal frequency base unit weight addition of data that cumulative resulting value arrives with an other rood again, obtain and be exactly the address of reading and saving carrier wave wave table ROM.Swept-frequency signal medium frequency base unit weight part just just constantly adds up the initial frequency word.The two paths of data addition obtains reading the address of carrier wave wave table, reads final frequency sweep range value from the RAM that preserves the carrier wave wave table.
These range values pass through the conversion of digital to analog converter (DAC) again, just obtain the swept-frequency signal of analog quantity.
The FPGA internal structure of above-mentioned swept-frequency signal generator is unreasonable, and the frequency sweep function that realizes also is weak:
At first, before frequency sweep begins, need software to calculate needed each frequency sweep frequency word in the frequency sweep process, then it all is written to the RAM that deposits the frequency sweep frequency word.So not only increase the burden of software, and can reduce system response time.
Secondly, used two each and every one accumulators respectively to frequency word base unit weight and increment accumulation.Accumulator not only consumes the FPGA internal resource, and reduces the timing performance of FPGA.Especially for the application of those parallel DDS structures that adopt for the bandwidth that improves the output swept-frequency signal, the fault of construction of this pair of accumulator can be more obvious.
Again, the swept-frequency signal of realization is too simple, is not enough to deal with practical measurement requirement.Can only scan the termination frequency from initial frequency, not stop the maintenance function of frequency, can not be from stopping the frequency flyback to initial frequency.
At last, as swept signal generator, lack frequency marker function at least.
Summary of the invention
The purpose of the embodiment of the present invention is to provide a kind of swept signal generator, to overcome all deficiencies of prior art scheme.
For achieving the above object, the invention provides a kind of swept signal generator, this swept signal generator comprises processor, memory, Subscriber Interface Module SIM, clock circuit, D/A converter module, analog module and fpga chip, it is characterized in that, this fpga chip comprises:
Communication interface modules is connected with described processor, is used for the instruction of receiving processor;
Clock module is connected with described clock circuit, is used for providing work clock;
The frequency sweep state machine is used for providing different frequency sweep states;
The frequency sweep time totalizer is connected with described frequency sweep state machine, and for the marking signal of completing to described frequency sweep state machine feedback time, and address output is read in generation;
The frequency sweep profile memory is connected with described frequency sweep state machine, is used for storing the frequency sweep curve that described frequency sweep state machine is determined, and reads frequency sweep curve sampling point according to the address of reading that described frequency sweep accumulator produces;
The skew multiplier is connected with described frequency sweep profile memory, obtains the incremental portion of frequency sweep frequency word by calculating;
The frequency word adder is connected with described skew multiplier, is used for the increment of frequency word and the frequency word of frequency word base quantity addition acquisition carrier wave;
Phase accumulator is connected with described frequency word adder, is used for the frequency word of described carrier wave is added up, and accumulation result is exported;
The carrier wave memory receives the Output rusults of described phase accumulator as reading the address, is used for the sampling point of the shape one-period of storage carrier wave;
The frequency marker comparator is for generation of the frequency marker signal.
Described frequency sweep state machine provides four kinds of state swept-frequency signals, comprising:
Initial hold mode is with the initial frequency output signal;
Scanning mode, the frequency of output signal changes to the termination frequency from initial frequency;
Stop hold mode, to stop the frequency output signal;
The flyback state, the frequency of output signal is from stopping frequency change to initial frequency.
Described skew multiplier provides frequency sweep offset coefficient and frequency sweep curve sampling point product, thereby obtains the incremental portion of frequency sweep frequency word.
Described frequency marker comparator obtains the mark frequency address threshold by user's setting that described processor transmits, and compares with the address of reading of described frequency sweep time totalizer output, when both equating, produces a marking signal as the frequency marker signal.
A kind of swept-frequency signal generator that the embodiment of the present invention provides adopts FPGA to produce swept-frequency signal as core component, and implementation is more reasonable, and the software burden is little, response is fast, and the resource that consumes FPGA is few; Simultaneously, increase the function that some meet market demand, frequency sweep mode is horn of plenty more.
Description of drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, consists of the application's a part, does not consist of limitation of the invention.In the accompanying drawings:
Fig. 1 is a kind of FPGA internal structure of prior art block diagram;
Fig. 2 is the structured flowchart of a kind of swept signal generator of the present invention;
Fig. 3 is the FPGA inner function module schematic diagram of a kind of swept signal generator of the present invention;
Fig. 4 is the frequency marker signal generating circuit figure of a kind of swept signal generator of the present invention;
Fig. 5 is 4 view of the linear frequency sweep of a kind of swept signal generator of the present invention;
Fig. 6 is the redirect schematic flow sheet of frequency sweep state machine in a kind of swept signal generator of the present invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the present invention is clearer, below in conjunction with embodiment and accompanying drawing, the embodiment of the present invention is described in further details.At this, illustrative examples of the present invention and explanation thereof are used for explanation the present invention, but not as a limitation of the invention.
Embodiment one
A kind of swept signal generator of the present invention adopts FPGA to add the structure of processor, and FPGA produces swept-frequency signal as core component, the inner function module of this signal generator as shown in Figure 2, Fig. 2 is the structural principle block diagram of a kind of swept signal generator of the present invention.
In Fig. 2, a kind of swept signal generator of the present invention comprises processor 201, memory 203, Subscriber Interface Module SIM 202, clock circuit 204, D/A converter module 606, analog module 207 and fpga chip 205, wherein:
Subscriber Interface Module SIM 202 comprises keyboard, demonstration and control port, such as GPIB, LAN, USB etc.
Flash memory 203 is used for the sampling point of storage carrier waveform sampling point and frequency sweep curve.
Fpga chip 205 is exported swept-frequency signal 212 and the frequency marker signal 211 of digital form according to the setting of processor 201.
Digital to analog converter DAC module 206 is converted to analog quantity 213 with digital signal 212.
Frequency sweep state machine 302 is used for providing different frequency sweep states;
Frequency sweep state machine 302 of the present invention provides one of four states output swept-frequency signal, is respectively:
Initial hold mode is with the initial frequency output signal;
Scanning mode, the frequency of output signal changes to the termination frequency from initial frequency;
Stop hold mode, to stop the frequency output signal;
The flyback state, the frequency of output signal is from stopping frequency change to initial frequency.
Take linear frequency sweep as example, Fig. 4 has illustrated the frequency change process of this one of four states.The duration of this one of four states can arrange respectively; Even can directly skip, for example only open " scanning " state, other three states are all closed.Therefore, before the output swept-frequency signal, processor need to arrange the opening and closing of this one of four states, and the corresponding time control word 311 of each state duration.
In frequency sweep state machine 302, the redirect flow process of this one of four states as shown in Figure 5.After the beginning frequency sweep, judge first whether this state is opened, if not unlatching, leap to NextState; If open, after the duration of waiting until this state completed, the frequency sweep time totalizer can feed back a marking signal 322, and frequency sweep state machine 302 is jumped into NextState after receiving this marking signal.
Frequency sweep state machine 302 selects time control word 323 corresponding to each state to give frequency sweep time totalizer 303 according to the redirect situation.
Frequency sweep time totalizer 303 is connected with described frequency sweep state machine 302, is used for the marking signal completed to described frequency sweep state machine 302 feedback times, and produces and read address 324 and export to frequency sweep profile memory 325.
Under each state, frequency sweep state machine 302 is given frequency sweep time totalizer 303 with the corresponding time control word of one of four states respectively, frequency sweep time totalizer 303 adds up with the time control word, accumulator overflows the duration that this state is described to be completed, and a marking signal is fed back to frequency sweep state machine 302.
The swept-frequency signal that the present invention realizes has one of four states, so the accumulated value of frequency sweep time totalizer can not directly give frequency sweep profile memory 303 as reading the address, but is handled as follows respectively under each state:
Initial hold mode: read the address and remain 0, read all the time first point under this state from frequency sweep profile memory 304;
Scanning mode: give frequency sweep profile memory 303 with accumulated value;
Stop hold mode: read the address and remain maximum, read all the time last point under this state from frequency sweep profile memory 304;
The flyback state: will give frequency sweep profile memory 304 after the accumulated value negate, meaning is namely from last some beginning value, until first point.
Frequency sweep profile memory 304 is connected with described frequency sweep state machine 302, is used for storing the frequency sweep curve that described frequency sweep state machine 302 is determined, and reads frequency sweep curve sampling point according to the address of reading that described frequency sweep accumulator 303 produces; The work of described frequency sweep profile memory 304 is after having determined sweep method, and before swept-frequency signal began output, processor was written to the frequency sweep curve 312 of the correspondence of sweep method in frequency sweep profile memory 304; After frequency sweep begins, take out frequency sweep curve sampling point 325 according to the address of reading that frequency sweep time totalizer 303 provides.
Frequency marker is that the frequency in sweep measurement is spent surely, namely exports a marking signal when locating to " mark frequency " that the user arranges when the frequency change of swept-frequency signal.The basic skills that produces the frequency marker signal is beat method, and its principle schematic as shown in Figure 6.It uses a standard signal generator to produce frequency is the signal of " mark frequency ", and the signal of this signal and swept signal generator output carries out mixing, then through narrow-band filtering and vertical amplification, thereby produce marking signal.The shortcoming of beat method is apparent, and not only circuit is complicated, cost is high, and due to the nonlinear distortion of analogue device cause the stability of frequency marker signal and accuracy all relatively poor, surely spend error because circuit delay can cause frequency simultaneously.
The corresponding output frequency of each sampling point of frequency sweep curve can calculate according to formula 1,2.
Frequency=master clock 321 frequencies of swept-frequency signal 333 * frequency word 327/2
K(formula 1)
The frequency sweep curve is write by processor, and the address at each sampling point place is also known to processor.Therefore, corresponding address threshold 316 configurations of mark frequency that processor arranges the user are to FPGA, the output of frequency marker comparator comparison frequency sweep time totalizer read address 324 and address threshold 316, when both equating, produce a marking signal, be the frequency marker signal.
The swept signal generator of realizing according to the present invention has following advantage:
Frequency sweep mode is horn of plenty more, and scan function is not only arranged, and also support initial maintenance, stop maintenance, flyback, and the time of this one of four states can be distinguished setting flexibly;
The fpga chip reasonable in internal structure is used the skew multiplier, need not software and expends plenty of time calculating frequency sweep frequency word, thereby alleviated the burden of software, has also accelerated system response time;
Compare with existing, only use an accumulator, not only reduced the resource occupation to FPGA, and be conducive to the raising of FPGA timing performance, also be conducive to expand to parallel DDS structure;
The generation circuit of frequency marker signal only needs a comparator, and is very simple; Owing to adopting digital methods, effect is very good, and not only frequency stability and accuracy are high, and there is no circuit delay, and also just not having frequency spends error surely; In addition, only need to increase the number of comparator, the present invention just is easy to increase the number of frequency marker signal, and because the FPGA resource is very abundant at present, the spent cost of the increase on this frequency marker signal number almost can be ignored;
Adopt FPGA to produce swept-frequency signal on the DDS technical foundation, therefore very natural the having plurality of advantages such as relative bandwidth is wide, frequency switching time is short, frequency resolution is high, control is flexible, the upgrading debugging is convenient.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above is only specific embodiments of the invention; the protection range that is not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (4)
1. swept signal generator, this swept signal generator comprises processor, memory, Subscriber Interface Module SIM, clock circuit, D/A converter module, analog module and fpga chip, it is characterized in that, this fpga chip comprises:
Communication interface modules is connected with described processor, is used for the instruction of receiving processor;
Clock module is connected with described clock circuit, is used for providing work clock;
The frequency sweep state machine is used for providing different frequency sweep states;
The frequency sweep time totalizer is connected with described frequency sweep state machine, and for the marking signal of completing to described frequency sweep state machine feedback time, and address output is read in generation;
The frequency sweep profile memory is connected with described frequency sweep state machine, is used for storing the frequency sweep curve that described frequency sweep state machine is determined, and reads frequency sweep curve sampling point according to the address of reading that described frequency sweep accumulator produces;
The skew multiplier is connected with described frequency sweep profile memory, obtains the incremental portion of frequency sweep frequency word by calculating;
The frequency word adder is connected with described skew multiplier, is used for the increment of frequency word and the frequency word of frequency word base quantity addition acquisition carrier wave;
Phase accumulator is connected with described frequency word adder, is used for the frequency word of described carrier wave is added up, and accumulation result is exported;
The carrier wave memory receives the Output rusults of described phase accumulator as reading the address, is used for the sampling point of the shape one-period of storage carrier wave;
The frequency marker comparator is for generation of the frequency marker signal.
2. swept signal generator according to claim 1, is characterized in that, described frequency sweep state machine provides four kinds of state swept-frequency signals, comprising:
Initial hold mode is with the initial frequency output signal;
Scanning mode, the frequency of output signal changes to the termination frequency from initial frequency;
Stop hold mode, to stop the frequency output signal;
The flyback state, the frequency of output signal is from stopping frequency change to initial frequency.
3. swept signal generator according to claim 1 is characterized in that:
Described skew multiplier provides frequency sweep offset coefficient and frequency sweep curve sampling point product, thereby obtains the incremental portion of frequency sweep frequency word.
4. swept signal generator according to claim 1 is characterized in that:
Described frequency marker comparator obtains the mark frequency address threshold by user's setting that described processor transmits, and compares with the address of reading of described frequency sweep time totalizer output, when both equating, produces a marking signal as the frequency marker signal.
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Cited By (7)
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| CN104734639A (en) * | 2015-04-08 | 2015-06-24 | 中国科学院光电技术研究所 | Three-section addressing high-precision DDS swept signal generator |
| CN104935258A (en) * | 2014-03-18 | 2015-09-23 | 苏州普源精电科技有限公司 | Sweep signal generator capable of generating a plurality of frequency markers |
| CN105577121A (en) * | 2014-10-14 | 2016-05-11 | 苏州普源精电科技有限公司 | Band-segmented frequency sweeping device and signal generator having band-segmented frequency sweeping function |
| CN107231151A (en) * | 2017-05-24 | 2017-10-03 | 中国电子科技集团公司第四十研究所 | A kind of broadband Sweep Source design circuit and design method |
| CN107450417A (en) * | 2017-09-21 | 2017-12-08 | 广东电网有限责任公司电力科学研究院 | A kind of nonlinear properties method for generation and nonlinear properties generator |
| CN108761363A (en) * | 2018-05-31 | 2018-11-06 | 上海东软医疗科技有限公司 | Swept-frequency signal output method and device |
| CN108983069A (en) * | 2018-05-28 | 2018-12-11 | 北京比特大陆科技有限公司 | chip scanning system and method |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104935258A (en) * | 2014-03-18 | 2015-09-23 | 苏州普源精电科技有限公司 | Sweep signal generator capable of generating a plurality of frequency markers |
| CN104935258B (en) * | 2014-03-18 | 2019-08-13 | 苏州普源精电科技有限公司 | A kind of swept signal generator can produce multiple frequency markings |
| CN105577121A (en) * | 2014-10-14 | 2016-05-11 | 苏州普源精电科技有限公司 | Band-segmented frequency sweeping device and signal generator having band-segmented frequency sweeping function |
| CN104734639A (en) * | 2015-04-08 | 2015-06-24 | 中国科学院光电技术研究所 | Three-section addressing high-precision DDS swept signal generator |
| CN107231151A (en) * | 2017-05-24 | 2017-10-03 | 中国电子科技集团公司第四十研究所 | A kind of broadband Sweep Source design circuit and design method |
| CN107231151B (en) * | 2017-05-24 | 2020-10-09 | 中国电子科技集团公司第四十一研究所 | Broadband frequency sweeping source design circuit and design method |
| CN107450417A (en) * | 2017-09-21 | 2017-12-08 | 广东电网有限责任公司电力科学研究院 | A kind of nonlinear properties method for generation and nonlinear properties generator |
| CN107450417B (en) * | 2017-09-21 | 2023-04-25 | 广东电网有限责任公司电力科学研究院 | Nonlinear signal generation method and nonlinear signal generator |
| CN108983069A (en) * | 2018-05-28 | 2018-12-11 | 北京比特大陆科技有限公司 | chip scanning system and method |
| CN108761363A (en) * | 2018-05-31 | 2018-11-06 | 上海东软医疗科技有限公司 | Swept-frequency signal output method and device |
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