CN107450417B - Nonlinear signal generation method and nonlinear signal generator - Google Patents
Nonlinear signal generation method and nonlinear signal generator Download PDFInfo
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- CN107450417B CN107450417B CN201710861827.5A CN201710861827A CN107450417B CN 107450417 B CN107450417 B CN 107450417B CN 201710861827 A CN201710861827 A CN 201710861827A CN 107450417 B CN107450417 B CN 107450417B
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Abstract
The embodiment of the invention discloses a nonlinear signal generation method and a nonlinear signal generator, wherein an FPGA chip in the generator receives configuration data sent by an external controller, performs data conversion on the data through a communication controller in the FPGA to obtain various control information, and respectively sends the control information to an address module, a multiplier and a data selection module in the FPGA, the address module reads data from a read-only memory (ROM) according to the control information, outputs the data to the multiplier, the multiplier finishes processing and sends the data to the data selection module, the data is processed by the data selection module and then is output to the outside of the FPGA, the outside of the FPGA generates an analog signal through a DA chip, and the analog signal outputs a required signal after passing through a low-pass filter.
Description
Technical Field
The invention relates to the field of high-power controllable current sources and voltage source equipment, in particular to a nonlinear signal generation method and a nonlinear signal generator.
Background
In scientific research, engineering education and production practice, such as industrial process control, teaching experiments, mechanical vibration experiments, dynamic analysis, material experiments, biomedicine, etc., low frequency signal generators are often required. The function generator is used as a universal electronic instrument and is widely applied to the fields of production, scientific research, measurement and control, communication and the like. However, such instruments in the market cannot meet the requirements of practical application in many aspects, such as frequency accuracy, bandwidth, waveform types and program control.
The signal generator used for a long time at present is mostly composed of analog circuits, the frequency of the instrument can reach hundreds of MHz as a signal source, and the instrument has high frequency stability and good adjustability in a high-frequency range. But when used for low-frequency signal output, the RC value required by the low-frequency signal output is large, and the accuracy of parameters is difficult to ensure. And the volume and the loss are large, and the manufacturing cost is extremely high. Most importantly, the frequency of the power source demand in the power industry is relatively low, typically below 1MHz, and it is apparent that the power source used in the power industry by the signal source is not satisfactory.
Therefore, it is a technical problem that needs to be solved by those skilled in the art to provide a nonlinear signal generating method and a nonlinear signal generator that have excellent performance in a low frequency band, low power consumption, and small volume.
Disclosure of Invention
The embodiment of the invention provides a nonlinear signal generation method and a nonlinear signal generator, which have the advantages of excellent performance, low power consumption, small volume and the like in a low frequency band.
The embodiment of the invention provides a nonlinear signal generation method, which comprises the following steps:
s1: after receiving the configuration data, converting the configuration data through an FPGA chip to obtain a control data frame;
S2: analyzing the control data frame through the FPGA chip to obtain control information, wherein the control information comprises: start character, control character, output signal frequency control information and data selection control information;
s3: determining an address accumulation amount through the FPGA chip according to the control character and the output signal frequency control information, performing address selection according to the address accumulation amount to obtain first address selection information and second address selection information, and performing data selection through the FPGA chip according to the first address selection information and the second address selection information to obtain first data and second data;
s4: adding or selecting the first data and the second data according to the data selection control information through the FPGA chip to obtain a nonlinear digital signal;
s5: and performing digital-to-analog conversion on the nonlinear digital signal to obtain a nonlinear analog signal, and performing filtering operation on the nonlinear digital signal through a low-pass filter to obtain a filtered nonlinear signal.
Preferably, the control information includes: a start character of two bytes, a control character of one byte, output signal frequency control information of four bytes, output signal amplitude control information of two bytes, and data selection control information of one byte;
The output signal frequency control information comprises four byte values, wherein the first byte value is a first value, the second byte value is a second value, the third byte value is a third value, and the fourth byte value is a fourth value.
Preferably, step S4 is preceded by:
amplifying or shrinking the first data and the second data according to the output signal amplitude control information through the FPGA chip to obtain processed first data and processed second data;
s4: and adding or selecting the processed first data and the processed second data through the FPGA chip according to the data selection control information to obtain a nonlinear digital signal.
Preferably, step S3 specifically includes:
s31: judging the type of the control character through the FPGA chip, if the control character is the first control character, executing S32, and if the control character is the second control character, executing S33;
s32: determining that the address accumulation amount is one through the FPGA chip, adding one to the first address after every first numerical clock pulse according to the output signal frequency control information, continuing the second numerical time in a period until the first address selection information is obtained, adding one to the second address after every third numerical clock pulse, and continuing the fourth numerical time in a period until the second address selection information is obtained;
S33: determining that the address accumulation amount is a first value according to the output signal frequency control information through the FPGA chip, adding the first value to the first address after every other clock pulse, continuing the second value for a time within one period until the first address selection information is obtained, adding the third value to the second address after every other clock pulse, and continuing the fourth value for a time within one period until the second address selection information is obtained;
s34: and carrying out data selection according to the first address selection information and the second address selection information through the FPGA chip to obtain first data and second data.
Preferably, the address selection range of the FPGA chip is 0 to 4095.
Preferably, the embodiment of the present invention further provides a nonlinear signal generator, including: the device comprises a communication module, an FPGA chip, a digital-to-analog conversion module and a low-pass filter;
wherein, the FPGA chip includes: the system comprises a communication controller, a data analysis module, a first address module, a second address module, a first memory, a second memory and a data selection module;
the communication controller is connected with the communication module and is used for receiving the configuration data sent by the communication module and converting the configuration data to obtain a control data frame;
The data analysis module is connected with the communication controller and is used for analyzing the control data frame to obtain control information, wherein the control information comprises: start character, control character, output signal frequency control information and data selection control information;
the data analysis module, the first address module and the first memory are connected in sequence, the first address module is used for determining an address accumulation amount according to control characters and output signal frequency control information, address selection is carried out according to the address accumulation amount to obtain first address selection information, and the first memory is used for outputting first data according to the first address selection information;
the data analysis module, the second address module and the second memory are connected in sequence, the second address module is used for determining an address accumulation amount according to control characters and output signal frequency control information, address selection is carried out according to the address accumulation amount to obtain second address selection information, and the second memory is used for outputting second data according to the second address selection information;
the data selection module is connected with the data analysis module and is used for adding or selecting the first data and the second data according to the data selection control information to obtain a nonlinear digital signal;
The data selection module is connected with the digital-to-analog conversion module, and the digital-to-analog conversion module is used for converting the nonlinear digital signals to obtain nonlinear analog signals;
the low-pass filter is used for carrying out filtering operation on the nonlinear digital signal to obtain a filtered nonlinear signal.
Preferably, the control information includes: a start character of two bytes, a control character of one byte, output signal frequency control information of four bytes, output signal amplitude control information of two bytes, and data selection control information of one byte;
the output signal frequency control information comprises four byte values, wherein the first byte value is a first value, the second byte value is a second value, the third byte value is a third value, and the fourth byte value is a fourth value.
Preferably, the nonlinear signal generator further provided in the embodiment of the present invention further includes: a first multiplier and a second multiplier;
the data analysis module, the first address module, the first memory and the first multiplier are sequentially connected, the first multiplier is connected with the data analysis module and is used for processing the first signal according to the control information to obtain processed first data;
The data analysis module, the second address module, the second memory and the second multiplier are sequentially connected, the second multiplier is connected with the data analysis module, and the second multiplier is used for processing the second signal according to the control information to obtain processed second data;
the data selection module is connected with the data analysis module and is used for adding or selecting the processed first data and the processed second data according to the control information to obtain a nonlinear digital signal.
Preferably, the nonlinear signal generator provided by the embodiment of the present invention further includes: a clock module;
the clock module is connected with the communication controller and is used for providing clock pulses;
the first address module is further used for determining that the address accumulation amount is one after judging that the type of the control character is a first control character, adding one to the first address after every first numerical clock pulse according to the output signal frequency control information, and continuing the second numerical time in a period until first address selection information is obtained;
the second address module is further configured to determine that the address accumulation amount is one after determining that the type of the control character is the first control character, increase the second address by one after every third numerical clock pulse according to the output signal frequency control information, and continue the fourth numerical value for a period until second address selection information is obtained;
The first address module is further used for determining that the address accumulation amount is a first value according to the output signal frequency control information after judging the type of the control character is a second control character, adding the first value to the first address after every other clock pulse, and continuing the second value for a plurality of times in a period until first address selection information is obtained;
the second address module is further configured to determine, according to the output signal frequency control information, that the address accumulation amount is a first value after determining that the type of the control character is the second control character, add a third value to the second address after every other clock pulse, and continue the fourth value for a period until second address selection information is obtained;
the first memory is used for outputting first data according to the first address selection information;
the second memory is used for outputting second data according to the second address selection information.
Preferably, the address selection range of the FPGA chip is 0 to 4095.
From the above technical solutions, the embodiment of the present invention has the following advantages:
the embodiment of the invention provides a nonlinear signal generation method and a nonlinear signal generator, wherein the nonlinear signal generation method comprises the following steps: s1: after receiving the configuration data, converting the configuration data through an FPGA chip to obtain a control data frame; s2: analyzing the control data frame through the FPGA chip to obtain control information, wherein the control information comprises: start character, control character, output signal frequency control information and data selection control information; s3: determining an address accumulation amount through the FPGA chip according to the control character and the output signal frequency control information, performing address selection according to the address accumulation amount to obtain first address selection information and second address selection information, and performing data selection through the FPGA chip according to the first address selection information and the second address selection information to obtain first data and second data; s4: adding or selecting the first data and the second data according to the data selection control information through the FPGA chip to obtain a nonlinear digital signal; s5: and performing digital-to-analog conversion on the nonlinear digital signal to obtain a nonlinear analog signal, and performing filtering operation on the nonlinear digital signal through a low-pass filter to obtain a filtered nonlinear signal. The nonlinear signal generating method and the nonlinear signal generator provided by the embodiment of the invention can quickly and accurately generate various signal waveforms, and simultaneously can quickly change the logic structure and increase the number of output channels by utilizing the FPGA design. All logic codes have high universality, can be compatible with FPGA chips of all factories such as Altera (Intel), xilinx and Actel, and have high portability, and a plurality of modules are reusable.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a schematic flow chart of an embodiment of a nonlinear signal generating method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of another embodiment of a nonlinear signal generating method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an embodiment of a nonlinear signal generator according to an embodiment of the present invention;
FIG. 4 is an application schematic diagram of a nonlinear signal generator;
fig. 5 is an application illustration of an FPGA chip.
Detailed Description
The embodiment of the invention provides a nonlinear signal generation method and a nonlinear signal generator, which have the advantages of excellent performance, low power consumption, small volume and the like in a low frequency band.
In order to make the objects, features and advantages of the present invention more comprehensible, the technical solutions in the embodiments of the present invention are described in detail below with reference to the accompanying drawings, and it is apparent that the embodiments described below are only some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, an embodiment of a nonlinear signal generating method according to an embodiment of the present invention includes:
101. after receiving the configuration data, converting the configuration data through an FPGA chip to obtain a control data frame;
102. analyzing the control data frame through the FPGA chip to obtain control information, wherein the control information comprises: start character, control character, output signal frequency control information and data selection control information;
103. determining an address accumulation amount through the FPGA chip according to the control character and the output signal frequency control information, performing address selection according to the address accumulation amount to obtain first address selection information and second address selection information, and performing data selection through the FPGA chip according to the first address selection information and the second address selection information to obtain first data and second data;
104. adding or selecting the first data and the second data according to the data selection control information through the FPGA chip to obtain a nonlinear digital signal;
105. and performing digital-to-analog conversion on the nonlinear digital signal to obtain a nonlinear analog signal, and performing filtering operation on the nonlinear digital signal through a low-pass filter to obtain a filtered nonlinear signal.
The FPGA chip in the embodiment of the invention receives the configuration data sent by the external controller, performs data conversion on the data through the communication controller in the FPGA to obtain various control information, respectively sends the control information to the address module, the multiplier and the data selection module in the FPGA, the address module reads the data from the read-only memory (ROM) according to the control information control, outputs the data to the multiplier, the multiplier finishes processing and sends the data to the data selection module, the data selection module processes the data and outputs the data to the outside of the FPGA, the outside of the FPGA generates analog signals through the DA chip, and the analog signals output required signals after passing through the low-pass filter. The embodiment of the invention can realize the self-defined nonlinear signal output, and comprises periodic signals: sine waves, triangular waves, square waves, periodic pulses, and various non-periodic signals.
The foregoing is an embodiment of a nonlinear signal generating method, and for more specific description, another embodiment of a nonlinear signal generating method is provided below, referring to fig. 2, and another embodiment of a nonlinear signal generating method provided in the present invention includes:
201. after receiving the configuration data, converting the configuration data through an FPGA chip to obtain a control data frame;
202. Analyzing the control data frame through the FPGA chip to obtain control information, wherein the control information comprises: start character, control character, output signal frequency control information and data selection control information;
in this embodiment, the control information includes: a start character of two bytes, a control character of one byte, output signal frequency control information of four bytes, output signal amplitude control information of two bytes, and data selection control information of one byte.
The output signal frequency control information comprises four byte values, wherein the first byte value is a first value, the second byte value is a second value, the third byte value is a third value, and the fourth byte value is a fourth value.
203. Judging the type of the control character through the FPGA chip, executing 204 if the control character is a first control character, and executing 205 if the control character is a second control character;
204. determining that the address accumulation amount is one through the FPGA chip, adding one to the first address after every first numerical clock pulse according to the output signal frequency control information, continuing the second numerical time in a period until the first address selection information is obtained, adding one to the second address after every third numerical clock pulse, and continuing the fourth numerical time in a period until the second address selection information is obtained;
205. Determining that the address accumulation amount is a first value according to the output signal frequency control information through the FPGA chip, adding the first value to the first address after every other clock pulse, continuing the second value for a time within one period until the first address selection information is obtained, adding the third value to the second address after every other clock pulse, and continuing the fourth value for a time within one period until the second address selection information is obtained;
206. performing data selection according to the first address selection information and the second address selection information through the FPGA chip to obtain first data and second data;
207. amplifying or shrinking the first data and the second data according to the output signal amplitude control information through the FPGA chip to obtain processed first data and processed second data;
208. adding or selecting the processed first data and the processed second data according to the data selection control information through the FPGA chip to obtain a nonlinear digital signal;
209. and performing digital-to-analog conversion on the nonlinear digital signal to obtain a nonlinear analog signal, and performing filtering operation on the nonlinear digital signal through a low-pass filter to obtain a filtered nonlinear signal.
In this embodiment, the internal design of the FPGA chip includes a communication controller, a data analysis module, a two-way address module, a two-way rom, a two-way multiplier, and a data selection module. The address selection range of the FPGA chip is 0 to 4095.
The communication controller of the FPGA chip receives configuration data output by an external PC or CPU according to bytes, then judges whether the received data is valid or not, and transmits the valid data to the data analysis module, and the data analysis module analyzes a data frame to obtain: a start character of 2 bytes, a control character of 1 byte, output signal frequency control information of 4 bytes, output signal amplitude control information of 2 bytes, and data selection control information of 1 byte. After the data analysis module analyzes the data, the data analysis module sends the information to the address module, the multiplier and the data selection module respectively. After the address module obtains the control character, it first judges whether all addresses need to be used. If all addresses need to be used, judging that data are read every few clock rising edges according to the output signal frequency control information, and meanwhile, the number of the clock rising edges is also changed to a certain extent, wherein one group of instructions only comprise two groups of clock rising edge counts, the groups of counts are obtained through early calculation in the external data transmission process, the FPGA chip is not needed to calculate, a non-integer clock rising edge counting mode is realized at the moment, and the output signal is a statistical value and is not an accurate value, and the error of the signal is negligible due to the fact that the digital circuit determines the number of the clock rising edges. Similarly, if not all addresses need to be obtained, the accumulated amount of each address needs to be obtained by analyzing the output signal frequency control information, and the accumulated amount may be a non-integer accumulated amount, which is the same as the previous accumulated amount, and is determined in the same manner. The two paths of data from different ROM are output to the multiplier, the data is correspondingly amplified (or reduced) according to the amplitude information multiplier, the two groups of data are added after being amplified and reduced in a certain proportion, one group of data or two groups of data or output direct current signals are selected and output according to data selection and control information, continuous waveforms are obtained after the output signals are subjected to DA conversion, and the required signals are obtained through the low-pass filter.
Referring to fig. 3, an embodiment of a nonlinear signal generator according to an embodiment of the present invention includes:
the device comprises a communication module 301, an FPGA chip 302, a digital-to-analog conversion module 303 and a low-pass filter 304;
wherein, FPGA chip 302 includes: a communication controller 3021, a data analysis module 3022, a first address module 3023, a second address module 3024, a first memory 3025, a second memory 3026, and a data selection module 3029;
the communication controller 3021 is connected to the communication module 301, and the communication controller 3021 is configured to receive configuration data sent by the communication module, and convert the configuration data to obtain a control data frame;
the data analysis module 3022 is connected to the communication controller 3021, and the data analysis module 3022 is configured to parse a control data frame to obtain control information, where the control information includes: start character, control character, output signal frequency control information and data selection control information;
the data analysis module 3022, the first address module 3023 and the first memory 3025 are connected in sequence, the first address module 3023 is used for determining an address accumulation amount according to control characters and output signal frequency control information, address selection is performed according to the address accumulation amount to obtain first address selection information, and the first memory 3025 is used for outputting first data according to the first address selection information;
The data analysis module 3022, the second address module 3024 and the second memory 3026 are connected in sequence, the second address module 3024 is used for determining an address accumulation amount according to control characters and output signal frequency control information, address selection is performed according to the address accumulation amount to obtain second address selection information, and the second memory 3026 is used for outputting second data according to the second address selection information;
the data selecting module 3029 is connected to the data analyzing module 3022, and the data selecting module 3029 is configured to add or select the first data and the second data according to the data selecting control information to obtain a nonlinear digital signal;
the data selecting module 3029 is connected to the digital-to-analog conversion module 303, and the digital-to-analog conversion module 303 is configured to convert the nonlinear digital signal to obtain a nonlinear analog signal;
the low-pass filter 304 and the digital-to-analog conversion module 303, the low-pass filter 304 is used for filtering the nonlinear digital signal to obtain a filtered nonlinear signal.
Further, the control information includes: a start character of two bytes, a control character of one byte, output signal frequency control information of four bytes, output signal amplitude control information of two bytes, and data selection control information of one byte;
The output signal frequency control information comprises four byte values, wherein the first byte value is a first value, the second byte value is a second value, the third byte value is a third value, and the fourth byte value is a fourth value.
Further, the embodiment of the present invention also provides a nonlinear signal generator, which further includes: a first multiplier 3027 and a second multiplier 3028;
the data analysis module 3022, the first address module 3023, the first memory 3025 and the first multiplier 3027 are connected in sequence, the first multiplier 3027 is connected with the data analysis module 3029, and the first multiplier 3027 is used for processing the first signal according to the control information to obtain processed first data;
the data analysis module 3022, the second address module 3024, the second memory 3026 and the second multiplier 3028 are sequentially connected, the second multiplier 3028 is connected to the data analysis module 3029, and the second multiplier 3028 is configured to process the second signal according to the control information to obtain processed second data;
the data selecting module 3029 is connected to the data analyzing module 3022, and the data selecting module 3029 is configured to add or select the processed first data and the processed second data according to the control information to obtain the nonlinear digital signal.
Further, the nonlinear signal generator further includes: a clock module 3020;
the clock module 3020 is connected to the communication controller 3021, and the clock module 3020 is used for providing clock pulses;
the first address module 3023 is further configured to determine that the address accumulation amount is one after determining that the type of the control character is the first control character, increase the first address by one after every first number of clock pulses according to the output signal frequency control information, and continue the second number of times in a period until the first address selection information is obtained;
the second address module 3024 is further configured to determine that the address accumulation amount is one after determining that the type of the control character is the first control character, increase the second address by one after every third numerical clock according to the output signal frequency control information, and continue the fourth numerical time in a period until the second address selection information is obtained;
the first address module 3023 is further configured to determine, according to the output signal frequency control information, that the address accumulation amount is a first value after determining that the type of the control character is a second control character, increase the first value to the first address after every other clock pulse, and continue the second value for a period until the first address selection information is obtained;
The second address module 324 is further configured to determine, according to the output signal frequency control information, that the address accumulation amount is a first value after determining that the type of the control character is a second control character, add a third value to the second address after every other clock pulse, and continue the fourth value for a period until second address selection information is obtained;
the first memory 3025 is configured to output first data according to the first address selection information;
the second memory 3026 is configured to output second data according to the second address selection information.
Further, the address selection range of the FPGA chip is 0 to 4095.
The above is a detailed description of the structure and connection manner of a nonlinear signal generator, and for convenience of understanding, the following will describe an application of a nonlinear signal generator in a specific application scenario, please refer to fig. 4 and 5, and an application example includes: communication module, FPGA chip, DA chip, filter, etc.; the FPGA chip internal design comprises a communication controller, a data analysis module, a two-way address module, a two-way read-only memory, a two-way multiplier and a data selection module. The FPGA receives configuration data sent by an external controller through a communication module interface, the communication controller performs data conversion on the data to obtain various control information, the control information is respectively sent to an address module, a multiplier and a data selection module, the address module reads content from a read-only memory (ROM) and outputs the content to the multiplier, the multiplier finishes processing the content to the data selection module, the data selection module outputs the data to the outside of the FPGA, the outside of the FPGA generates analog signals through a DA chip, and the analog signals output required signals after passing through a low-pass filter.
The communication module uses UART serial ports, serial port data comprises 1 bit start bit, 18 bit data bit, 1 bit check bit and 1 bit stop bit, the communication module is not limited to UART serial ports, and SPI, USB, CAN bus interfaces, network ports, wiFi and the like CAN be used.
The output of the address module is controlled, the count value of the address module is 0 to 4095, the internal register uses 12 bits, the internal register can automatically count again when the count value exceeds 4095 according to the characteristics of the FPGA, the address module judges the external condition when each clock arrives, the count value is increased by a larger value when the data time requiring higher frequency is increased by 1 to 2048 according to the need, the count value is kept unchanged in a certain time when the data time requiring lower frequency is increased by 1 to 2048, and the specific situation is given by the communication controller.
The address module actually refers to the address of the data pre-stored in the ROM, that is, the data of the ROM can be read according to the address, the data of the ROM is the pre-stored 12-bit standard cosine wave data, the data in the ROM is extracted according to a certain time interval and the address sequence by the control information sent by the control data frame, thus the second extraction is carried out on the 12-bit standard cosine wave data of 4096 data, and the time interval is X in the control data frame 2 X and clock pulse of FPGA are determined together, extracted data are sent to DA converter through multiplier and data selecting module, and after thatThe filter outputs a nonlinear signal to complete nonlinear signal generation.
And outputting internally stored data by a read-only memory (ROM) module according to the information sent by the address module, wherein the internally stored data of the ROM is a 12-bit standard cosine wave with a complete period, the data stored in the two groups of ROMs are completely consistent, MATLAB software is utilized to calculate and multiply a certain amplitude value, the data is rounded, and the data is stored in the ROM module in the FPGA chip. The ROM internal storage data is not limited to 12bit data, and is mainly determined according to the number of output parallel data bits, and the data coding mode comprises the following steps: offset binary coding, etc. The manner in which the ROM stores data varies from one external DA conversion chip to another.
The information sent to the ROM by the address module is an address, the data in the ROM and the address are in one-to-one correspondence, and the ROM outputs the data of the address according to the address. The count is to change the address, and data of another address is read, that is, data of an address after the ROM output count.
The multiplier module is used for respectively amplifying or reducing two paths of periodic signals according to a certain proportion, and simultaneously only carrying out shift operation on data to reduce the data so as to adapt to the self requirement of the FPGA, amplifying the data within a certain range, ensuring that the data output is not distorted, namely, the maximum value of the data amplification is lower than or equal to the maximum value of the output digital signal, and the same reason is adopted for the data reduction; an output data waveform exceeding this limit may deviate greatly from the desired signal.
The data selecting module mainly comprises the steps of adding two paths of signals and selecting 1 path of data for outputting standard sine or cosine signals by using the data selecting module.
The external DA chip converts the 12bit parallel digital signal into an analog signal, and the signal filters an interference signal higher than 50MHz (clock frequency) through a low-pass filter.
The FPGA chip comprises the following components: the system comprises a PLL clock generator, a communication controller, a data analysis module, a two-way address module, a two-way read-only memory, a two-way multiplier and a data selection module. The PLL clock generator mainly provides stable clocks for all modules at the back, the communication controller needs to communicate with the outside to receive instructions, the data analysis module analyzes data, the speed requirement is relatively low, the requirement of data transmission can be well met by adopting a low-frequency clock below 1MHz, all parts of nonlinear signal generation need to be consistent with the conversion rate of an external DA chip, therefore, the parts are determined by the DA chip, and meanwhile, the clocks of the parts also influence the partial value of the data sent by upper software through a communication port. The clock rate needs to be determined from upper layer software calculations.
The communication controller of the FPGA chip receives configuration data output by an external PC or CPU according to bytes, then judges whether the received data is valid or not, and transmits the valid data to the data analysis module, and the data analysis module analyzes a data frame to obtain: a start character of 2 bytes, a control character of 1 byte, output signal frequency control information of 4 bytes, output signal amplitude control information of 2 bytes, and data selection control information of 1 byte. After the data analysis module analyzes the data, the data analysis module sends the information to the address module, the multiplier and the data selection module respectively. After the address module obtains the control character, it first judges whether all addresses need to be used. If all addresses need to be used, judging that data are read every few clock rising edges according to the output signal frequency control information, and meanwhile, the number of the clock rising edges is also changed to a certain extent, wherein one group of instructions only comprise two groups of clock rising edge counts, the groups of counts are obtained through early calculation in the external data transmission process, the FPGA chip is not needed to calculate, a non-integer clock rising edge counting mode is realized at the moment, and the output signal is a statistical value and is not an accurate value, and the error of the signal is negligible due to the fact that the digital circuit determines the number of the clock rising edges. Similarly, if not all addresses need to be obtained, the accumulated amount of each address needs to be obtained by analyzing the output signal frequency control information, and the accumulated amount may be a non-integer accumulated amount, which is the same as the previous accumulated amount, and is determined in the same manner. The two paths of data from different ROM are output to the multiplier, the data is correspondingly amplified (or reduced) according to the amplitude information multiplier, the two groups of data are added after being amplified and reduced in a certain proportion, one group of data or two groups of data or output direct current signals are selected and output according to data selection and control information, continuous waveforms are obtained after the output signals are subjected to DA conversion, and the required signals are obtained through the low-pass filter.
The control signal input selects MAX232, the MAX232 chip is a single power supply level conversion chip specially designed for an RS-232 standard serial port by Messaging (MAXIM) company, and +5v single power supply is used for supplying power.
The FPGA can adopt a second-generation SmartFusion2FPGA product of Microsemi corporation, which can effectively integrate a flash memory-based FPGA architecture, an ARM Cortex-M3 processor with 166MHz, an advanced security processing accelerator, a DSP module, SRAM, eNVM and a high-performance communication interface required by industry on a single chip.
The DA (digital to analog) chip adopts an AD5340 chip, and the AD5340 is an analog to digital conversion chip with 12-bit parallel input and single voltage output. The price is relatively low. For designs with higher precision requirements, a 16-bit conversion chip can be selected, and meanwhile, the data stored in the ROM inside the FPGA is updated.
The ROM stores cosine waves with data of 1 complete period, the number of the data is 4096, and the data is generated by MATLAB software. Data=4095×sin t/2, where t=2×pi (0:4095)/4096, the Data coding mode is normal binary coding, and the Data value is an integer part. What should be stated here is: the integer part includes: the three modes of tail cutting, rounding and Gaussian rounding are adopted, and the tail cutting and rounding mode is adopted to prevent partial quantity from exceeding the range when binary conversion is carried out.
For FPGA internal programming, the upper layer control data frame format is "FF FF X 1 X X 2 X X 3 X X 4 X X 5 X X 6 X X 7 X ", the specific protocol is as follows:
TABLE 1
Where "FF" is the frame initiator, no check, and a total of 7 bytes of data.
The three obtained data are respectively sent into corresponding modules, the control characters are used as the advance judgment standard to be carried out according to the established mode as shown in the table 1, two groups of data streams are respectively obtained, the two groups of data streams are respectively sent into respective multipliers, the amplitude values are amplified or reduced according to the table 1, the new data streams are obtained through processing, the new data streams are sent into a data selection module, the needed nonlinear digital signals are obtained, the nonlinear digital signals are output to an external DA conversion chip, and the analog signals are converted into the analog signals to obtain the needed nonlinear signals after the analog signals pass through a filter.
The control characters mentioned above are: 01, this is when the frequency is low, because the frequency is low, every X is required according to the control character in the address data frame 2 The address value of the X pulse clocks is increased by one, and X is the same as the address value of the X pulse clocks 2 In the X pulses, the address values are the same, at the moment, the ROM data read by a plurality of clock pulses are the same value, a step wave is output, and an analog signal is output after filtering; at this time, in the low frequency mode, i.e. the low frequency band signal, no matter how low the frequency is, only X will be 2 Since the value of X increases, theoretically, only X 2 X is big enough, can export infinitesimal frequency, but the cut-off frequency that needs post filter is low enough, just can restore standard sine wave signal, because just a step waveform just before the filtering, only need the parameter that changes the filter in each frequency channel just, and the precision of filter does not have the requirement, only need cut-off frequency is low enough, therefore the cost is very low, ordinary RC filter can realize, can do the resistance of RC through digital resistance, can change the parameter of filter through adjusting resistance value like this, need not to add other circuits again, and is with low costs, small, the consumption is low, is applicable to the power supply of electric power trade.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. A method of nonlinear signal generation comprising:
s1: after receiving the configuration data, converting the configuration data through an FPGA chip to obtain a control data frame;
s2: analyzing the control data frame through the FPGA chip to obtain control information, wherein the control information comprises: start character, control character, output signal frequency control information and data selection control information;
s3: determining an address accumulation amount through the FPGA chip according to the control character and the output signal frequency control information, performing address selection according to the address accumulation amount to obtain first address selection information and second address selection information, and performing data selection through the FPGA chip according to the first address selection information and the second address selection information to obtain first data and second data; the step S3 specifically includes:
S31: judging the type of the control character through the FPGA chip, if the control character is the first control character, executing S32, and if the control character is the second control character, executing S33;
s32: determining that the address accumulation amount is one through the FPGA chip, adding one to the first address after every first numerical clock pulse according to the output signal frequency control information, continuing the second numerical time in a period until the first address selection information is obtained, adding one to the second address after every third numerical clock pulse, and continuing the fourth numerical time in a period until the second address selection information is obtained;
s33: determining that the address accumulation amount is a first value according to the output signal frequency control information through the FPGA chip, adding the first value to the first address after every other clock pulse, continuing the second value for a time within one period until the first address selection information is obtained, adding the third value to the second address after every other clock pulse, and continuing the fourth value for a time within one period until the second address selection information is obtained;
s34: performing data selection according to the first address selection information and the second address selection information through the FPGA chip to obtain first data and second data;
S4: adding or selecting the first data and the second data according to the data selection control information through the FPGA chip to obtain a nonlinear digital signal;
s5: and performing digital-to-analog conversion on the nonlinear digital signal to obtain a nonlinear analog signal, and performing filtering operation on the nonlinear digital signal through a low-pass filter to obtain a filtered nonlinear signal.
2. The nonlinear signal generating method in accordance with claim 1, wherein the control information includes: a start character of two bytes, a control character of one byte, output signal frequency control information of four bytes, output signal amplitude control information of two bytes, and data selection control information of one byte;
the output signal frequency control information comprises four byte values, wherein the first byte value is a first value, the second byte value is a second value, the third byte value is a third value, and the fourth byte value is a fourth value.
3. The nonlinear signal generating method according to claim 2, further comprising, before step S4:
amplifying or shrinking the first data and the second data according to the output signal amplitude control information through the FPGA chip to obtain processed first data and processed second data;
S4: and adding or selecting the processed first data and the processed second data through the FPGA chip according to the data selection control information to obtain a nonlinear digital signal.
4. The method of claim 1, wherein the FPGA chip has an address selection range of 0 to 4095.
5. A non-linear signal generator, comprising: the device comprises a communication module, an FPGA chip, a digital-to-analog conversion module and a low-pass filter;
wherein, the FPGA chip includes: the system comprises a communication controller, a data analysis module, a first address module, a second address module, a clock module, a first memory, a second memory, a data selection module, a first multiplier and a second multiplier;
the communication controller is connected with the communication module and is used for receiving the configuration data sent by the communication module and converting the configuration data to obtain a control data frame;
the data analysis module is connected with the communication controller and is used for analyzing the control data frame to obtain control information, wherein the control information comprises: start character, control character, output signal frequency control information and data selection control information;
The data analysis module, the first address module and the first memory are connected in sequence, the first address module is used for determining an address accumulation amount according to control characters and output signal frequency control information, address selection is carried out according to the address accumulation amount to obtain first address selection information, and the first memory is used for outputting first data according to the first address selection information;
the data analysis module, the first address module, the first memory and the first multiplier are sequentially connected, the first multiplier is connected with the data analysis module and is used for processing the first signal according to the control information to obtain processed first data;
the data analysis module, the second address module, the second memory and the second multiplier are sequentially connected, the second multiplier is connected with the data analysis module, and the second multiplier is used for processing the second signal according to the control information to obtain processed second data;
the data selection module is connected with the data analysis module and is used for adding or selecting the processed first data and the processed second data according to the control information to obtain a nonlinear digital signal;
the data analysis module, the second address module and the second memory are connected in sequence, the second address module is used for determining an address accumulation amount according to control characters and output signal frequency control information, address selection is carried out according to the address accumulation amount to obtain second address selection information, and the second memory is used for outputting second data according to the second address selection information; specific:
The clock module is connected with the communication controller and is used for providing clock pulses;
the first address module is further used for determining that the address accumulation amount is one after judging that the type of the control character is a first control character, adding one to the first address after every first numerical clock pulse according to the output signal frequency control information, and continuing the second numerical time in a period until first address selection information is obtained;
the second address module is further configured to determine that the address accumulation amount is one after determining that the type of the control character is the first control character, increase the second address by one after every third numerical clock pulse according to the output signal frequency control information, and continue the fourth numerical value for a period until second address selection information is obtained;
the first address module is further used for determining that the address accumulation amount is a first value according to the output signal frequency control information after judging the type of the control character is a second control character, adding the first value to the first address after every other clock pulse, and continuing the second value for a plurality of times in a period until first address selection information is obtained;
the second address module is further configured to determine, according to the output signal frequency control information, that the address accumulation amount is a first value after determining that the type of the control character is the second control character, add a third value to the second address after every other clock pulse, and continue the fourth value for a period until second address selection information is obtained;
The first memory is used for outputting first data according to the first address selection information;
the second memory is used for outputting second data according to the second address selection information;
the data selection module is connected with the data analysis module and is used for adding or selecting the first data and the second data according to the data selection control information to obtain a nonlinear digital signal;
the data selection module is connected with the digital-to-analog conversion module, and the digital-to-analog conversion module is used for converting the nonlinear digital signals to obtain nonlinear analog signals;
the low-pass filter is used for carrying out filtering operation on the nonlinear digital signal to obtain a filtered nonlinear signal.
6. The non-linear signal generator of claim 5, wherein the control information comprises: a start character of two bytes, a control character of one byte, output signal frequency control information of four bytes, output signal amplitude control information of two bytes, and data selection control information of one byte;
the output signal frequency control information comprises four byte values, wherein the first byte value is a first value, the second byte value is a second value, the third byte value is a third value, and the fourth byte value is a fourth value.
7. The nonlinear signal generator in accordance with claim 5, wherein the FPGA chip has an address selection range of 0 to 4095.
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