CN107231151A - A kind of broadband Sweep Source design circuit and design method - Google Patents
A kind of broadband Sweep Source design circuit and design method Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
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- H03L2207/50—All digital phase-locked loop
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Abstract
The invention discloses a kind of broadband Sweep Source design circuit and design method, belong to synthetic wideband source technology field.The present invention is automatic inside FPGA in Sweep Source scanning process to realize the logic control of whole process at a high speed, stable under PC control, need not be interacted during frequency sweep with host computer, greatly reduce the frequency sweep time, optimize frequency-swept speed；A kind of algorithm optimization of FPGA internal arithmetics process is proposed in the case of ensureing that output signal is high performance, FPGA hardware resource has at utmost been saved, has reduced hardware cost.
Description
Technical field
The invention belongs to synthetic wideband source technology field, and in particular to a kind of broadband Sweep Source design circuit and design side
Method.
Background technology
The broadband Sweep Source for being currently based on integrated lock phase chip mainly carries out the switching of frequency by host computer, first
By carrying out the initialization of register to integrated lock phase chip, number is then put to particular register for different functions and realizes frequency
The switching of point, can be seen that in the whole scanning process of Sweep Source from this mode, it is necessary to be handed in real time with host computer
Mutual communication, the register for completing different frequent points is set, and is finally completed the frequency error factor of broadband Sweep Source, whole process and host computer
Interaction is excessive, and host computer typically uses industrial computer or Zero greeve controller etc., and its cycle of operation is ms grades, so in each frequency
Handoff procedure in can drag slow whole process with interacting for host computer, greatly increase the switching time of frequency.
In synthetic wideband source design at this stage, the volume, frequency range, output signal of synthetic source are mutually made an uproar, spuious, work(
The requirement more and more higher of rate stability and frequency modulated time, while for different applications, on the premise of low cost is pursued, needing
Ask emphasis also more and more diversified, current high-frequency wideband synthesis source circuit is mainly obtained by two schemes：
The first scheme：The synthetic wideband source circuit constituted based on discrete component, wherein so-called discrete component master
Refer to the device of composition synthesis phase-locked loop, such as phase discriminator, VCO are independent component, circuit company is carried out by printed board
Connect, the circuit volume that this mode takes is big, but control is simple, is mainly used in many phase-locked loops nestings to constitute high phase place
The synthetic wideband source circuit of noise objective, in this case, the control of circuit will become very because of the combination control of many loops
Complexity, this scheme is usually used in the broadband local oscillator module design in the generation of high-end simulation source, signal analysis quasi-instrument at present, but
Be in simple single loop phase lock circuitry, because its cost, VCO bandwidth, circuit volume restriction, while its final output letter
Number index also has no advantage, is just gradually replaced based on the facies-controlled synthetic wideband source scheme of integrated lock.
Second scheme：Based on the synthetic wideband source circuit of integrated lock phase chip, integrated lock phase integrated chip therein
Most of monocyclic lock such as parametric frequency divider, phase discriminator, charge pump, broadband VCO and feedback divider in phase-locked loop is mutually electric
Road, integrated level is high, while the output end in VCO increases integer frequency divider and frequency multiplier, further widens the frequency range covering of chip
Scope, only needs to the power supply biasing circuit and loop filter of addition periphery, occupies little space in use, integrated level
Height, cost is low, low in energy consumption, output signal mutually make an uproar index can meet it is most communication, the demand of RF application, be usually used in hand
Hold in the signal generation and analytical instrument of formula low side；But in the program integrated lock phase chip functions it is many, it is necessary to control deposit
Device digit is more, and control is complicated, and normal conditions need host computer to carry out the frequency handover that real-time operation completes broadband Sweep Source, this
The frequency handover time of mode is maintained at ms ranks, and overall sweep velocity is slower.
Prior art mainly has the deficiency of following three aspect：
Firstth, synthetic wideband source occupancy volume, the power consumption based on discrete phase lock circuitry are larger, and cost is high.
Secondth, the monocyclic scheme output signal in synthetic wideband source based on discrete phase lock circuitry mutually makes an uproar index with integrated lock phase core
Piece is compared and has no advantage.
3rd, the synthetic wideband source scheme based on integrated lock phase scheme, need to carry out the register of complexity with host computer at present
Control, whole frequency sweep process time is longer.
The content of the invention
For above-mentioned technical problem present in prior art, the present invention propose a kind of broadband Sweep Source design circuit and
Design method, it is reasonable in design, the deficiencies in the prior art are overcome, with good effect.
To achieve these goals, the present invention is adopted the following technical scheme that：
A kind of broadband Sweep Source designs circuit, including master controller, ALU, address decoding data buffer storage list
Member, ram memory cell, ALU, send counting unit, interrupt processing unit, integrated phase lock circuitry, region filtering circuit,
Power amplification circuit and fixed amplitude circuit；Master controller, ALU, ram memory cell, ALU, send number
Unit, integrated phase lock circuitry, region filtering circuit, power amplification circuit and fixed amplitude circuit pass sequentially through connection, address
Decoding data buffer unit respectively with master controller, ram memory cell by connection, interrupt processing unit respectively with RAM
Memory cell, ALU pass through connection；
Master controller, is configurable for carrying out logical-sequential control to whole Sweep Source；
ALU, is configurable for completing the corresponding frequency dividing ratio N.F logical operations of output frequency；
Address decoding data buffer storage unit, is configurable for completing the address storage of ram memory cell；
Ram memory cell, is configurable for the corresponding frequency dividing ratio N.F of storage Sweep Source output frequency；
Logic control element, is configurable for completion RAM data and calls, and the accumulation of address ram is calculated；
Counting unit is sent, the parallel data for being configurable for transmitting logic control element is converted into serial data and sent out
Send；
Interrupt processing unit, is configurable for carrying out cumulative by the count pulse of master controller and then is ordered according to host computer
Order produces interrupt signal control logic control unit；
Integrated phase lock circuitry, is configurable for carrying out the frequency synthesis output of Sweep Source；
Region filtering circuit, is configurable for carrying out region filtering to the frequency signal of output；
Power amplification circuit, is configurable for carrying out power amplification to output frequency；
Fixed amplitude circuit, is configurable for carrying out fixed ampllitude to the power of output frequency, ensures the frequency stabilization of power output
Degree；
In addition, the present invention is it is also mentioned that a kind of broadband Sweep Source design method, this method is using a kind of broadband as described above
Sweep Source designs circuit, comprises the following steps：
Step 1：In each sweep phase, master controller sends initial frequency, Step Frequency to ALU successively
Rate and stepping number parameter, the first address data of ram memory cell are sent to address decoding data buffer storage unit；
Step 2：ALU is by initial frequency, step frequency and stepping number, by integrated phase lock circuitry itself
Control mode, on the premise of ensureing that phase demodulation frequency is fixed, N.F corresponding to each frequency is carried out from calculating, master controller
The first address of ram cell is inputted into address decoding data buffer storage unit, RAM is completed by accumulator in logic control element
The accumulation calculating of address, the cumulative address ram completed and the N.F data obtained in ALU correspond and carry out RAM
Data storage, so under the logic control of master controller, completes ram memory cell inside frequency dividing ratio during whole frequency sweep
N.F data are loaded；
Step 3：After the completion of data are loaded, master controller starts to send synchronous to interrupt processing unit and ALU
Trigger pulse, is added up by counting reading address in completion ram memory cell to pulse accumulation in interrupt processing unit, passed through
Accumulator and data call unit complete calling and frequency step number for data in ram memory cell in ALU
It is cumulative, send SPI data conversions in counting unit that N.F control words are sent into integrated lock, it is necessary to coordinate wherein completing a data call
In circuitry phase；
Step 4：Send counting unit to send into data after integrated phase lock circuitry, sequentially pass through region filtering circuit, the work(of rear end
Rate amplifying circuit and fixed amplitude circuit, are finally completed the switching of a frequency；
Step 5：Under the control of synchronous trigger pulse, repeat step 3- steps 4 complete stepping number by cumulative clock
It is cumulative, after stepping number is reached, interrupt signal is produced under next synchronous trigger pulse, by the reading of ram memory cell
Location automatically returns to the first address of ram memory cell, starts multiple scanning process；
Step 6：Master controller to ALU by carrying out initial frequency, step frequency and stepping number again
Set, complete the switching of frequency sweep state.
Preferably, the N.F is main by integer frequency ratio NINTCompare N with fractional frequency divisionFRACTwo parts are constituted.
Preferably, in step 2, N.F corresponding to each frequency is carried out from calculating according to formula (1)；
Wherein, NINTFor integer frequency ratio；NFRACFor fractional frequency division ratio；FVCOSpan is 1500MHz~3000MHz；
NINTPass through FVCO50 progress divisions are rounded and can obtained；NFRACObtained by formula (2)；
Complete FVCOTo 50MHz=50 × 106After Hz remainders are calculated, 2 are completed by moving to left 1717Multiplying, passes through
8 times are carried out except 5 computings complete NFRACCalculate, wherein, in division arithmetic, do not influenceing NFRAC, it is necessary to right in the case of significance bit
NFRACValue carries out real-time digit optimization.
Preferably, to NFRACThe specific Optimization Steps that value carries out real-time digit optimization are as follows：
Step 1：NFRAC1st time except 5, NFRAC2 are moved to right, 2 are given up；
Step 2：NFRAC2nd time except 5, NFRAC2 are moved to right, 2 are given up；
Step 3：NFRAC3rd time except 5, NFRAC2 are moved to right, 2 are given up；
Step 4：NFRACThe 4th removes 5, NFRAC3 are moved to right, 3 are given up；
Step 5：NFRACThe 5th removes 5, NFRAC2 are moved to right, 2 are given up；
Step 6：NFRAC6th time except 5, NFRAC2 are moved to right, 2 are given up；
Step 7：NFRAC7th time except 5, NFRAC3 are moved to right, 3 are given up；
Step 8：NFRAC8th time except 5, NFRAC2 are moved to right, 2 are given up.
The advantageous effects that the present invention is brought：
(1) present invention is automatic inside FPGA in Sweep Source scanning process to realize that whole process is high under PC control
Speed, stable logic control, need not interact with host computer during frequency sweep, greatly reduce the frequency sweep time, optimize frequency
Rate sweep velocity.
(2) present invention proposes that a kind of algorithm of FPGA internal arithmetics process is excellent in the case of ensureing that output signal is high performance
Change, at utmost saved FPGA hardware resource, reduced hardware cost.
Brief description of the drawings
Fig. 1 is the theory diagram of the inventive method.
Wherein, 1- ALUs；2- address decoding data buffer storage units；3-RAM memory cell；4- logical operation lists
Member；5- send counting unit；6- interrupt processing units；The integrated phase lock circuitries of 7-；8- region filtering circuits；9- power amplification circuits；10-
Fixed amplitude circuit.
Embodiment
Below in conjunction with the accompanying drawings and embodiment is described in further detail to the present invention：
The invention reside in the deficiencies in the prior art are made up, a kind of miniaturization based on programmable logic controller (PLC) is devised wide
Band high speed frequency sweep source circuit, its solution principle block diagram are as shown in figure 1, this programme is main by ALU 1, address decoding number
According to buffer unit 2, ram memory cell 3, ALU 4, send counting unit 5, interrupt processing unit 6, integrated phase lock circuitry 7,
Region filtering circuit 8, power amplification circuit 9 and fixed amplitude circuit 10 are constituted.Completed by additional reference signal and master controller
Whole broadband Sweep Source control.Specific control process is as follows：
(1) in each sweep phase, master controller sends initial frequency, step frequency to ALU 1 successively
With stepping number parameter, RAM first address data are sent to address decoding data buffer storage unit 2；
(2) by initial frequency, step frequency and stepping number in ALU 1, by integrated phase lock circuitry 7 itself
Control mode, on the premise of ensureing that phase demodulation frequency is fixed, N.F corresponding to each frequency is carried out from calculating, in main control
Device the first address of ram memory cell 3 control under, by interrupt processing unit 6 to the accumulation calculating of the address of ram memory cell 3
It is sequentially completed the N.F obtained in ALU 1 to be stored, address sum in ram memory cell 3 during completion frequency sweep
According to loading；
(3) after the completion of data are loaded, master controller starts to send synchronization to interrupt processing unit 6 and ALU 4
Trigger pulse, is added up by counting reading address in completion ram memory cell 3 to pulse accumulation in interrupt processing unit 6, led to
Cross in ALU 4 and tire out plus/minus device and data call unit and complete calling and frequency steps for data in ram memory cell 3
Enter the cumulative of number, send SPI data conversions in counting unit 5 to send N.F control words, it is necessary to coordinate wherein completing a data call
Enter in integrated phase lock circuitry 7；
(4) send counting unit 5 to send into data after integrated phase lock circuitry 7, sequentially pass through region filtering circuit 8, the work(of rear end
Rate amplifying circuit 9 and fixed amplitude circuit 10, are finally completed the switching of a frequency.
(5) under the control of synchronous trigger pulse, (3)-(4) step is repeated, completing stepping number by cumulative clock tires out
Plus, after stepping number is reached, interrupt signal is produced under next synchronous trigger pulse, by the reading address of ram memory cell 3
The first address of ram memory cell 3 is automatically returned to, starts multiple scanning process.
(6) master controller is set by carrying out initial frequency, step frequency and stepping number to ALU 1 again
Put, complete the switching of frequency sweep state.
ALU is mainly completed to N.F frequency dividing ratios from calculating, and wherein N.F is mainly made up of two parts, respectively
For integer frequency ratio NINTCompare N with fractional frequency divisionFRAC；Integrated phase lock circuitry control in patent of the present invention is mainly based upon ADI/
HMC820, HMC840, HMC830, HMC833 and HMC834 family chip of Hittite companies, its control mode are general, this hair
Bright patent is from VCO output of the HMC833 chips based on fundamental wave section 1500MHz~3000MHz, and rear end passes through 2 frequencys multiplication and 1~62
Secondary integral frequency divisioil completes the output of final 25MHz~6000MHz wide-bands, and wherein frequency step is mainly by changing N.F points
Frequency ratio is completed.And N.F completes to calculate by below equation：
Wherein NINTPass through FVCO50 progress divisions are rounded, key point of the invention is to fractional frequency division NFRACMeter
Calculate, because carrying 24bit ∑-△ modulation frequency dividers inside HMC family chips, it is contemplated that the minimum 6Hz steppings essence of Sweep Source
Degree (is based on 50MHz phase demodulation frequencies), is needed in ALU 1 to N thereinFRACAlgorithm optimization, and
Pass through NFRACCalculation formula can be seen that in programmable logic controller (PLC) FPGA arithmetic element, multiplication and division fortune
Calculation can take substantial amounts of logical resource, if not doing algorithm optimization, can directly bring the increase of hardware cost, complete here
FVCOTo 50MHz=50 × 106After Hz remainders are calculated, 2 are completed by moving to left 1717Multiplying, 5 computings are removed by carrying out 8 times
Complete NFRACCalculate, in division arithmetic, do not influenceing NFRAC, it is necessary to N in the case of significance bitFRACValue carries out real-time position
Number optimization is as shown in table 1 below to reduce the digit optimization in the occupancy of logical resource in calculating process, specific division process as far as possible.
The N of table 1FRACThe specific optimized algorithm of internal arithmetic
It can be seen from Table 1 that, by each computings of ÷ 5, while gained NFRACCarry out it is different move to right truncation, ensureing
NFRAC, at most can be to N in the case of digit optimization is completed as far as possible in the case of significance bitFRACProcess computing optimizes 18,
Greatly reduce the logical resource occupancy inside FPGA, hardware cost during reduction FPGA type selectings.
Certainly, described above is not limitation of the present invention, and the present invention is also not limited to the example above, this technology neck
The variations, modifications, additions or substitutions that the technical staff in domain is made in the essential scope of the present invention, should also belong to the present invention's
Protection domain.
Claims (5)
1. a kind of broadband Sweep Source designs circuit, it is characterised in that：Including master controller, ALU, address decoding number
According to buffer unit, ram memory cell, ALU, send counting unit, interrupt processing unit, integrated phase lock circuitry, segmentation filter
Wave circuit, power amplification circuit and fixed amplitude circuit；Master controller, ALU, ram memory cell, logical operation list
Member, send counting unit, integrated phase lock circuitry, region filtering circuit, power amplification circuit and fixed amplitude circuit pass sequentially through circuit company
Connect, address decoding data buffer storage unit passes through connection, interrupt processing unit point with master controller, ram memory cell respectively
Connection is not passed through with ram memory cell, ALU；
Master controller, is configurable for carrying out logical-sequential control to whole Sweep Source；
ALU, is configurable for completing the corresponding frequency dividing ratio N.F logical operations of output frequency；
Address decoding data buffer storage unit, is configurable for completing the address storage of ram memory cell；
Ram memory cell, is configurable for the corresponding frequency dividing ratio N.F of storage Sweep Source output frequency；
Logic control element, is configurable for completion RAM data and calls, and the accumulation of address ram is calculated；
Counting unit is sent, the parallel data for being configurable for transmitting logic control element is converted into serial data and is transmitted；
Interrupt processing unit, is configurable for carrying out cumulative by the count pulse of master controller and then is produced according to host computer order
Raw interrupt signal control logic control unit；
Integrated phase lock circuitry, is configurable for carrying out the frequency synthesis output of Sweep Source；
Region filtering circuit, is configurable for carrying out region filtering to the frequency signal of output；
Power amplification circuit, is configurable for carrying out power amplification to output frequency；
Fixed amplitude circuit, is configurable for carrying out fixed ampllitude to the power of output frequency, ensures the frequency stability of power output.
2. a kind of broadband Sweep Source design method, it is characterised in that：Set using a kind of broadband Sweep Source as claimed in claim 1
Circuit is counted, is comprised the following steps：
Step 1：In each sweep phase, master controller successively to ALU send initial frequency, step frequency and
Stepping number parameter, the first address data of ram memory cell are sent to address decoding data buffer storage unit；
Step 2：ALU is by initial frequency, step frequency and stepping number, by the control of itself of integrated phase lock circuitry
Mode processed, on the premise of ensureing that phase demodulation frequency is fixed, N.F corresponding to each frequency is carried out from calculating, and master controller is to ground
The first address of ram cell is inputted in the decoding data buffer unit of location, address ram is completed by accumulator in logic control element
Accumulation calculating, the cumulative address ram completed and the N.F data obtained in ALU correspond and carry out RAM data
Storage, so under the logic control of master controller, frequency dividing ratio N.F inside ram memory cell during the whole frequency sweep of completion
Data are loaded；
Step 3：After the completion of data are loaded, master controller starts to send synchronous triggering to interrupt processing unit and ALU
Pulse, is added up by counting reading address in completion ram memory cell to pulse accumulation in interrupt processing unit, passes through logic
Accumulator and data call unit complete calling for data and tiring out for frequency step number in ram memory cell in arithmetic element
Plus, send SPI data conversions in counting unit that N.F control words are sent into integrated lock phase, it is necessary to coordinate wherein completing a data call
In circuit；
Step 4：Counting unit is sent to send into data after integrated phase lock circuitry, region filtering circuit, the power for sequentially passing through rear end are put
Big circuit and fixed amplitude circuit, are finally completed the switching of a frequency；
Step 5：Under the control of synchronous trigger pulse, repeat step 3- steps 4 complete stepping number by cumulative clock and tired out
Plus, after stepping number is reached, interrupt signal is produced under next synchronous trigger pulse, by the reading address of ram memory cell
The first address of ram memory cell is automatically returned to, starts multiple scanning process；
Step 6：Master controller is set by carrying out initial frequency, step frequency and stepping number to ALU again
Put, complete the switching of frequency sweep state.
3. frequency sweep operated control method in broadband according to claim 2, it is characterised in that：The N.F is main by integral frequency divisioil
Compare NINTCompare N with fractional frequency divisionFRACTwo parts are constituted.
4. frequency sweep operated control method in broadband according to claim 2, it is characterised in that：In step 2, to each frequency phase
The N.F answered is carried out from calculating according to formula (1)；
Wherein, NINTFor integer frequency ratio；NFRACFor fractional frequency division ratio；FVCOSpan is 1500MHz~3000MHz；NINTIt is logical
Cross FVCO50 progress divisions are rounded and can obtained；NFRACObtained by formula (2)；
Complete FVCOTo 50MHz=50 × 106After Hz remainders are calculated, 2 are completed by moving to left 1717Multiplying, by carrying out
8 times except 5 computings completion NFRACCalculate, wherein, in division arithmetic, do not influenceing NFRAC, it is necessary to N in the case of significance bitFRAC
Value carries out real-time digit optimization.
5. frequency sweep operated control method in broadband according to claim 4, it is characterised in that：To NFRACValue carries out real-time digit
The specific Optimization Steps of optimization are as follows：
Step 1：NFRAC1st time except 5, NFRAC2 are moved to right, 2 are given up；
Step 2：NFRAC2nd time except 5, NFRAC2 are moved to right, 2 are given up；
Step 3：NFRAC3rd time except 5, NFRAC2 are moved to right, 2 are given up；
Step 4：NFRACThe 4th removes 5, NFRAC3 are moved to right, 3 are given up；
Step 5：NFRACThe 5th removes 5, NFRAC2 are moved to right, 2 are given up；
Step 6：NFRAC6th time except 5, NFRAC2 are moved to right, 2 are given up；
Step 7：NFRAC7th time except 5, NFRAC3 are moved to right, 3 are given up；
Step 8：NFRAC8th time except 5, NFRAC2 are moved to right, 2 are given up.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001063742A1 (en) * | 2000-02-25 | 2001-08-30 | Infineon Technologies Ag | Swept frequency phase locked loop |
| US6906560B1 (en) * | 2004-01-20 | 2005-06-14 | Harris Corporation | Phase-continuous frequency synthesizer |
| CN102468805A (en) * | 2010-11-03 | 2012-05-23 | 北京普源精电科技有限公司 | Sweep signal generator and method for generating sweep signals |
| CN101917204B (en) * | 2010-08-23 | 2013-04-24 | 中国电子科技集团公司第四十一研究所 | Computing and digital control method of scanning control parameters of scanning frequency receiver |
| CN103152034A (en) * | 2013-02-26 | 2013-06-12 | 中国电子科技集团公司第四十一研究所 | Decimal frequency dividing phase-locked loop circuit and control method for frequency dividing ratio |
| CN103178782A (en) * | 2011-12-21 | 2013-06-26 | 北京普源精电科技有限公司 | Frequency sweeping signal generator |
| CN104320087A (en) * | 2014-10-13 | 2015-01-28 | 中国电子科技集团公司第四十一研究所 | High-speed digital frequency scanning method |
-
2017
- 2017-05-24 CN CN201710371340.9A patent/CN107231151B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001063742A1 (en) * | 2000-02-25 | 2001-08-30 | Infineon Technologies Ag | Swept frequency phase locked loop |
| US6906560B1 (en) * | 2004-01-20 | 2005-06-14 | Harris Corporation | Phase-continuous frequency synthesizer |
| CN101917204B (en) * | 2010-08-23 | 2013-04-24 | 中国电子科技集团公司第四十一研究所 | Computing and digital control method of scanning control parameters of scanning frequency receiver |
| CN102468805A (en) * | 2010-11-03 | 2012-05-23 | 北京普源精电科技有限公司 | Sweep signal generator and method for generating sweep signals |
| CN103178782A (en) * | 2011-12-21 | 2013-06-26 | 北京普源精电科技有限公司 | Frequency sweeping signal generator |
| CN103152034A (en) * | 2013-02-26 | 2013-06-12 | 中国电子科技集团公司第四十一研究所 | Decimal frequency dividing phase-locked loop circuit and control method for frequency dividing ratio |
| CN104320087A (en) * | 2014-10-13 | 2015-01-28 | 中国电子科技集团公司第四十一研究所 | High-speed digital frequency scanning method |
Non-Patent Citations (3)
| Title |
|---|
| DECHUN ZHAO 等: "A FPGA-based Sweep-frequency Voltage Source for EIT System", 《2010 INTERNATIONAL CONFERENCE ON ELECTRONICS AND INFORMATION ENGINEERING》 * |
| 潘林杰: "1.2～2.4GHz合成扫频源的设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
| 王李飞 等: "小型化高性能多模式宽带合成源方案设计", 《微波学报》 * |
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