WO2001063742A1

WO2001063742A1 - Swept frequency phase locked loop

Info

Publication number: WO2001063742A1
Application number: PCT/EP2000/001575
Authority: WO
Inventors: Michael-Richard Richardson
Original assignee: Infineon Technologies Ag
Priority date: 2000-02-25
Filing date: 2000-02-25
Publication date: 2001-08-30

Abstract

A Phase Locked Loop for frequency sweeping comprises a dual modulus prescaler counter (2) and a swallow counter (4) having two modulus counters (41, 42) in the feedback path. The modulus values N and A of the swallow modulus counters are generated from a sequence of consecutive values (p, p + 1, p + 2, ..., q) by a conversion device (9). The update of the modulus values (N, A) as well as the conversion and the generation of the consecutive values are controlled synchronously by a cycle counter (11). The Phase Locked Loop provides a linear frequency sweep and low phase noise.

Description

Swept Frequency Phase Locked Loop

The invention refers to a Phase Locked Loop for frequency sweeping with a Voltage Controlled Oscillator, a feedback loop with a phase comparator and a counter arrangement in the feedback loop.

Many types of sensor systems employ Continous Wave (CW) transmissions. In such sensor systems a Swept Frequency Phase Locked Loop can be used. The implementation with available technology is easy, and the circuits are power efficient. CW transmissions have the advantage that, in comparison with other types of modulation, they generally do not cause significant EMC problems or create the kind of safety hazards which may be present with the high peak powers generated by pulsed type signals. In many applications a suitable form of modulation must be applied in order to permit the sensor to measure parameters such as range and speed. One form of modulation involves Frequency Modulation (FM) or Phase Modulation (PM) using Voltage Controlled Oscillators (VCOs) . The oscillation frequency of the VCO is controlled by an external applied low frequency signal. FM and PM lead to similar embodi- ments. Linear Frequency Sweeping employing FM or PM methods use a VCO whose frequency is swept from frequency fi to frequency f₂ in a time interval τ at a constant of (f₂ - fi) 1% Hz/s. Frequency sweeping may consist of a series of unidirectional sweeps with a fast flyback to the start frequency af- ter each sweep or a series of up and down sweeps or even a more complex combination of sweeps of deferring bandwidth rates and directions, combined with periods of an unmodulated signal. This is often called Frequency Modulated Continuous Wave, or FM-CW modulation. It is an objective of the invention to provide a Phase Locked Loop (PLL) for frequency sweeping which is easy to implement and provides a linear sweep and low phase noise.

This objective is solved by a Phase Locked Loop, comprising: a Voltage Controlled Oscillator,- a feedback loop comprising a phase comparator for comparing a reference frequency signal with a feedback signal, said feedback being supplied from an output of the Voltage Controlled Oscillator via a counter ar- rangement; said counter arrangement performing a variable modulus count being controlled by corresponding modulus values; said modulus values being generated by a control device comprising a source for consecutive values, a conversion device for converting said consecutive values to said modulus values for said first and second counters and a cycle counter being controlled by a reference clock generator; said cycle counter synchronously controlling said source for consecutive values and said conversion device.

The Phase Locked Loop according to the invention can use commercially available components, whereby linear sweeping is achieved through appropriate control of the synthesiser logic which provides proper counter load values and timing signals . In Continuous Wave mode the frequency and phase control loop digitally divides down the VCO frequency by a ratio provided by the modulus value loaded into a programmable counter. The load values are provided by the control logic with the necessary time synchronisation. The counter output signal is digitally compared with a stable reference clock in a phase com- parator. This produces a pulse train in which polarity and width of successive pulses represent the phase error between the counter output and the- reference clock. This pulse train is low pass filtered and the filter output drives the VCO tuning signal. If the actual division ratio of the counter arrangement is n, and the reference clock frequency is f_r, then the VCO frequency is stabilised to the frequency n * f_r. When the loop is in lock, the cycle time of the programmable counter is always l/f_r.

Any random short-term fluctuations of the phase or frequency caused by noise effects, so called phase noise, are reduced. The control loop of the Phase Locked Loop synthesiser has a response bandwidth which is determined by the VCO and loop filter parameters as well as the division ratio of the counter arrangement. When the loop is in lock, any phase noise with spectral components within the response bandwidth of the loop is reduced. The dynamic control reduces spectral noise sideband levels close to the VCO frequency in comparison to open loop or free running VCOs .

In order to achieve all possible integer frequency division ratios over a given range from p to q (q > p) , the programmable counter arrangement is implemented with a swallow counter. There are also alternative division techniques possible which achieve the same end result compared to a swallow coun- ter. i - __,

The VCO frequency is made to sweep between frequencies ]_ = p * f_r and f2 = q * f_r (P > <l) by loading a selected subset of all the possible integer division ratios in the se- quence p, p + 1, p + 2, p + 3, ..., q - 2, q - 1, q at regular time intervals to the programmable counter. For an upsweep, the generation order is p to q and for a downsweep the order is q to p. The smallest increment and decrement between frequency division ratios is achieved when all integer values between p and q are chosen. However, according to system design constraints, it may be necessary or desirable to load only a subset of every second, third, fourth etc. division ratio.

Each frequency division ratio must be executed for exactly k programmable counter cycles, with k = 1, 2, 3, ... Thus the division ratio update rate is f_r/k. The PLL according to the invention generates a phase continuous linear frequency sweep between f]_ and f2 with reduced phase noise.

The control logic for providing the sequence of frequency division ratios from p to q can be implemented as an ASIC, ΞPLD, microcontroller or with discrete digital components.

In order to achieve all possible integer division ratios over the range p to q, the programmable counter can be implemented by a counter chain comprising a dual modulus prescaler and a swallow counter. The swallow counter itself is split into two sections, often referred to as the N and A counters. The N and A counters are modulus counters and during each division cycle they are both clocked by the output of the prescaler and each performs a count cycle equal to the modulus value selected for it for that division cycle. During each cycle, the swallow counter selects the division modulus of the dual modulus prescaler according to the value in the A counter, and in this way provides all of the integer division ratios in the range p to q. The swallow counter must be supplied with the new modulus values before the end of the final count cycle with the previous values, so that the new modulus values are avail- able for use when the first count cycle to use the new modulus values begins. The control logic and counter system must operate so that no spurious count events are generated and no count events are lost when modulus values are updated. This ensures that a linear frequency sweep with no phase disconti- nuities is generated. For example, on all count cycles for a given division ratio, m, the swallow counter must complete its count cycle within m frequency cycles of the VCO. After updating the modulus values for the next division ratio m - n or m + n the swallow counter must complete its count cycle within m - n or m + n frequency cycles of the VCO respectively. Further, the loop filter characteristics must be chosen to ensure that the synthesiser response bandwidth is sufficiently wide to ensure that on the one hand the loop remains in lock at each frequency division ratio update, but on the other hand is not so wide that significant frequency side bands are generated at the VCO output due to breakthrough of the transient phase error pulses generated by the phase comparator at the end of every division cycle.

Preferred embodiments of the invention are given in the de- i ; -i pendent claims .

The reference clock is generated by a stable reference clock generator and is divided by r to be provided to the reference signal input of the phase comparator. The cycle counter which generates the clock that drives the components of the control logic performs a division by k * r and is fed with the stable reference clock signal.

A modulus register is provided which is connected to the modulus input of the swallow counter. The modulus register is updated at the end of the count cycle of the swallow counter so that the new modulus values are loaded into the modulus register at the end of the extant division cycle and can then be used by the swallow counter on the following division cycle. This modulus value storage register must be double buffered using a transfer register in order to make it possible to pre-load new modulus values for N and A into the transfer register at any time without disturbing the operation of the swallow counter. An enable signal input must be available which has the function of arming the modulus register update sequence and thus controlling when new modulus values become operative. The cycle counter in the control logic generates the sweep update timing and the swallow counter cycle in the PLL feedback loop is forced to synchronise to this counter by use of the enable signal. A frequency division sequence source or generator generates the modulus values p, p + 1, p + 2, ... For an upsweep the start value is the quotient of the lowest sweep frequency and the reference frequency and the end value of the sequence of modulus values is the quotient of the highest sweep frequency and the reference frequency. For a downsweep the start value is the quotient of the highest sweep frequency and the reference frequency and the end value is the quotient of the lowest sweep frequency and the reference frequency. The genera- tion of the modulus values is triggered by the cycle counter. The swallow counter modulus values N and A are generated according to the formula X * N + A = s, whereby X is the base modulus of the dual modulus prescaler which can divide by a factor of X or X + 1, and s is the current modulus value of the sequence p, ... , q.

The loop filter characteristics must be chosen so that the loop remains in lock at each frequency division ratio update and does not allow a breakthrough of the transient phase er- ror signal at each time when the division ratio is updated. The loop filter has a bandwidth which is a fraction of the frequency f_r. Preferably the loop filter has a bandwidth which is less than a fraction of 1/20 of the reference frequency f_r. The N and A counters of the swallow counter and the dual modulus prescaler operate as a division counter which is clocked at the VCO frequency by the portion of the VCO output signal and divides the VCO frequency by a factor of s, according to the formula s = X * N + A. The output of the counter block is fed to the digital phase comparator, where it is compared with the reference frequency input to produce an output signal pulse train at the reference frequency f_r in which the pulse widths and polarities represent the phase error between the two input signal to the comparator, and which is used to drive the loop filter input.

In a double loop configuration another PLL is connected downstream to the output of the VCO of the first PLL that con- tains the swallow counter for frequency sweeping. Especially in microwave transmitters when the synthesiser PLL response bandwidth may be limited by sideband suppression constraints which conflict with the requirements for transmitter phase noise control, the double loop design can be employed to permit both linear frequency sweeping and phase noise control to be achieved. The VCO output of the frequency sweep PLL is connected to the reference input of the phase comparator of the PLL connected downstream. When the synthesiser loop is swept, the second loop forces the transmitter VCO to track the synthesiser loop output. The second PLL has a wide control bandwidth so that frequency tracking of the linear frequency sweep from the synthesiser is very accurate. Also, effective phase noise control is obtained. Preferably, both loops are operated at a convenient intermediate frequency and the transmit VCO frequency is down converted by frequency mixing or prescaling. The second VCO is a simple PLL with no programmable swallow counter so that increased complexity is paid off by low phase noise and linear frequency sweep.

The principles and preferred embodiments of the invention are now described with respect to the embodiments depicted in the drawings . Corresponding elements are denoted by like reference numerals. In the drawings, the various figures show:

Figure 1 a swept frequency Phase Locked Loop according to the invention and

Figure2 a double loop configuration including a swept frequency Phase Locked Loop.

The PLL in figure 1 shows a Voltage Controlled Oscillator (VCO) 1 the oscillation frequency of which is controllable by a control voltage. The output signal of the VCO 1 is transmitted via an antennae in a radar system. A proportion of the VCO output signal is fed back through a control loop. The control loop comprises a prescaler 2, a swallow counter 4 and a phase comparator 5 which compares the swallow count signal with a reference frequency signal at frequency f_r. The output signal of the phase comparator 5 is provided to a loop filter 6 the output of which provides the control voltage signal for the VCO 1. The swallow counter 4 comprises an N modulus coun- ter 41 and an A modulus counter 42. Both the N and A modulus counters 41 and 42 are clocked by the dual modulus prescaler 2 and are provided with modulus values through a modulus register 7. At the start of the count cycle both N and A modulus counters 41 and 42 are preset from the modulus register 7 and the prescaler 2 modulus value is set to X + 1 . Both modulus counters 41 and 42 then begin to count down. When the A modulus counter 42 reaches zero the prescaler 2 modulus value is set to X. The count then proceeds until the N counter 41 reaches zero when the next set of modulus values is loaded from modulus register 7 and a clock pulse is supplied to the phase comparator 5.

In order to provide the modulus values A and N, a frequency division sequence generator 8 generates the required subse- quence of modulus values selected from the sequence p, p + 1, p + 2, ... , q for an upsweep (or q, q - 1, q - 2, ...., p for a downsweep) . The generator 8 receives a control signal for start as well as for up/down selection. A converter 9 receives the modulus values p, ... , q from the generator 8 and converts them into a corresponding combination of A and N modulus values for the swallow counter 4. A transfer register 10 is connected between the converter 9 and the modulus register 7.

A cycle counter 11 controls the operation of the control logic. The output signal of the cycle counter 11 is provided to modulus register 7 to enable the update with new modulus values A, N. Further it is provided to the converter 9 to generate and transfer a new combination of modulus values A, N to transfer register 10. Finally, it is provided to the frequency division sequence generator 8 to update the p, ..., q sequence. A stable frequency signal from a reference clock generator 12 is provided to the cycle counter 11. The cycle counter 11 performs a division by k * r. Also, a reference counter 13 divides the stable reference clock from clock generator 12 by r to obtain the reference frequency f_r. The value r is fixed. The value k is an integer k = l, 2, 3, ..., appropriately chosen to generate the required sweep parameters.

The swept frequency PLL can be designed for an Adaptive Cruise Control sensor with the following parameters. The required sweep must span 200 MHz in 2 ms. The centre frequency is chosen to be 1 GHz, so the sweep limits are fi = 900 MHz and f₂ = 1100 MHz with τ = 2 ms . The prescaler 2 is a 32/33:1 dual modulus prescaler, and the swallow counter 4 is split into a 5 bit A register 42 and a 7 bit N register 41. The loop bandwidth B must be chosen to be wide enough to track the sweep and to be considerably smaller than the reference frequency f_r so that the breakthrough at this frequency from the loop phase comparator is filtered out. In the practical design B = 20/τ and f_r > 20 * B. In this case this results in B = 10 kHz and f_r > 200 kHz. Here, it is convenient to chose f_r = 312.5 kHz. As with most synthesiser chips the internal reference counter 13 can be programmed to generate the desired reference frequency from a standard frequency crystal clock. Here, 312.5 kHz can be conveniently generated by the division of 20 MHz by 64. The swallow counter update rate is set equal to the reference frequency, therefore k = 1. Thus, the sweep is generated from a sequence of 639 frequency steps, with 312.5 KHz spacing and each of duration of 3.2 μs, giving an actual sweep time of 2.045 ms which is deemed to be sufficiently close to the specified time of 2 ms .

There is a number of possible combinations of reference frequency and update rate to generate the required sweep parame- ters . For a highly linear sweep the number of steps in the sweep should be maximised. However, other system performance constraints demand that f_r is made as large as possible, since breakthrough from the phase comparator is then easier to filter out. Since the number of steps in sweep is inversely proportional to f_r due to the fact that each step is always equal in size to f_r or a multiple of f_r, the choice of optimum sweep parameters is always a compromise between conflicting system design constraints of large step count and high reference frequency.

The values p and q can be calculated as p = fι/f_r = 2880, and q = f₂/f_r = 3520. For an upsweep the sequence is 2880, 2881, 2882, ..., 3520, and for a downsweep the sequence 3520, 3519, 3518, ... , 2880.

The modulus values A and N for the swallow counter 4 are de- rived from the sequence p, ..., s, ..., q with s being a sequence member using the following relationship with a 32/33:1 prescaler: 32 * N + A = s. The modulus values A and N for an upsweep are:

p, ... , s, ... , q A N

2880 0 90 2881 1 90 2882 2 90

2911 31 90 2912 0 91 2913 1 91

3520 0 110

Some synthesiser circuits do not operate correctly if the A modulus value is less than 2, due to logic timing constraints. This problem may be solved by adding 3 to all A modulus val- ues, so that the A modulus value sequence is 3, 4, 5, . , ., 31, 32, 33, 34, 3, 4, ... instead of 0, 1, 2, 3, ..., 29, 30, 31, 0, 1, ... This results in the whole sweep being increased in frequency by 3 * f_r, which is normally only a negligible amount .

The control logic function to provide the A and N modulus values may be realised by a DSP program or a state machine in a FPGA. The A and N modulus values must be provided to the swallow counter 4 in synchronism with the swallow counter division cycle. Preferably, the swallow counter is updated at the end of its count cycle so that the new modulus values are loaded into this register at the end of the extant division cycle and are then used by the swallow counter on the following division cycle. The swallow counter modulus storage register 7 must be double buffered using a transfer register 10, in order to make it possible to preload new modulus values for A and N into the transfer register at any time without disturbing the operation of the swallow counter. An enable signal must be available which has the function of arming the modulus register update sequence and thus controlling when new modulus values become operative. The cycle counter 11 in the control logic generates the sweep update timing and the swallow counter cycle in the feedback loop is forced to synchronise to this counter by use of the enable signal. All the logic must be driven by the same stable reference clock 12 to ensure synchronous operation. The cycle counter can be pro- grammed with k times the division ratio r of the reference counter 13. The cycle counter produces an output pulse train at rate f_r/k, and the swallow counter produces an output pulse train at rate f_r. The output of the synthesiser reference counter 13 is used for the phase comparator reference in the PLL, and the output of the cycle counter 11 is used for triggering the control logic . The trigger performs three functions. Firstly, it clocks the frequency division sequence generator 8 to produce the next value in the p, ..., q sequence every k cycles of the swallow counter 4. Secondly, it initiates the conversion to the next pair of A and N values by the converter 9 and their loading into the transfer register 10. Thirdly, it supplies the enable pulse which arms the modulus register 7 causing it to update from the transfer register at the end of the swallow counter cycle with the A and N values which were generated and transferred during the previous cycle.

The frequency swept PLL rapidly synchronises to the control logic after power up. The correct modulus values are quickly established, and the swallow counter then begins to cycle with the correct division ratio. The PLL subsequently pulls into lock, and when in lock, both inputs to the phase comparator 5 are in phase at frequency f_r. Thus, when lock is achieved, the swallow counter cycle time becomes an integral multiple of the cycle counter in the control logic, and subsequent updates to the division ratio occur synchronously with the swallow counter cycle.

The double PLL configuration in Figure 2 shows the swept frequency PLL 20 described before the output 21 of which is an input carrying a reference frequency signal to a second PLL 30. PLL 30 is a conventional PLL without any frequency sweep comprising a phase comparator 31 which is connected to output 21 of PLL 20, a loop filter 32 and a VCO 33 whose output 35 is the output of the double PLL configuration. The output 35 is conventionally fed back via a divider 34 to the other in- put of the phase comparator.

With a microwave VCO in the second loop 30, the circuit block 34, shown as a divider in Figure 2, can be implemented by a suitable down-conversion mixer driven by a stable local oscil- lator.

Claims

1. Phase Locked Loop for frequency sweeping, comprising:

- a Voltage Controlled Oscillator (1) ; - a feedback loop comprising a phase comparator (5) for comparing a reference frequency signal (f_r) with a feedback signal, said feedback being supplied from an output of the Voltage Controlled Oscillator (1) via a counter arrangement (2, 4); - said counter arrangement (2, 4) performing a variable modulus count being controlled by corresponding modulus values;

- said modulus values being generated by a control device (8, 9, 11) comprising a source (8) for consecutive values, a conversion device (9) for converting said consecutive values to said modulus values for said first and second counters (41, 42) and a cycle counter (11) being controlled by a reference clock generator (12);

- said cycle counter (11) synchronously controlling said source (8) for consecutive values and said conversion device (9) .

2. Phase Locked Loop according to claim 1, c h a r a c t e r i s e d i n t h a t said counter arrangement (2, 4) comprising a dual modulus prescaler (2) and a swallow counter (4) with a first (41) and a second (42) counter, each performing a modulus count controlled by said modulus values .

3. Phase Locked Loop according to claim 1 or 2, c h a r a c t e r i s e d i n t h a t said reference clock generator (12) is connected to one input of said phase comparator (5) via a counter (13) performing a division by a factor r with r being an integer value.

4. Phase Locked Loop according to claim 3 , c h a r a c t e r i s e d i n t h a t said cycle counter (11) performs a division by k * r with k being an integer value.

I >

5. Phase Locked Loop according to any of claims 1 to 4, c h a r a c t e r i s e d by a modulus register (7) , the output of which is connected to an input of said counter arrangement (4) for providing said modulus values and coupled to the output of said conversion device (9) and which is controlled clockwise by said cycle counter (11) .

6. Phase Locked Loop according to claim 5, c h a r a c t e r i s e d b y a transfer register (10) connected between said conversion device (9) and said modulus register (7) .

7. Phase Locked Loop according to any of claims 1 to 6, c h a r a c t e r i s e d i n t h a t said source (8) for consecutive values generates consecutive integer values within a range (p, ... , q) with the range having one end value being the quotient of the lowest sweep frequency (fi) to be generated by the output signal of the Voltage Controlled Oscillator (1) and the reference frequency (f_r) and having another end value being the quotient of the highest sweep frequency (f₂) to be generated by the output I i signal of the VCO (1) and the reference frequency.

8. Phase Locked Loop according to any of claims 1 to 7 , c h a r a c t e r i s e d i n t h a t said counter arrangement (2, 4) comprises a prescaling counter (2) performing a selectable division by X or X + 1 connected to said first and second counters (41, 42) and an output of the Voltage Controlled Oscillator (1) , said first counter (41) having a modulus count value of N, said second counter (42) having a modulus count value of A, one of said consecutive values from said source (8) being s, said values N and A being generated according to the formula: X * N + A = s in response to an output signal from said cycle counter (11) .

9. Phase Locked Loop according to any of claims 1 to 8, c h a r a c t e r i s e d b y a loop filter (6) being connected between an output of said phase comparator (5) and a control input of said Voltage Controlled Oscillator (1), said loop filter (6) having a bandwidth which is a fraction of the frequency of said reference frequency signal (f_r) , preferably less than a fraction of 1/20 of the frequency of said reference frequency signal (fr).

10. Phase Locked Loop according to any of claims 1 to 9, c h a r a c t e r i s e d by a second Phase Locked Loop (30) with a reference signal input coupled to a phase comparator (31) , whereby said reference signal input of said second Phase Locked Loop (30) is connected to said output (21) of said Voltage Controlled Oscil- lator (1) .