CN107231151B - Broadband frequency sweeping source design circuit and design method - Google Patents
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Abstract
The invention discloses a broadband sweep frequency source design circuit and a design method, and belongs to the technical field of broadband synthetic sources. Under the control of an upper computer, the high-speed and stable logic control of the whole process is automatically realized in the FPGA in the scanning process of the frequency sweeping source, and the interaction with the upper computer is not needed in the frequency sweeping process, so that the frequency sweeping time is greatly reduced, and the frequency sweeping speed is optimized; the algorithm optimization of the FPGA internal operation process is provided under the condition of ensuring the high performance of output signals, so that FPGA hardware resources are saved to the maximum extent, and the hardware cost is reduced.
Description
Technical Field
The invention belongs to the technical field of broadband synthetic sources, and particularly relates to a broadband frequency sweeping source design circuit and a design method.
Background
At present, a frequency point is switched by an upper computer mainly based on an integrated phase-locked chip, firstly, registers of the integrated phase-locked chip are initialized, then, the frequency point switching is realized by the number of specific registers according to different functions, and the mode can be seen.
In the design of the broadband synthetic source at the present stage, the requirements on the volume, the frequency range, the phase noise, the spurious signal, the power stability and the frequency modulation time of the synthetic source are higher and higher, meanwhile, aiming at different applications, on the premise of pursuing low cost, the demand side is more and more diversified, and the current high-frequency broadband synthetic source circuit is mainly obtained through two schemes:
the first scheme is as follows: the broadband synthesis source circuit is composed of discrete components, wherein the discrete components mainly refer to components for composing a synthesis phase-locked loop, if the phase detector and the VCO are independent components and are connected by a printed board, the circuit volume occupied by the method is large, but the control is simple, the method is mainly applied to nesting of multiple phase-locked loops to form a broadband synthesis source circuit with high phase noise index, in this case, the control of the circuit becomes very complex due to the combined control of multiple loops, and this scheme is commonly used in the design of broadband local oscillation module in high-end analog source generation and signal analysis instruments, however, in a simple single-loop phase-locked circuit, due to the constraints of cost, VCO bandwidth and circuit size, meanwhile, the final output signal index has no advantage and is gradually replaced by a broadband synthetic source scheme based on integrated phase-locked control.
The second scheme is as follows: the broadband synthesis source circuit based on the integrated phase-locked chip integrates most of single-loop phase-locked circuits such as a reference frequency divider, a phase discriminator, a charge pump, a broadband VCO (voltage controlled oscillator), a feedback frequency divider and the like in a phase-locked loop, has high integration level, increases an integer frequency divider and a frequency multiplier at the output end of the VCO, further widens the frequency band coverage range of the chip, only needs to add a peripheral power supply bias circuit and a loop filter in use, has small occupied space, high integration level, low cost and low power consumption, can meet the requirements of most of the communication and radio frequency fields by outputting signal phase noise indexes, and is commonly used in a handheld low-end signal generation and analysis instrument; however, the integrated phase-locked chip in the scheme has multiple functions, needs multiple control register bits, is complex to control, generally needs an upper computer to perform real-time operation to complete frequency point switching of a broadband frequency sweeping source, and the frequency point switching time of the mode is kept at the ms level, so that the integral frequency sweeping speed is relatively low.
The prior art mainly has the following three defects:
first, the broadband synthetic source based on the discrete phase-locked circuit occupies a large volume, consumes a large amount of power, and has a high cost.
Secondly, compared with an integrated phase-locked chip, the broadband synthetic source single-loop scheme based on the discrete phase-locked circuit has no advantages in output signal phase noise indexes.
And thirdly, a broadband synthetic source scheme based on an integrated phase-locking scheme needs to use an upper computer to perform complex register control at present, and the whole frequency sweeping process is long in time.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a broadband frequency sweeping source design circuit and a design method, which are reasonable in design, overcome the defects of the prior art and have good effects.
In order to achieve the purpose, the invention adopts the following technical scheme:
a broadband sweep frequency source design circuit comprises a main controller, a logic operation unit, an address decoding data cache unit, an RAM storage unit, a logic operation unit, a data sending unit, an interrupt processing unit, an integrated phase-locked circuit, a segmented filter circuit, a power amplification circuit and an amplitude stabilizing circuit; the main controller, the logic operation unit, the RAM storage unit, the logic operation unit, the data transmission unit, the integrated phase-locked circuit, the segmented filter circuit, the power amplification circuit and the amplitude stabilizing circuit are sequentially connected through a line, the address decoding data cache unit is respectively connected with the main controller and the RAM storage unit through a line, and the interrupt processing unit is respectively connected with the RAM storage unit and the logic operation unit through a line;
a master controller configured for logical timing control of the entire sweep source;
the logical operation unit is configured to complete the logical operation of the frequency division ratio N.F corresponding to the output frequency point;
the address decoding data caching unit is configured to finish address storage of the RAM storage unit;
a RAM storage unit configured to store a frequency dividing ratio N.F corresponding to the swept source output frequency point;
the logic control unit is configured to complete RAM data calling and the accumulative calculation of the RAM address;
the data transmission unit is configured to convert the parallel data transmitted by the logic control unit into serial data for transmission;
the interrupt processing unit is configured to accumulate the counting pulse of the main controller and then generate an interrupt signal according to the command of the upper computer to control the logic control unit;
an integrated phase-locked circuit configured to perform a frequency synthesized output of the swept-frequency source;
a segmented filtering circuit configured to segment filter the output frequency signal;
a power amplification circuit configured to power amplify an output frequency;
the amplitude stabilizing circuit is configured to stabilize the power of the output frequency and guarantee the frequency stability of the output power;
in addition, the invention also provides a design method of the broadband sweep source, which adopts the broadband sweep source design circuit and comprises the following steps:
step 1: in each scanning stage, the main controller sequentially sends initial frequency, stepping frequency and stepping number parameters to the logic operation unit and sends first address data of the RAM storage unit to the address decoding data cache unit;
step 2: the logic operation unit carries out self-calculation on N.F corresponding to each frequency point on the premise of ensuring the fixed phase discrimination frequency according to the control mode of the integrated phase-locked circuit by the initial frequency, the stepping frequency and the stepping number, the main controller inputs the initial address of the RAM unit into the address decoding data cache unit, the accumulated calculation of the RAM address is completed in the logic control unit through an accumulator, the RAM address after the accumulated calculation corresponds to N.F data obtained in the logic operation unit one by one to store RAM data, and thus, under the logic control of the main controller, the data loading of the partial frequency ratio N.F in the RAM storage unit in the whole frequency sweeping process is completed;
and step 3: after the data loading is finished, the main controller starts to send synchronous trigger pulses to the interrupt processing unit and the logic operation unit, the accumulation of read addresses in the RAM storage unit is finished in the interrupt processing unit through pulse accumulation counting, the calling of data in the RAM storage unit and the accumulation of frequency stepping numbers are finished through an accumulator and a data calling unit in the logic operation unit, wherein one-time data calling is finished, and N.F control words are sent into the integrated phase-locked circuit by matching with SPI data conversion in the data sending unit;
and 4, step 4: after the data are sent to the integrated phase-locked circuit by the data sending unit, the data sequentially pass through a segmented filter circuit, a power amplifying circuit and an amplitude stabilizing circuit at the rear end, and finally, the switching of frequency points is completed;
and 5: repeating the steps 3-4 under the control of the synchronous trigger pulse, finishing the step number accumulation by an accumulation clock, generating an interrupt signal under the next synchronous trigger pulse after the step number is reached, automatically returning the read address of the RAM storage unit to the initial address of the RAM storage unit, and starting the repeated scanning process;
step 6: the main controller completes the switching of the frequency sweeping state by resetting the initial frequency, the stepping frequency and the stepping number of the logic operation unit.
Preferably, the N.F is mainly composed of an integer frequency dividing ratio NINTAnd fractional division ratio NFRACTwo parts are formed.
Preferably, in step 2, N.F corresponding to each frequency point is self-calculated according to formula (1);
wherein N isINTIs an integer frequency division ratio; n is a radical ofFRACA fractional division ratio; fVCOThe value range is 1500 MHz-3000 MHz; n is a radical ofINTBy FVCOThe integer is obtained by dividing 50; n is a radical ofFRACSolving by a formula (2);
at completion FVCO50MHz 50 × 106After Hz remainder calculation, 2 is completed by left shift by 17 bits17Multiplication, by performing 8 divide-by-5 operations to complete NFRACCalculation, wherein in the division operation, N is not affectedFRACIn the case of a valid bit, the pair N is requiredFRACAnd (4) carrying out real-time digit optimization on the values.
Preferably, for NFRACThe specific optimization steps for real-time digit optimization by value taking are as follows:
step 1: n is a radical ofFRAC1 st removal of 5, NFRACRight shift 2 bit, house 2 bit;
step 2: n is a radical ofFRAC2 nd removal of 5, NFRACRight shift 2 bit, house 2 bit;
and step 3: n is a radical ofFRAC3 rd time by 5, NFRACRight shift 2 bit, house 2 bit;
and 4, step 4: n is a radical ofFRAC4 th removal of 5, NFRACRight shift 3 bits, and house 3 bits;
and 5: n is a radical ofFRAC5 th time by 5, NFRACRight shift 2 bit, house 2 bit;
step 6: n is a radical ofFRAC6 th time of removing 5, NFRACRight shift 2 bit, house 2 bit;
and 7: n is a radical ofFRAC7 th time by 5, NFRACRight shift 3 bits, and house 3 bits;
and 8: n is a radical ofFRAC8 th time by 5, NFRACMove 2 bit to the right, cut 2 bit.
The invention has the following beneficial technical effects:
(1) under the control of the upper computer, the high-speed and stable logic control in the whole process is automatically realized in the FPGA in the scanning process of the frequency sweeping source, and the FPGA does not need to interact with the upper computer in the frequency sweeping process, so that the frequency sweeping time is greatly reduced, and the frequency sweeping speed is optimized.
(2) The invention provides algorithm optimization of an internal operation process of the FPGA under the condition of ensuring high performance of output signals, saves FPGA hardware resources to the maximum extent and reduces hardware cost.
Drawings
FIG. 1 is a schematic block diagram of the method of the present invention.
Wherein, 1-a logical operation unit; 2-address decoding data buffer unit; a 3-RAM memory unit; 4-a logical operation unit; 5-a number delivery unit; 6-an interrupt handling unit; 7-an integrated phase-locked circuit; 8-a segmented filter circuit; 9-a power amplification circuit; 10-amplitude stabilizing circuit.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
the invention aims to make up the defects of the prior art, designs a miniaturized broadband high-speed frequency sweeping source circuit based on a programmable logic controller, and the schematic block diagram of the scheme is shown in figure 1, and the scheme mainly comprises a logic operation unit 1, an address decoding data cache unit 2, an RAM (random access memory) storage unit 3, a logic operation unit 4, a data transmission unit 5, an interrupt processing unit 6, an integrated phase-locked circuit 7, a segmented filter circuit 8, a power amplification circuit 9 and an amplitude stabilizing circuit 10. The whole broadband sweep source control is completed through an additional reference signal and a main controller. The specific control process is as follows:
(1) in each scanning stage, the main controller sequentially sends initial frequency, stepping frequency and stepping number parameters to the logic operation unit 1 and sends first address data of the RAM to the address decoding data cache unit 2;
(2) the logic operation unit 1 performs self-calculation on N.F corresponding to each frequency point on the premise of ensuring that the phase discrimination frequency is fixed according to the control mode of the integrated phase-locked circuit 7 by the initial frequency, the stepping frequency and the stepping number, and sequentially completes storage of N.F obtained in the logic operation unit 1 by the accumulated calculation of the address of the RAM storage unit 3 in the interrupt processing unit 6 under the control of the first address of the RAM storage unit 3 of the main controller, so as to complete loading of the address and data in the RAM storage unit 3 in the frequency sweeping process;
(3) after the data loading is finished, the main controller starts to send synchronous trigger pulses to the interrupt processing unit 6 and the logic operation unit 4, the accumulation of read addresses in the RAM storage unit 3 is finished in the interrupt processing unit 6 through pulse accumulation counting, the calling of data in the RAM storage unit 3 and the accumulation of the frequency stepping number are finished through an accumulation/subtraction device and a data calling unit in the logic operation unit 4, wherein one-time data calling is finished, and N.F control words are sent to the integrated phase-locked circuit 7 by matching with SPI data conversion in the data sending unit 5;
(4) after the data is sent to the integrated phase-locked circuit 7 by the data sending unit 5, the data passes through the segmented filter circuit 8, the power amplifying circuit 9 and the amplitude stabilizing circuit 10 at the rear end in sequence, and finally, the switching of frequency points is completed.
(5) And (3) repeating the steps (3) to (4) under the control of the synchronous trigger pulse, finishing the step number accumulation by an accumulation clock, generating an interrupt signal under the next synchronous trigger pulse after the step number is reached, automatically returning the read address of the RAM storage unit 3 to the initial address of the RAM storage unit 3, and starting the repeated scanning process.
(6) The main controller performs the setting of the initial frequency, the stepping frequency and the stepping number on the logic operation unit 1 again to complete the switching of the frequency sweeping state.
The logic operation unit mainly completes self-calculation of N.F frequency division ratio, wherein N.F is mainly composed of two parts, namely an integer frequency division ratio NINTAnd fractional division ratio NFRAC(ii) a The integrated phase-locked circuit control in the invention is mainly based on HMC820, HMC840, HMC830, HMC833 and HMC834 series chips of ADI/Hittite company, the control mode is universal, the invention selects the HMC833 chip to output based on VCO with 1500 MHz-3000 MHz fundamental wave section, the rear end finishes the final output of 25 MHz-6000 MHz wide frequency band by 2 times of frequency multiplication and 1-62 times of integer frequency division, wherein the frequency stepping is mainly finished by changing N.F frequency division ratio. And N.F is calculated by the following formula:
wherein N isINTBy FVCOThe method is to divide the decimal by NFRACBecause the HMC series chip is internally provided with the ∑ - △ modulation frequency divider with 24 bits, the logic operation unit 1 needs to perform calculation on N in the frequency sweep source according to the minimum 6Hz stepping precision (based on 50MHz phase detection frequency) of the frequency sweep sourceFRACAlgorithm is optimized, and
by NFRACCan be calculated byIt is shown that, in the operation unit of the programmable logic controller FPGA, the multiplication and division operation occupies a large amount of logic resources, and if algorithm optimization is not performed, the hardware cost is directly increased, and F is completed hereVCO50MHz 50 × 106After Hz remainder calculation, 2 is completed by left shift by 17 bits17Multiplication, by performing 8 divide-by-5 operations to complete NFRACCalculating, in a division operation, without affecting NFRACIn the case of a valid bit, the pair N is requiredFRACThe real-time digit optimization is performed on the values to reduce the occupation of logic resources in the operation process as much as possible, and the digit optimization in the specific division process is shown in the following table 1.
TABLE 1NFRACInternal operation specific optimization algorithm
As can be seen from Table 1, by every division by 5, N is obtained at the same timeFRACPerforming different right shift rounding on the guaranteed NFRACIn the case of valid bits, N can be maximized in the case of optimizing the number of bits as much as possibleFRACThe 18 bits are optimized in the process operation, the occupation amount of logic resources in the FPGA is greatly reduced, and the hardware cost of the FPGA in the model selection is reduced.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (5)
1. A broadband sweep source design circuit is characterized in that: the device comprises a main controller, a logic operation unit, an address decoding data cache unit, an RAM storage unit, a logic operation unit, a data transmission unit, an interrupt processing unit, an integrated phase-locked circuit, a segmented filter circuit, a power amplification circuit and an amplitude stabilizing circuit; the main controller, the logic operation unit, the RAM storage unit, the logic operation unit, the data transmission unit, the integrated phase-locked circuit, the segmented filter circuit, the power amplification circuit and the amplitude stabilizing circuit are sequentially connected through a line, the address decoding data cache unit is respectively connected with the main controller and the RAM storage unit through a line, and the interrupt processing unit is respectively connected with the RAM storage unit and the logic operation unit through a line;
a master controller configured for logical timing control of the entire sweep source;
the logical operation unit is configured to complete the logical operation of the frequency division ratio N.F corresponding to the output frequency point;
the address decoding data caching unit is configured to finish address storage of the RAM storage unit;
a RAM storage unit configured to store a frequency dividing ratio N.F corresponding to the swept source output frequency point;
the logic control unit is configured to complete RAM data calling and the accumulative calculation of the RAM address;
the data transmission unit is configured to convert the parallel data transmitted by the logic control unit into serial data for transmission;
the interrupt processing unit is configured to accumulate the counting pulse of the main controller and then generate an interrupt signal according to the command of the upper computer to control the logic control unit;
an integrated phase-locked circuit configured to perform a frequency synthesized output of the swept-frequency source;
a segmented filtering circuit configured to segment filter the output frequency signal;
a power amplification circuit configured to power amplify an output frequency;
and the amplitude stabilizing circuit is configured to stabilize the power of the output frequency and guarantee the frequency stability of the output power.
2. A design method of a broadband sweep source is characterized by comprising the following steps: a broadband swept source design circuit as claimed in claim 1, comprising the steps of:
step 1: in each scanning stage, the main controller sequentially sends initial frequency, stepping frequency and stepping number parameters to the logic operation unit and sends first address data of the RAM storage unit to the address decoding data cache unit;
step 2: the logic operation unit carries out self-calculation on N.F corresponding to each frequency point on the premise of ensuring the fixed phase discrimination frequency according to the control mode of the integrated phase-locked circuit by the initial frequency, the stepping frequency and the stepping number, the main controller inputs the initial address of the RAM unit into the address decoding data cache unit, the accumulated calculation of the RAM address is completed in the logic control unit through an accumulator, the RAM address after the accumulated calculation corresponds to N.F data obtained in the logic operation unit one by one to store RAM data, and thus, under the logic control of the main controller, the data loading of the partial frequency ratio N.F in the RAM storage unit in the whole frequency sweeping process is completed;
and step 3: after the data loading is finished, the main controller starts to send synchronous trigger pulses to the interrupt processing unit and the logic operation unit, the accumulation of read addresses in the RAM storage unit is finished in the interrupt processing unit through pulse accumulation counting, the calling of data in the RAM storage unit and the accumulation of frequency stepping numbers are finished through an accumulator and a data calling unit in the logic operation unit, wherein one-time data calling is finished, and N.F control words are sent into the integrated phase-locked circuit by matching with SPI data conversion in the data sending unit;
and 4, step 4: after the data are sent to the integrated phase-locked circuit by the data sending unit, the data sequentially pass through a segmented filter circuit, a power amplifying circuit and an amplitude stabilizing circuit at the rear end, and finally, the switching of frequency points is completed;
and 5: repeating the steps 3-4 under the control of the synchronous trigger pulse, finishing the step number accumulation by an accumulation clock, generating an interrupt signal under the next synchronous trigger pulse after the step number is reached, automatically returning the read address of the RAM storage unit to the initial address of the RAM storage unit, and starting the repeated scanning process;
step 6: the main controller completes the switching of the frequency sweeping state by resetting the initial frequency, the stepping frequency and the stepping number of the logic operation unit.
3. A method for designing a broadband swept frequency source as defined by claim 2Characterized in that: N.F is mainly composed of integer frequency dividing ratio NINTAnd fractional division ratio NFRACTwo parts are formed.
4. A method for designing a broadband swept source as claimed in claim 2, wherein: in step 2, N.F corresponding to each frequency point is self-calculated according to the formula (1);
wherein N isINTIs an integer frequency division ratio; n is a radical ofFRACA fractional division ratio; fVCOThe value range is 1500 MHz-3000 MHz; n is a radical ofINTBy FVCOThe integer is obtained by dividing 50; n is a radical ofFRACSolving by a formula (2);
at completion FVCO50MHz 50 × 106After Hz remainder calculation, 2 is completed by left shift by 17 bits17Multiplication, by performing 8 divide-by-5 operations to complete NFRACCalculation, wherein in the division operation, N is not affectedFRACIn the case of a valid bit, the pair N is requiredFRACAnd (4) carrying out real-time digit optimization on the values.
5. A broadband swept source design method as claimed in claim 4, wherein: to NFRACThe specific optimization steps for real-time digit optimization by value taking are as follows:
step 1: n is a radical ofFRAC1 st removal of 5, NFRACRight shift 2 bit, house 2 bit;
step 2: n is a radical ofFRAC2 nd removal of 5, NFRACRight shift 2 bit, house 2 bit;
and step 3: n is a radical ofFRAC3 rd time by 5, NFRACRight shift 2 bit, house 2 bit;
and 4, step 4: n is a radical ofFRAC4 th removal of 5, NFRACRight shift 3 bits, and house 3 bits;
and 5: n is a radical ofFRAC5 th time by 5, NFRACRight shift 2 bit, house 2 bit;
step 6: n is a radical ofFRAC6 th time of removing 5, NFRACRight shift 2 bit, house 2 bit;
and 7: n is a radical ofFRAC7 th time by 5, NFRACRight shift 3 bits, and house 3 bits;
and 8: n is a radical ofFRAC8 th time by 5, NFRACMove 2 bit to the right, cut 2 bit.
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