CN115333484A

CN115333484A - Frequency multiplication frequency sweeping method

Info

Publication number: CN115333484A
Application number: CN202211007299.4A
Authority: CN
Inventors: 谢丹
Original assignee: Chengdu Sicore Semiconductor Corp Ltd
Current assignee: Chengdu Sicore Semiconductor Corp Ltd
Priority date: 2022-08-22
Filing date: 2022-08-22
Publication date: 2022-11-11
Anticipated expiration: 2042-08-22
Also published as: CN115333484B

Abstract

The invention discloses a frequency multiplication frequency sweeping method, which relates to the field of frequency modulation and is applied to a frequency sweeping device, wherein the frequency sweeping device comprises: the frequency sweep module, the decimal modulator module, the frequency divider and the phase-locked loop; the clocks of the frequency sweep module and the decimal modulator module are respectively controlled by a phase discrimination clock and a frequency division clock of a phase-locked loop, the phase-locked loop outputs a locking indication signal to the frequency sweep module, an integer frequency division ratio and a decimal frequency division ratio output by the frequency sweep module are input as a decimal modulator module, and the decimal modulator module outputs the frequency division ratio to the phase-locked loop; the method comprises the following steps: obtaining a starting frequency dividing ratio and a stopping frequency dividing ratio based on the control signal and inputting the starting frequency dividing ratio and the stopping frequency dividing ratio into the frequency sweeping module, and outputting the frequency dividing ratio to a frequency dividing ratio switching signal of the frequency divider controlled by the frequency sweeping module; setting a plurality of working states of the frequency sweeping device; the frequency sweeping device is controlled to switch in a plurality of working states so that the frequency divider outputs a frequency sweeping signal of multiple octaves.

Description

Frequency multiplication frequency sweeping method

Technical Field

The invention relates to the field of frequency modulation, in particular to a frequency multiplication frequency sweeping method.

Background

Frequency-modulated continuous wave (FMCW) is widely applied to the fields of modern radars, unmanned aerial vehicles, automobile automatic driving and the like, compared with Doppler radars, the FMCW based Frequency modulation continuous wave has the advantages of high resolution, high sensitivity and more measurable information, the Frequency sweeping function is realized through a digital circuit in a mode of continuously controlling the Frequency dividing ratio of a delta-sigma fractional modulator, and the performance can be improved in a mode of controlling a PLL (phase locked loop) in a DDS (direct digital Frequency synthesis) mode. In practical engineering application, an output frequency divider can be connected behind the VCO, and the output frequency divider can realize frequency division of power of 2 (such as 1/2/4/8 \8230; equal frequency division ratio).

Disclosure of Invention

The invention aims to provide frequency sweep output of multiple octaves.

In order to achieve the above object, the present invention provides a frequency multiplication frequency sweeping method, which is applied to a frequency sweeping device, wherein the frequency sweeping device comprises: the frequency sweeping module, the delta-sigma decimal modulator module, the frequency divider and the phase-locked loop; clocks of the frequency sweeping module and the delta-sigma decimal modulator module are respectively controlled by a phase discrimination clock and a frequency division clock of the phase-locked loop, a locking indication signal LDT output by the phase-locked loop is connected with the input of the frequency sweeping module, an integer frequency division ratio and a decimal frequency division ratio output by the frequency sweeping module are used as the input of the delta-sigma decimal modulator module, and the delta-sigma decimal modulator module outputs the frequency division ratio to the phase-locked loop;

the method comprises the following steps:

obtaining a starting frequency dividing ratio and a stopping frequency dividing ratio based on the control signal and inputting the starting frequency dividing ratio and the stopping frequency dividing ratio into the frequency sweeping module, and outputting the frequency dividing ratio to a frequency dividing ratio switching signal of the frequency divider controlled by the frequency sweeping module;

setting a plurality of working states of the frequency sweeping device;

and controlling the frequency sweeping device to switch in a plurality of working states so that the frequency divider outputs a frequency sweeping signal with multiple octaves.

The working frequency of the frequency sweeping module is controlled by the phase discrimination frequency fref of the phase-locked loop, and the working frequency of the frequency sweeping module and the working frequency of the delta-sigma fractional modulator are ensured to be the same in frequency and have a fixed phase difference in a locked state (namely, two input clocks have the same frequency and have a fixed phase difference in the locked state). In the circuit, a clock clk _ swp represented as a sweep frequency module is connected with a phase detection clock clk _ ref of a phase-locked loop, and for convenience of description, the sweep frequency output is agreed to respond to the rising edge of the sweep frequency clock clk _ swp, that is, when the rising edge of the clk _ swp comes, the values of an integer frequency division ratio nint and a decimal frequency division ratio nfrac of the sweep frequency output are updated. The initial frequency dividing ratio odiv _ str and the final frequency dividing ratio odiv _ trm of an external control signal are input to the frequency sweeping module to be used as frequency doubling control of a frequency doubling algorithm of the indication frequency sweeping module, and after algorithm processing, the frequency sweeping module outputs a control word odiv _ cal to the power frequency divider of 2 to be used as a frequency dividing ratio switching signal for controlling the power frequency divider of 2. The power-power frequency divider of 2 outputs a frequency sweep signal of multiple octaves to the outside.

The frequency sweeping module realizes continuous change of frequency from high to low (or from low to high); the decimal modulation module realizes a decimal frequency division function, and the phase-locked loop realizes that the frequency of an output signal reflects the frequency of an input signal in proportion; the frequency divider implements a frequency division of the output frequency.

Preferably, the frequency sweeping device includes 8 operating states, which are respectively: the method comprises the following steps of initializing and locking a judging state S1, a frequency sweeping mode judging state S2, an uplink frequency sweeping state S3, a downlink frequency sweeping state S4, an initial unlocking processing state S5, an uplink unlocking processing state S6, a downlink unlocking processing state S7 and a termination state S8;

starting the sweep frequency to enter a state S1, performing phase-locked loop locking judgment after the configuration of initialization parameters is completed in the state S1, and switching to a state S5 if the phase-locked loop is unlocked;

in the state S5, switching back to the state S1 after the phase-locked loop is locked again, and in the state S1, switching to the state S2 if the phase-locked loop is locked;

performing frequency sweep mode judgment in a state S2, then performing frequency sweep direction judgment, switching from the state S2 to a state S3 if the frequency sweep is uplink frequency sweep, switching from the state S2 to a state S4 if the frequency sweep is downlink frequency sweep, and setting a frequency ratio hopping pointer;

performing uplink frequency sweeping control in the state S3, switching to the state S8 if the frequency sweeping frequency reaches a frequency dividing stopping ratio and the phase-locked loop is locked, and switching to the state S6 if the phase-locked loop is unlocked; performing phase-locked loop locking judgment in the uplink process in the state S6, and switching back to the state S3 if the phase-locked loop is locked;

performing downlink frequency sweeping control in the state S4, switching to the state S8 if the frequency sweeping frequency returns to the initial frequency dividing ratio and the phase-locked loop is locked, and switching to the state S7 if the phase-locked loop is unlocked;

in the state S8, the next sweep state is determined according to the sweep mode, and if the sweep is continuous sweep, the state S2 is switched, and if the sweep is triggered sweep, the state S1 is switched.

Preferably, the sweep frequency signal comprises a plurality of sweep frequency signal segments connected in sequence, the sweep frequency direction of each sweep frequency signal segment is any one of an uplink sweep frequency, a downlink sweep frequency and a parallel sweep frequency, and each sweep frequency signal segment corresponds to a corresponding sweep frequency duration.

Preferably, before the frequency sweeping, the method further includes marking the initial integer frequency division ratio and the initial fractional frequency division ratio of each frequency sweeping signal segment respectively to obtain marking information, and configuring condition information that the marking information needs to meet according to the frequency sweeping signals.

The frequency sweep signal is an upper sawtooth waveform frequency sweep signal, or the frequency sweep signal is a lower sawtooth waveform frequency sweep signal, or the frequency sweep signal is a triangular waveform frequency sweep signal, or the frequency sweep signal is a trapezoidal waveform frequency sweep signal.

Namely, the device can realize the frequency sweep of any waveform, and the specific realization mode is as follows:

in order to realize the upper sawtooth wave type frequency sweep signal, the upper sawtooth wave can be characterized as an upper traveling frequency band, the method is correspondingly designed, and particularly, when the frequency sweep signal is the upper sawtooth wave type frequency sweep signal, the method also comprises the following steps before frequency sweep:

configure nint _ ramp0, nfrac _ ramp0, step _ ramp0, nint _ ramp1, and nfrac _ ramp1, which satisfy at least one of the following two conditions:

condition 1: nint _ ramp0 < nint _ ramp1;

condition 2: nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1;

the initial integer frequency division ratio of the first section of the sweep signal segment is marked as nint _ ramp0, the initial decimal frequency division ratio of the first section of the sweep signal segment is marked as nfrac _ ramp0, and the sweep step of the first section of the sweep signal segment is marked as step _ ramp0; the starting integer divide ratio for the second segment of the swept signal is labeled nint _ ramp1, the starting fractional divide ratio for the second segment of the swept signal is labeled nfrac _ ramp1, and the sweep step for the second segment of the swept signal is labeled step _ ramp1.

In order to realize the sawtooth waveform frequency sweeping signal, the sawtooth waveform can be characterized as a section of descending frequency sweeping band, the method is correspondingly designed, and particularly, when the frequency sweeping signal is the sawtooth waveform frequency sweeping signal, the method also comprises the following steps before frequency sweeping:

configuring nint _ ramp0, nfrac _ ramp0, step _ ramp0, nint _ ramp1 and nfrac _ ramp1, the configuration satisfying at least one of the following two conditions:

condition 3: nint _ ramp0 > nint _ ramp1;

condition 4: nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 > nfrac _ ramp1;

the initial integer frequency division ratio of the first section of the sweep signal segment is marked as nint _ ramp0, the initial decimal frequency division ratio of the first section of the sweep signal segment is marked as nfrac _ ramp0, and the sweep step of the first section of the sweep signal segment is marked as step _ ramp0; the starting integer frequency division ratio of the second segment of the swept frequency signal is labeled nint _ ramp1, the starting fractional frequency division ratio of the second segment of the swept frequency signal is labeled nfrac _ ramp1, and the sweep step of the second segment of the swept frequency signal is labeled step _ ramp1.

In order to realize the triangular wave type sweep frequency signal, the triangular wave can be characterized in that an upstream sweep frequency section is connected with a downstream sweep frequency section, the method is correspondingly designed, and specifically, when the sweep frequency signal is the triangular wave type sweep frequency signal, the method also comprises the following steps before the sweep frequency:

configuring nint _ ramp0, nfrac _ ramp0, step _ ramp0, nint _ ramp1, nfrac _ ramp1, step _ ramp1, nint _ ramp2 and nfrac _ ramp2, wherein at least one of the following four conditions is satisfied:

condition 5: nint _ ramp0 < nint _ ramp1 and nint _ ramp1 > nint _ ramp2;

condition 6: nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1 and nint _ ramp1 > nint _ ramp2;

condition 7: nint _ ramp0 < nint _ ramp1 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1 > nfrac _ ramp2;

condition 8: nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1 > nfrac _ ramp2;

the initial integer frequency division ratio of the first section of the sweep signal segment is marked as nint _ ramp0, the initial decimal frequency division ratio of the first section of the sweep signal segment is marked as nfrac _ ramp0, and the sweep step of the first section of the sweep signal segment is marked as step _ ramp0; the start integer frequency division ratio of the second section of the frequency scanning signal segment is marked as nint _ ramp1, the start decimal frequency division ratio of the second section of the frequency scanning signal segment is marked as nfrac _ ramp1, the frequency scanning stepping of the second section of the frequency scanning signal segment is marked as step _ ramp1, the start integer frequency division ratio of the third section of the frequency scanning signal segment is marked as nint _ ramp2, the start decimal frequency division ratio of the third section of the frequency scanning signal segment is marked as nfrac _ ramp2, and the frequency scanning stepping of the third section of the frequency scanning signal segment is marked as step _ ramp2.

In order to realize the trapezoidal wave type sweep frequency signal, the trapezoidal wave can be characterized in that an ascending sweep frequency section is connected with a parallel sweep frequency section and then connected with a descending sweep frequency section, the method is correspondingly designed, and specifically, when the sweep frequency signal is the trapezoidal wave type sweep frequency signal, the method further comprises the following steps before the sweep frequency:

configuring nint _ ramp0, nfrac _ ramp0, step _ ramp0, nint _ ramp1, nfrac _ ramp1, step _ ramp1, nint _ ramp2, nfrac _ ramp2, step _ ramp2, nint _ ramp3 and nfrac _ ramp3, wherein at least one of the following four conditions is met:

condition 9: nint _ ramp0 < nint _ ramp1 and nint _ ramp2 > nint _ ramp3 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1= nfrac _ ramp2;

condition 10: nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1 and nint _ ramp2 > nint _ ramp3 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1= nfrac _ ramp2;

condition 11: nint _ ramp0 < nint _ ramp1 and nint _ ramp2= nint _ ramp3 and nfrac _ ramp2 > nfrac _ ramp3 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1= nfrac _ ramp2;

condition 12: nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1 and nint _ ramp2= nint _ ramp3 and nfrac _ ramp2 > nfrac _ ramp3 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1= nfrac _ ramp2;

the initial integer frequency division ratio of the first section of the sweep signal segment is marked as nint _ ramp0, the initial decimal frequency division ratio of the first section of the sweep signal segment is marked as nfrac _ ramp0, and the sweep step of the first section of the sweep signal segment is marked as step _ ramp0; the starting integer frequency division ratio of the second section of the sweep signal segment is marked as nint _ ramp1, the starting decimal frequency division ratio of the second section of the sweep signal segment is marked as nfrac _ ramp1, the sweep step of the second section of the sweep signal segment is marked as step _ ramp1, the starting integer frequency division ratio of the third section of the sweep signal segment is marked as nint _ ramp2, the starting decimal frequency division ratio of the third section of the sweep signal segment is marked as nfrac _ ramp2, the sweep step of the third section of the sweep signal segment is marked as step _ ramp2, the starting integer frequency division ratio of the fourth section of the sweep signal segment is marked as nint _ ramp3, the starting decimal frequency division ratio of the fourth section of the sweep signal segment is marked as nfrac _ ramp3, and the sweep step of the fourth section of the sweep signal segment is marked as step _ ramp3.

Preferably, the state S1 includes the following steps:

processing the input starting integer divide ratio nint _ str, starting fractional divide ratio nfrac _ str and starting divide ratio odiv _ str to obtain an expanded starting integer divide ratio nint _ str _ expand and an expanded starting fractional divide ratio nfrac _ str _ expand;

processing the input terminated integer division ratio nint _ trm, terminated fractional division ratio nfrac _ trm and terminated division ratio odiv _ trm to obtain a final integer division ratio nint _ trm _ expand and an expanded terminated fractional division ratio nfrac _ trm _ expand;

judging the current state of the phase-locked loop through a locking indication signal LDT output by the phase-locked loop, entering a state S2 if the phase-locked loop is in a locking state, switching from the state S1 to a state S5 if the phase-locked loop is in an unlocking state, entering a re-locking process, returning to the state S1 after locking is finished, and switching to the state S2.

Preferably, the following steps are included in the state S2:

judging a set frequency sweep mode, wherein the frequency sweep mode comprises continuous bidirectional frequency sweep, triggered bidirectional frequency sweep and triggered unidirectional frequency sweep, the continuous bidirectional frequency sweep is alternately carried out by uplink frequency sweep and downlink frequency sweep, the triggered bidirectional frequency sweep is carried out by controlling and starting the uplink frequency sweep and the downlink frequency sweep through an external trigger signal, the triggered unidirectional frequency sweep is carried out by controlling and starting the uplink frequency sweep through an external trigger signal, and an initial frequency point is returned after the uplink frequency sweep is finished;

setting the variation condition of the frequency dividing ratio of the frequency divider odiv in the frequency sweeping process;

for continuous bidirectional frequency sweeping and triggered bidirectional frequency sweeping, when uplink frequency sweeping is adopted, the state S2 is switched to the state S3, and when downlink frequency sweeping is adopted, the state S2 is switched to the state S4; for the triggered unidirectional frequency sweep, the state S2 is switched to the state S3.

Preferably, the following steps are included in the state S3:

the ascending of the frequency dividing ratio of the frequency dividing module is obtained by accumulating the temporary register nfrac _ tmp by stepping step so as to realize the ascending frequency dividing, and the values of the temporary register nint _ tmp and the temporary register nfrac _ tmp are updated once every time the rising edge of the clk _ swp clock comes;

judging whether to switch the states or not through a locking indication signal LDT output by the phase-locked loop, switching from the state S3 to the state S6 when the phase-locked loop loses the lock, and continuing to keep the state S3 if the phase-locked loop still keeps the lock;

whether the temporary registers nint _ tmp and nfrac _ tmp reach the end integer frequency division ratio and the end decimal frequency division ratio is judged, if so, the state S3 is switched to the state S8, and if not, the state S3 is kept.

Preferably, the following steps are included in the state S4:

the gradual reduction of the frequency dividing ratio of the frequency dividing module is obtained by decreasing the temporary register nfrac _ tmp by stepping step to realize downlink frequency dividing, and the values of nint _ tmp and nfrac _ tmp are updated once every time the rising edge of the clk _ swp clock comes;

judging whether to switch the states or not through a locking indication signal LDT output by the phase-locked loop, switching from the state S4 to the state S7 when the phase-locked loop loses the lock, and continuing to keep the state S4 if the phase-locked loop still keeps locking;

whether the temporary registers nint _ tmp and nfrac _ tmp reach the initial integer frequency division ratio and the initial fractional frequency division ratio of the first stage is judged, if so, the state S4 is switched to the state S8, and if so, the state S4 is kept continuously.

Preferably, the following steps are included in the state S6:

when the pointer odiv _ up =1, dividing the values of the temporary register nint _ tmp and the temporary register nfrac _ tmp by 2, respectively;

the timer is enabled to time from 0 by configuring the duration of the timer externally, and the state S6 is switched back to the state S3 after the timer is full;

in state S7 the following steps are included:

when the pointer odiv _ dw =1, dividing the values of the temporary register nint _ tmp and the temporary register nfrac _ tmp by 2, respectively;

the timer is timed from 0 by externally configuring the duration of the timer, and the state S7 is switched back to the state S4 after the timer expires.

Preferably, the frequency sweep signal is an upper sawtooth waveform frequency sweep signal, or the frequency sweep signal is a lower sawtooth waveform frequency sweep signal, or the frequency sweep signal is a triangular waveform frequency sweep signal, or the frequency sweep signal is a trapezoidal waveform frequency sweep signal.

One or more technical schemes provided by the invention at least have the following technical effects or advantages:

according to the invention, through reasonably setting each state, the working steps are orderly and logically decomposed, and the implementation efficiency of the frequency sweeping function is greatly improved;

the invention provides a frequency sweeping method of multiple octaves by adopting a shift algorithm, which is combined with a power frequency divider of 2, thereby greatly expanding the frequency sweeping range;

the abnormal processing means added in the invention can flexibly and effectively interrupt the lost lock in the frequency sweeping process, thereby solving the problems of the lost lock and other faults caused by signal loss and the like in practical application;

the continuous mode and the external trigger mode provided by the invention can meet the requirements of different application scenes.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention;

FIG. 1 is a schematic diagram of the principle of the method;

fig. 2 is a schematic diagram of state switching in the method.

Detailed Description

In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments of the present invention and features of the embodiments may be combined with each other without conflicting with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described and thus the scope of the present invention is not limited by the specific embodiments disclosed below.

Example one

Referring to fig. 1, fig. 1 is a schematic diagram of a frequency multiplication and frequency sweep method, which is a method for controlling a frequency sweep frequency dividing ratio by a shift algorithm to realize a frequency multiplication and frequency sweep function.

The embodiment of the invention is realized by the following technical scheme: the frequency-sweeping module for realizing multi-octave, the delta-sigma decimal modulator module, the phase-locked loop and the power frequency divider of 2. The algorithms of the first two modules are realized by synthesizing Hardware Description Language (HDL) (such as verilog Language) into a digital circuit, the integer frequency division ratio and the decimal frequency division ratio of the output of the frequency sweeping module are used as the input of a delta-sigma decimal modulator, and the power frequency divider of 2 can be realized by adopting a digital circuit or an analog circuit.

The working frequency of the frequency sweep module is controlled by the phase discrimination frequency fref of the phase-locked loop, and the working frequency of the frequency sweep module and the working frequency of the delta-sigma fractional modulator are ensured to be the same and have fixed phase difference in a locked state. In the circuit, a clock clk _ swp represented as a sweep frequency module is connected with a phase detection clock clk _ ref of a phase-locked loop, and for convenience of description, the sweep frequency output is agreed to respond to the rising edge of the sweep frequency clock clk _ swp, that is, when the rising edge of the clk _ swp comes, the values of an integer frequency division ratio nint and a decimal frequency division ratio nfrac of the sweep frequency output are updated. The initial frequency dividing ratio odiv _ str and the final frequency dividing ratio odiv _ trm of an external control signal are input to the frequency sweeping module to be used as frequency doubling control of a frequency doubling algorithm of the indication frequency sweeping module, and after algorithm processing, the frequency sweeping module outputs a control word odiv _ cal to the power frequency divider of 2 to be used as a frequency dividing ratio switching signal for controlling the power frequency divider of 2. The power-power frequency divider of 2 outputs a frequency sweep signal of multiple octaves to the outside.

In the present invention, it is set that odiv _ str > odiv _ trm, where odiv _ str corresponds to the maximum achievable division ratio of a power divider of 2 and odiv _ trm corresponds to the minimum achievable division ratio of a power divider of 2. Since the division ratios of the dividers are both powers of 2, the values of odiv _ str and odiv _ trm are both powers of 2.

The connection diagram of the frequency sweep module, the delta-sigma decimal modulator module and the power frequency divider of 2 is shown in figure 1. The clock of the frequency sweep module and the clock of the delta-sigma decimal modulator are respectively controlled by a phase discrimination clock and a frequency division clock of the phase-locked loop, on the other hand, a locking indication signal LDT output by the phase-locked loop is connected with the input of the frequency sweep module, the delta-sigma decimal modulator outputs a frequency division ratio to the phase-locked loop, the multi-octave algorithm of the frequency sweep module is controlled by an initial frequency division ratio and a final frequency division ratio which are input externally, and a variable frequency division ratio is output to the power frequency divider of 2.

For the single-frequency-pass frequency sweep module, variable integer division ratio nint and fractional division ratio nfrac are output, and the relation between the two signals and the output frequency fout is:

fout＝fref×nint.nfrac。

fref is the phase detection frequency of the phase-locked loop, nint represents an integer part, nfrac represents a fractional part, for example, 47 in 47.65 is nint,0.65 is nfrac, and nint.nfrac is accumulated or decreased according to a fixed sweep step, so that the output frequency fout is linear, and the FMCW is realized by the method. The range of single-frequency-pass sweep output is determined by the range of nint.nfrac (maximum value nint.nfrac @ max and minimum value nint.nfrac @ min), i.e. the range of fout is the maximum value fref × (nint.nfrac @ max) and the minimum value fref × (nint.nfrac @ min).

In the following, nfrac needs to be converted to binary by the following equation: decimal nfrac is multiplied by 2 p and then converted into binary nfrac. Wherein p is the number of bits of the delta-sigma fractional modulator.

For the multi-octave frequency sweep module, since the frequency division ratio of the power frequency divider of 2 can be controlled, and the odiv _ str corresponds to the maximum frequency division ratio achievable by the power frequency divider of 2, the minimum value of the frequency range fout of the achievable frequency sweep output is fref x (nint.nfrac @ min)/odiv _ str, and the odiv _ trm corresponds to the minimum frequency division ratio achievable by the power frequency divider of 2, so the maximum value of the frequency range fout of the achievable frequency sweep output is fref x (nint.nfrac @ max)/odiv _ trm. Compared with a single-frequency-range frequency sweep module, the output frequency range of the frequency sweep module adopting the multiple octaves is greatly increased (for example, the frequency division is set to 1 odiv _ trm), so that the range of practical application is expanded.

The frequency sweeping method of the multiple octaves applied by the power frequency divider combined with 2 provided by the invention comprises 8 states, including an initialization and locking judgment state (marked as S1), a frequency sweeping mode judgment state (marked as S2), an uplink frequency sweeping state (marked as S3), a downlink frequency sweeping state (marked as S4), an initial lock losing processing state (marked as S5), an uplink lock losing processing state (marked as S6), a downlink lock losing processing state (marked as S7) and a termination state (marked as S8), and the switching among the states is shown in figure 2.

The frequency sweeping directions comprise an uplink frequency sweeping direction and a downlink frequency sweeping direction. The ascending frequency sweeping, namely the initial frequency of the frequency sweeping is smaller than the final frequency, and the ascending frequency is represented as a slope on a relational graph which takes a time axis as a horizontal axis and takes a frequency axis as a vertical axis; the frequency sweep of the downlink, i.e. the initial frequency fstr of the frequency sweep, is greater than the end frequency ftrm, and is shown as a downward slope on a relational graph which takes a time axis as a horizontal axis and takes a frequency axis as a vertical axis.

The invention can realize the frequency sweep of any waveform, and the specific realization mode is as follows:

the arbitrary waveform frequency sweep is characterized by being formed by connecting multiple sections in sequence, the frequency sweep direction of each section can be any one of uplink frequency sweep, downlink frequency sweep and parallel frequency sweep, and each section can correspond to different frequency sweep duration; for adjacent sweep frequency sections in the same direction, if the sweep frequency time is different, the sweep frequency sections can be considered as different sections; for convenience of explanation, the embodiment of the present invention uses 3 segments as an example, and the number of segments of any waveform can be expanded in practical application. The sawtooth wave is divided into an upper sawtooth wave and a lower sawtooth wave, and the upper sawtooth wave can be characterized as an upper line scanning frequency band; the down sawtooth waveform can be characterized as a down sweep; the triangular wave can be characterized in that an ascending sweep frequency section is connected with a descending sweep frequency section; the trapezoidal wave can be characterized as an upward swept frequency band connected to a parallel swept frequency band and then to a downward swept frequency band.

In order to scan any waveform, it is necessary to mark each sweep frequency signal segment according to actual needs, where the number of the sweep frequency signal segments may be designed according to the needs of the actual sweep frequency signal, and this embodiment only exemplifies the 8 th segment, but is not limited to 8 segments, and only provides a way that can be implemented.

For convenience of illustration, the first segment of the present invention has a starting integer divide ratio labeled nint _ ramp0, a starting fractional divide ratio labeled nfrac _ ramp0, and a sweep step labeled step _ ramp0; the starting integer frequency dividing ratio of the second stage, namely the ending integer frequency dividing ratio of the first stage, is marked as nint _ ramp1, the starting decimal frequency dividing ratio of the second stage, namely the ending decimal frequency dividing ratio of the first stage, is marked as nfrac _ ramp1, and the frequency sweeping stepping of the second stage is marked as step _ ramp1; the initial integer frequency dividing ratio of the third section, namely the ending integer frequency dividing ratio of the second section, is marked as nint _ ramp2, the initial decimal frequency dividing ratio of the third section, namely the ending decimal frequency dividing ratio of the second section, is marked as nfrac _ ramp2, and the frequency sweeping stepping of the third section is marked as step _ ramp2; the starting integer frequency dividing ratio of the fourth section, namely the ending integer frequency dividing ratio of the third section, is marked as nint _ ramp3, the starting decimal frequency dividing ratio of the fourth section, namely the ending decimal frequency dividing ratio of the third section, is marked as nfrac _ ramp3, and the frequency sweeping stepping of the fourth section is marked as step _ ramp3; the starting integer frequency dividing ratio of the fifth section, namely the ending integer frequency dividing ratio of the fourth section, is marked as nint _ ramp4, the starting decimal frequency dividing ratio of the fifth section, namely the ending decimal frequency dividing ratio of the fourth section, is marked as nfrac _ ramp4, and the frequency sweeping stepping of the fifth section is marked as step _ ramp4; the starting integer frequency dividing ratio of the sixth section, namely the ending integer frequency dividing ratio of the fifth section, is marked as nint _ ramp5, the starting decimal frequency dividing ratio of the sixth section, namely the ending decimal frequency dividing ratio of the fifth section, is marked as nfrac _ ramp5, and the frequency sweeping stepping of the sixth section is marked as step _ ramp5; the starting integer frequency division ratio of the seventh segment, namely the ending integer frequency division ratio of the sixth segment, is marked as nint _ ramp6, the starting decimal frequency division ratio of the seventh segment, namely the ending decimal frequency division ratio of the sixth segment, is marked as nfrac _ ramp6, and the frequency sweeping stepping of the seventh segment is marked as step _ ramp6; the starting integer frequency division ratio of the eighth segment, i.e. the ending integer frequency division ratio of the seventh segment, is labeled nint _ ramp7, the starting fractional frequency division ratio of the eighth segment, i.e. the ending fractional frequency division ratio of the seventh segment, is labeled nfrac _ ramp7, and the frequency sweep step of the eighth segment is labeled step _ ramp7; the ending integer divide ratio for the eighth stage is labeled nint _ ramp8 and the ending fractional divide ratio for the eighth stage is labeled nfrac _ ramp8. The frequency dividing ratio and the stepping need to be set according to the application waveform, and the number of segments is selected through the gate, so as to shield the invalid sweep frequency segment.

In the upper sawtooth wave frequency sweeping, nint _ ramp0, nfrac _ ramp0, step _ ramp0, nint _ ramp1 and nfrac _ ramp1 need to be configured according to design requirements, other frequency division ratios and stepping need to be shielded, and at least one of the following two conditions needs to be met:

1)nint_ramp0＜nint_ramp1；

2) nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1

In the lower sawtooth wave frequency sweeping, nint _ ramp0, nfrac _ ramp0, step _ ramp0, nint _ ramp1 and nfrac _ ramp1 need to be configured according to design requirements, other frequency dividing ratios and stepping needs to be shielded, and at least one of the following two conditions needs to be met:

1)nint_ramp0＞nint_ramp1；

2) nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 > nfrac _ ramp1;

in the triangular wave frequency sweeping, nint _ ramp0, nfrac _ ramp0, step _ ramp0, nint _ ramp1, nfrac _ ramp1, step _ ramp1, nint _ ramp2 and nfrac _ ramp2 need to be configured according to design requirements, other frequency division ratios and stepping need to be shielded, and at least one of the following four conditions needs to be met:

1) nint _ ramp0 < nint _ ramp1 and nint _ ramp1 > nint _ ramp2;

2) nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1 and nint _ ramp1 > -

nint_ramp2；

3) nint _ ramp0 < nint _ ramp1 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1 > -

nfrac_ramp2；

4) nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1 and nint _ ramp1=

nint _ ramp2 and nfrac _ ramp1 > nfrac _ ramp2;

for the trapezoidal wave frequency sweeping, nint _ ramp0, nfrac _ ramp0, step _ ramp0, nint _ ramp1, nfrac _ ramp1, step _ ramp1, nint _ ramp2, nfrac _ ramp2, step _ ramp2, nint _ ramp3 and nfrac _ ramp3 need to be configured according to design requirements, and other frequency division ratios and steps need to be shielded, and at least one of the following four conditions needs to be met:

1) nint _ ramp0 < nint _ ramp1 and nint _ ramp2 > nint _ ramp3 and nint _ ramp1=

nint _ ramp2 and nfrac _ ramp1= nfrac _ ramp2;

2) nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1 and nint _ ramp2 > -

nint _ ramp3 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1= nfrac _ ramp2;

3) nint _ ramp0 < nint _ ramp1 and nint _ ramp2= nint _ ramp3 and nfrac _ ramp2 > -

nfrac _ ramp3 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1= nfrac _ ramp2;

4) nint _ ramp0= nint _ ramp1 and nfrac _ ramp0 < nfrac _ ramp1 and nint _ ramp2=

nint _ ramp3 and nfrac _ ramp2 > nfrac _ ramp3 and nint _ ramp1= nint _ ramp2 and nfrac _ ramp1

＝nfrac_ramp2；

The sweep duration is the elapsed time t from the start to the end frequency, and the slope k of the sweep can be obtained by the following formula:

k＝(ftrm-fstr)/t

the relationship between the sweep step and the sweep duration t is as follows:

step＝t×fref

the expression represents that the sweep frequency duration is in direct proportion to the sweep frequency stepping and the phase discrimination frequency.

For ease of description, the power of 2 divider is defined as odiv in the following discussion.

The S1 state comprises the following steps:

a first step of performing a shift algorithm operation on the input starting integer frequency division ratio nint _ str, starting fractional frequency division ratio nfrac _ str and starting odiv frequency division ratio odiv _ str to process into an extended starting integer frequency division ratio nint _ str _ expand and an extended starting fractional frequency division ratio nfrac _ str _ expand; the algorithm processing method comprises the following steps:

1) When odiv _ str =1, i.e., the starting odiv divide ratio is divided by 1, nint _ str _ extended = nint _ str,

nfrac_str_expand＝nfrac_str；

2) When odiv _ str =2, i.e. the initial odiv division ratio is divided by 2, the integer division ratio nint _ str and the fractional division ratio nfrac _ str both need to be multiplied by 2, and the carry problem of nfrac _ str needs to be considered, so the following steps are adopted:

a) After the two are respectively converted into binary systems, the number of bits is determined by the number of bits of the delta-sigma decimal modulator and is respectively kept unchanged in the process of carrying out the shift algorithm;

b) Shifting the nint _ str by 1 bit to the left and temporarily storing the shifted nint _ str as nint _ str _ a;

c) Whether carry is judged according to whether the most significant bit of nfrac _ str is 1:

i. when the most significant bit of nfrac _ str in binary is 1, it is necessary to advance the integer by 1 bit, i.e. the integer is not changed

nint_str_a+1＝nint_str_expand；

When the most significant bit of the binary nfrac _ str is 0, no carry to integer is required, i.e.

nint_str_a＝nint_str_expand；

d) Then nfrac _ str is shifted left by 1 to obtain nfrac _ str _ expand.

3) When the odiv _ str =4, that is, the initial odiv division ratio is division by 4, a multiplication 4 algorithm needs to be performed on both the integer division ratio nint _ str and the fractional division ratio nfrac _ str, and the carry problem of nfrac _ str needs to be considered, and since the operation is equivalent to multiplication by 2 and then multiplication by 2, 4 cases need to be considered in the carry operation, so the following steps are adopted:

a) After the two are respectively converted into binary systems, the number of bits is determined by the number of bits of the delta-sigma decimal modulator, and the two numbers are respectively kept unchanged in the process of carrying out the shift algorithm;

b) Shifting the nint _ str left by 2 bits and temporarily storing as nint _ str _ b;

c) The carry case is selected according to the most significant bit and the second most significant bit (i.e., the upper two bits) of nfrac _ str:

i. when the highest bit and the second highest bit of the binary nfrac _ str are 1 and 1 respectively, 3 bits need to be added into the integer, namely nint _ str _ b +3= nint \_expand;

when the most significant bit and the second most significant bit of nfrac _ str in binary are 1 and 0, respectively, it is necessary to carry 2 bits into the integer, i.e. nint _ str _ b +2= nint \strexpand;

when the highest bit and the second highest bit of nfrac _ str in binary are 0 and 1 respectively, it is necessary to carry 1 bit into the integer, i.e. nint _ str _ b +1= nint \\strexpand;

when the most significant bit and the second most significant bit of nfrac _ str in binary are 0 and 0, respectively, carry to integer is not needed, i.e., nint _ str _ b = nint _ str _ expand;

d) Then, nfrac _ str is shifted left by 2 to obtain nfrac _ str _ expand.

4) When the odiv _ str =8, that is, the initial odiv division ratio is division by 8, a multiplication 8 algorithm needs to be performed on both the integer division ratio nint _ str and the fractional division ratio nfrac _ str, and the carry problem of nfrac _ str needs to be considered, and since the operation of multiplying 2 by 2 and then multiplying 2 by 2 is equivalent, 8 cases need to be considered in the carry operation, so the following steps are adopted:

b) Shifting the nint _ str by 3 bits to the left and temporarily storing the shifted nint _ str as nint _ str _ c;

c) The carry case is selected according to the upper three bits of nfrac _ str:

i. when the upper three bits of nfrac _ str in binary are 111, respectively, it is necessary to advance the integer by 7 bits, i.e.

nint_str_c+7＝nint_str_expand；

When the upper three bits of the binary nfrac _ str are 110, it is necessary to carry 6 bits into the integer, i.e. to do so

nint_str_c+6＝nint_str_expand；

When the upper three bits of nfrac _ str in binary are 101, respectively, it is necessary to advance the integer by 5 bits, i.e.

nint_str_c+5＝nint_str_expand；

When the upper three bits of the binary nfrac _ str are 100, 4 bits need to be added to the integer, i.e.

nint_str_c+4＝nint_str_expand；

v. when the upper three bits of binary nfrac _ str are 011, it is necessary to advance the integer by 3 bits, i.e. by

nint_str_c+3＝nint_str_expand；

When the upper three bits of nfrac _ str in binary are 010, respectively, it is necessary to advance the integer by 2 bits, i.e.

nint_str_c+2＝nint_str_expand；

When the upper three bits of nfrac _ str in binary are 001, respectively, it is necessary to advance the integer by 1 bit, i.e.

nint_str_c+1＝nint_str_expand；

When the upper three bits of nfrac _ str in binary are 000, respectively, there is no need to carry to integer, i.e.

nint_str_c＝nint_str_expand；

d) Then, nfrac _ str is shifted to the left by 3 bits to obtain nfrac _ str _ expand.

5) By analogy, when the odiv _ str =2^ m (m represents power, and 2^ m represents power of 2), that is, the initial odiv frequency division ratio is divided by 2^ m, the algorithm of multiplying 2^ m needs to be done for both integer division ratio nint _ str and fractional division ratio nfrac _ str, and the carry problem of nfrac _ str needs to be considered, because the operation of multiplying 2 by m times is equivalent, the carry operation needs to consider 2^ m cases, therefore, the following steps are adopted:

b) Shifting the nint _ str to the left by m bits and temporarily storing the shifted nint _ str _ c;

c) The carry case is selected according to the high m bits of nfrac _ str:

i. when the high m bits of the binary nfrac _ str are all 1 (denoted as k, k =2^ m-1), the integer needs to be added with 2^ m-1 bits, namely nint _ str _ c +2^ m-1= nint \\/u expand;

when the high m bits of the binary nfrac _ str are k-1 (corresponding binary), respectively, the integer needs to be shifted by 2^ m-2 bits, i.e., nint _ str _ c +2^ m-1= nint \ str expand;

iii, the following analogy

When the high m bits of the binary nfrac _ str are 1, respectively, it is necessary to advance the integer by 1 bit, i.e.

nint_str_c+1＝nint_str_expand；

v. when the high m bits of binary nfrac _ str are all 0, respectively, carry to integer is not needed, i.e. nint _ str _ c = nint _ str _ expand;

d) Then shifting nfrac _ str to the left by m bits to obtain nfrac _ str _ expand;

e) Nfrac _ str _ expand is stored in a temporary register nfrac _ tmp, and nint _ str _ expand is stored in a temporary register nint _ tmp.

Secondly, performing a shift algorithm operation on the input terminated integer frequency division ratio nint _ trm, the terminated decimal frequency division ratio nfrac _ trm and the terminated odiv frequency division ratio odiv _ trm, and processing the input terminated integer frequency division ratio nint _ trm _ expand and the input terminated decimal frequency division ratio nfrac _ trm _ expand into an extended terminated integer frequency division ratio nint _ trm _ expand; the algorithm processing method comprises the following steps:

1) When odiv _ trm =1, i.e., terminates the odiv division ratio at division 1, nint _ trm _ extended = nint _ trm,

nfrac_trm_expand＝nfrac_trm；

2) When the odiv _ trm =2, that is, the odiv division ratio is terminated as division 2, a multiplication-by-2 algorithm needs to be performed on both the integer division ratio nint _ trm and the fractional division ratio nfrac _ trm, and a carry problem of nfrac _ trm needs to be considered, so the following steps are adopted:

b) Shifting the nint _ trm by 1 bit to the left and temporarily storing the shifted nint _ trm as nint _ trm _ a;

c) Judging whether carry is carried according to whether the most significant bit of nfrac _ trm is 1:

i. when the most significant bit of the binary nfrac _ trm is 1, it is necessary to advance the integer by 1 bit, i.e. the integer is

nint_trm_a+1＝nint_trm_expand；

When the most significant bit of the binary nfrac _ trm is 0, no carry to integer is required, i.e.

nint_trm_a＝nint_trm_expand；

d) Then, nfrac _ trm is shifted left by 1 bit to obtain nfrac _ trm _ expand.

3) When the odiv _ str =4, that is, the frequency division of the odiv division ratio is terminated by 4, a multiplication 4 algorithm needs to be performed on both the integer division ratio nint _ trm and the fractional division ratio nfrac _ trm, and the carry problem of nfrac _ trm needs to be considered, and since the operation of multiplying 2 and then multiplying 2 is equivalent, 4 cases need to be considered in the carry operation, so the following steps are adopted:

b) Shifting the nint _ trm left by 2 bits and temporarily storing as nint _ trm _ b;

c) The carry case is selected according to the most significant and second most significant (i.e., two high) bits of nfrac _ trm:

i. when the highest bit and the second highest bit of the binary nfrac _ trm are 1 and 1 respectively, 3 bits need to be added into the integer, namely nint _ trm _ b +3= nint \\uexpand;

when the most significant and the second most significant bits of the binary nfrac _ trm are 1 and 0, respectively, it is necessary to carry the integer by 2 bits, i.e. nint _ trm _ b +2= nint \\ trm _expand;

when the most significant bit and the second most significant bit of the binary nfrac _ trm are 0 and 1, respectively, it is necessary to carry 1 bit into the integer, i.e. nint _ trm _ b +1= nint \\ trm _expand;

when the most significant bit and the second most significant bit of the binary nfrac _ trm are 0 and 0, respectively, no carry to an integer is required, i.e., nint _ trm _ b = nint _ trm _ expand;

d) Then, nfrac _ trm is shifted left by 2 bits to obtain nfrac _ trm _ expand.

4) When the odiv _ trm =8, that is, when the odiv division ratio is terminated by division 8, a multiplication 8 algorithm needs to be performed on both the integer division ratio nint _ trm and the fractional division ratio nfrac _ trm, and the carry problem of nfrac _ trm needs to be considered, since the operation of multiplying 2 by 2 and then multiplying 2 by 2 is equivalent to the carry operation, 8 cases need to be considered in the carry operation, and therefore the following steps are adopted:

b) Shifting the nint _ trm left by 3 bits and temporarily storing the shifted nint _ trm as nint _ trm _ c;

c) The carry case is selected according to the upper three bits of nfrac _ trm:

i. when the upper three bits of the binary nfrac _ trm are 111, respectively, an integer needs to be advanced by 7 bits, i.e., nint _ trm _ c +7= nint \\ trm \, extended;

when the upper three bits of the binary nfrac _ trm are 110, respectively, the integer needs to be advanced by 6 bits, i.e., nint _ trm _ c +6= nint \_expandd;

when the upper three bits of the binary nfrac _ trm are 101, respectively, the integer needs to be advanced by 5 bits, i.e. nint _ trm _ c +5= nint \_ _ trm \expand;

when the upper three bits of the binary nfrac _ trm are 100, respectively, 4 bits need to be added to the integer, i.e., nint _ trm _ c +4= nint \\uexpandd;

v. when the upper three bits of binary nfrac _ trm are 011, respectively, 3 bits need to be advanced into the integer, i.e., nint _ trm _ c +3= nint \_expandd;

when the upper three bits of the binary nfrac _ trm are 010 respectively, 2 bits need to be added into the integer, namely nint _ trm _ c +2= nint \_ _ expand;

when the upper three bits of nfrac _ trm in binary are 001, respectively, it is necessary to advance 1 bit into the integer, i.e. nint _ trm _ c +1= nint \_ _ expand;

when the upper three bits of the binary nfrac _ trm are 000, respectively, carry to integer is not needed, i.e., nint _ trm _ c = nint _ trm _ expand;

d) Then shifting nfrac _ trm to the left by 3 bits to obtain nfrac _ trm _ expand.

5) By analogy, when the odiv _ trm =2^ m (m represents power, and 2^ m represents power of 2), namely when the stop of the odiv frequency division ratio is 2^ m frequency division, the algorithm of multiplying 2^ m needs to be carried out on the integer frequency division ratio nint _ trm and the decimal frequency division ratio nfrac _ trm, and the carry problem of nfrac _ trm needs to be considered, because the operation of multiplying 2 by m times is equivalent, the carry operation needs to consider 2^ m conditions, so the following steps are adopted:

b) Shifting the nint _ trm left by m bits and temporarily storing as nint _ trm _ c;

c) The carry case is selected according to the high m bits of nfrac _ trm:

i. when the high m bits of binary nfrac _ trm are all 1 (denoted as k, k =2^ m-1) respectively,

2 m-1 bits are needed to be added into the integer, i.e., nint _ trm _ c +2 m-1= nint \utrm \ "extended;

when the high m bits of binary nfrac _ trm are k-1 (corresponding binary), respectively, it is necessary to carry the integer 2^ m-2 bits, i.e., nint _ trm _ c +2^ m-1=nint \\ u trm \, extended;

iii, the following analogy

When the high m bits of binary nfrac _ trm are 1, respectively, it is necessary to advance the integer by 1 bit, i.e.

nint_trm_c+1＝nint_trm_expand；

v. when the high m bits of binary nfrac _ trm are all 0, respectively, carry to integer is not needed, i.e. nint _ trm _ c = nint _ trm _ expand;

d) Then, left shift is performed on nfrac _ trm by m bits to obtain nfrac _ trm _ expand.

And thirdly, judging the current state of the phase-locked loop through the locking indication LDT, and entering the next state S2 if the phase-locked loop is in the locking state. If the phase-locked loop is in the unlocking state, the phase-locked loop is switched from the S1 state to the S5 state, enters the re-locking process, returns to the S1 state after locking is finished, and is immediately switched to the S2 state.

The S2 state of the invention judges the frequency sweeping mode and judges the frequency sweeping direction (uplink or downlink) according to the externally set frequency sweeping mode, and the state comprises the following steps:

firstly, judging according to an externally set frequency sweeping mode. Taking the present invention as an example, the frequency sweep modes include three modes, namely continuous bidirectional frequency sweep, triggered unidirectional frequency sweep, and the like. Continuous bidirectional frequency sweeping means that uplink frequency sweeping and downlink frequency sweeping are carried out alternately, namely, the downlink frequency sweeping is carried out immediately after the uplink frequency sweeping, the uplink frequency sweeping is carried out immediately after the downlink frequency sweeping, and the like, so that the frequency sweeping is carried out continuously, and the triangular waveform is realized; the triggered bidirectional frequency sweeping is similar to the direction of continuous bidirectional frequency sweeping, and the frequency sweeping is carried out alternately in an uplink mode and a downlink mode, but the starting of the uplink frequency sweeping or the downlink frequency sweeping needs to be controlled by an external trigger signal; the triggered unidirectional frequency sweep adopts uplink frequency sweep, the starting frequency point is returned after the uplink frequency sweep is finished, and the starting of each uplink frequency sweep needs to be controlled by an external trigger signal. For the frequency sweep mode in this state, for example, a mode of adding any frequency sweep waveform, refer to the "method for sweeping any waveform based on continuously controlled delta-sigma fractional modulator" in the applied patent.

Setting an odiv change direction pointer, namely indicating the change condition of the frequency dividing ratio of the power frequency divider of 2 in the frequency sweeping process, wherein the pointer is marked as odiv _ updw, when the odiv changes from a high frequency dividing ratio to a low frequency dividing ratio, the frequency sweeping is from low frequency to high frequency, and the odiv _ up =1, and if no jump exists, the frequency sweeping is 0; when odiv changes from a low division ratio to a high division ratio, the frequency sweep is from high frequency to low frequency, odiv _ dw =1, and is 0 if there is no transition. By setting the odiv _ up and odiv _ dw pointers, continuous coverage of the frequency sweep can be ensured between different octaves. And storing the odiv _ str in a temporary register odiv _ tmp, switching to the next octave after the frequency sweeping of one octave is finished, and updating the corresponding odiv _ tmp until the odiv _ trm is reached, and ending the updating.

And thirdly, after the frequency sweep mode is determined, judging the uplink or downlink frequency sweep. Taking the present invention as an example, for both continuous bidirectional frequency sweeping and triggered bidirectional frequency sweeping, when the uplink frequency sweeping is adopted, the state S2 is switched to the state S3, and when the downlink frequency sweeping is adopted, the state S2 is switched to the state S4. For the triggered unidirectional frequency sweep, the state S2 is directly switched to the state S3 because only the uplink frequency sweep is adopted.

S3 is the ascending frequency sweeping processing.

The method comprises the following steps:

the first step, obtaining the increment of the frequency dividing ratio of the frequency dividing module by accumulating nfrac _ tmp by a stepping step to realize the up frequency dividing, wherein the stepping is controlled by the clk _ swp clock, namely, every time when clk _ swp rises, the values of nint _ tmp and nfrac _ tmp are updated once;

after the steps are completed, if the abnormal condition of losing the lock occurs, the abnormal processing stage after losing the lock needs to be immediately switched to, namely, the locking indication LDT is used for judging whether to switch the state or not, and when the abnormal condition occurs, the state is switched from the S3 state to the S6 state; if the lock is still kept, the state is continued (S3);

thirdly, judging whether the nint _ tmp and nfrac _ tmp reach the termination integer frequency division ratio and the termination decimal frequency division ratio, wherein the reaching judgment is carried out according to the following criteria:

1) The current divide ratio of the power-of-2 divider is odiv _ trm and nint _ tmp > nint _ trm _ expand;

2) When nint _ tmp = nint _ trm _ expand and nfrac _ tmp > nfrac _ trm _ expand.

When the two criteria are met, one criterion is considered to be met, and the state needs to be switched from the S3 state to the S8 state at the same time. If neither of these conditions is satisfied, the present state is continued (S3).

S4 of the invention is the descending frequency sweep treatment, which comprises the following steps:

the first step, the gradual reduction of the frequency dividing ratio of the frequency dividing module is obtained by decreasing nfrac _ tmp by a stepping step to realize the downlink frequency dividing, the stepping is controlled by a clk _ swp clock, namely, the values of nint _ tmp and nfrac _ tmp are updated once every time the rising edge of clk _ swp comes;

after the steps are completed, if the abnormal condition of losing the lock occurs, the abnormal processing stage after losing the lock needs to be immediately switched to, namely, the locking indication LDT is used for judging whether to switch the state or not, and when the abnormal condition occurs, the state is switched from the S4 state to the S7 state; if the lock is still kept, the state is continued (S4);

thirdly, judging whether the nint _ tmp and nfrac _ tmp reach the initial integer frequency division ratio and the initial decimal frequency division ratio of the first segment, wherein the reaching judgment is carried out according to the following criteria:

1) The division ratio of the current power-of-2 divider is odiv _ str and nint _ tmp < nint _ str _ expand;

2) When nint _ tmp = nint _ str _ expand and nfrac _ tmp < nfrac _ str _ expand.

When the two criteria are met, one criterion is considered to be met, and the state needs to be switched from the S4 state to the S8 state at the same time. If both are not satisfied, the present state is continued (S4).

The step of the S5 state is to enable the timer to time from 0 by externally configuring the time length of the timer, switch the S5 state back to the S1 state after the timer is expired, and aim to enable the sweep frequency module to enter the dormancy state and wait for the phase-locked loop to complete the process of losing the lock to re-locking in the dormancy process.

The S6 state of the invention comprises the following steps:

first, when the pointer odiv _ up =1, it is stated that the division ratio of the power-squared divider of 2 jumps from a high division ratio to a low division ratio, and at this time, the values in nint _ tmp and nfrac _ tmp are required to be respectively divided by 2 to adapt to the new octave, and the shifting algorithm is performed on the binary system while shifting to the right by one bit.

And secondly, the timer is enabled to time from 0 by externally configuring the time length of the timer, and the S6 state is switched back to the S3 state after the timer is expired, so that the sweep frequency module enters the dormancy state, and the phase-locked loop is waited to complete the process from losing the lock to re-locking in the dormancy process.

The S7 state of the invention comprises the following steps:

in the first step, when the pointer odiv _ dw =1, it is stated that the division ratio of the power-wise divider of 2 jumps from a low division ratio to a high division ratio, and then the values in nint _ tmp and nfrac _ tmp are multiplied by 2 respectively to adapt to the new octave, and the shifting algorithm is performed on the binary system to shift one bit to the left at the same time.

And secondly, the timer is enabled to time from 0 by externally configuring the duration of the timer, and the S7 state is switched back to the S4 state after the timer is expired, so that the sweep frequency module enters the dormancy state, and the phase-locked loop is waited to finish the process from losing the lock to re-locking in the dormancy process.

The S8 state is the next state judged according to the frequency sweeping mode, when the frequency sweeping mode is a continuous mode, and the frequency sweeping mode is a continuous bidirectional frequency sweeping mode in the invention, the S8 state is switched to the state S2, a new round of ascending and descending frequency sweeping is automatically entered, and the continuous frequency sweeping work is realized; when the frequency sweep mode is a trigger type, in the invention, the frequency sweep mode is a trigger type two-way frequency sweep mode and a trigger type one-way frequency sweep mode, the frequency sweep mode is switched from S8 to S1, the process of relocking needs to be entered, and after relocking is finished, the frequency sweep mode is switched from S1 to S2, an indication command of an external trigger signal is waited, and then a new frequency sweep mode is entered, so that the trigger type frequency sweep is realized.

The transition diagram of the above-described respective states is shown in fig. 2.

Starting to enter an S1 state from the start of frequency sweeping, after configuration of initialization parameters is completed in S1, switching to an S5 state through locking judgment if the initial parameters are unlocked, and switching back to the S1 state after S5 waits for re-locking of a phase-locked loop, and switching to an S2 state if the initial parameters are locked; performing frequency sweeping mode judgment in the S2 state, performing frequency sweeping direction judgment, switching from the S2 state to the S3 state if the frequency sweeping direction is the uplink frequency sweeping direction, and switching from the S2 state to the S4 state if the frequency sweeping direction is the downlink frequency sweeping direction, and setting a pointer with hopping frequency division ratio of power of 2 so as to indicate octave switching of frequency sweeping; performing uplink frequency sweeping control in the S3 state, performing frequency division ratio termination judgment, performing locking judgment at the same time, and switching to S6 if the frequency division ratio is unlocked; performing downlink frequency sweeping control in the S4 state, performing judgment of reaching the initial frequency division ratio, performing locking judgment at the same time, and switching to S7 if the locking is lost; s5, performing locking judgment in the initial process, and switching back to the S1 state if locking is performed; s6, performing locking judgment in the uplink process, and switching back to the S3 state if locking is performed; s7, performing locking judgment in a downlink process, and switching back to the S4 state if locking is performed; and S8, determining to enter the next section of frequency sweeping state according to the frequency sweeping mode, if the frequency sweeping state is continuous frequency sweeping, switching to S2, and if the frequency sweeping state is triggered frequency sweeping, switching to S1.

Example two

On the basis of the first embodiment, the second embodiment of the present invention takes a triangular wave for realizing continuous bidirectional frequency sweeping as an example, the durations of the upstream and downstream frequency sweeping portions of the triangular wave are both 50us, the phase demodulation frequency of the clock output by the phase-locked loop to the frequency sweeping module is 100MHz, the frequency division frequency of the clock output to the delta-sigma fractional modulator is 100mhz, and the delta-sigma fractional modulator is 8 bits. The obtained integer frequency division ratio of the lowest frequency division ratio configured in the single frequency pass is 42, the fractional frequency division ratio is 0.5, the integer frequency division ratio of the highest frequency division ratio is 47, the fractional frequency division ratio is 0.5, the lowest frequency in the single frequency pass is 4250MHz, the highest frequency is 4750MHz, and the frequency sweep stepping can be obtained by the formula step = t × fref. The highest division ratio of the power-of-2 divider is 2 and the lowest division ratio is 1.

The following parameters are correspondingly configured:

nint_str＝42

nfrac_str＝0.5

step＝5000

nint_trm＝47

nfrac_trm＝0.5

odiv_str＝2

odiv_trm＝1

the lowest frequency of the multiple frequency sweep obtained by the formula fref x (nint. Nfrac @ min)/odiv _ str is 2125MHz, and the highest frequency obtained by the formula fref x (nint. Nfrac @ max)/odiv _ trm is 4750Mz. Compared with the single-frequency-pass frequency sweep range, the frequency sweep range of the multiple frequency is expanded by 2125MHz.

The above configuration satisfies the design requirements of the triangular wave described above.

Starting frequency sweep, entering an S1 state, storing configured nint _ str =42 in a temporary register nint _ tmp, storing nfrac _ str =0.5 in a temporary register nfrac _ tmp, and temporarily outputting the nfrac _ str =0.5 to a delta-sigma decimal modulator when a rising edge of clk _ swp comes. Judging the current state of the phase-locked loop through the locking indication LDT, and switching from the S1 state to the S5 state if the phase-locked loop is in the unlocking state; the initial state of the phase-locked loop in the embodiment is an unlocked state, the phase-locked loop is switched from the S1 state to the S5 state, the sweep frequency module enters the dormant state after the time length of the timer is configured outside the S5, the phase-locked loop is waited to complete unlocking to re-locking in the dormant process, and then the phase-locked loop is switched back to the S1 state from the S5 state.

Performing a shift algorithm operation on the input starting integer division ratio nint _ str, starting fractional division ratio nfrac _ str and starting odiv division ratio odiv _ str to process into an expanded starting integer division ratio nint _ str _ expand and an expanded starting fractional division ratio nfrac _ str _ expand; the algorithm processing method comprises the following steps:

1) Since the odd _ str =2, that is, when the initial odd dividing ratio is divided by 2, the integer dividing ratio nint _ str and the fractional dividing ratio nfrac _ str both need to be multiplied by 2, and carry problem of nfrac _ str needs to be considered, the following steps are adopted:

a) The two are respectively converted into binary systems, the digit is about 8 bits, the nint _ str =42 is converted into binary systems of 00101010, and the binary systems are represented by the formula: decimal nfrac _ str multiplied by 2^8=128, which is converted into binary nfrac _ str to obtain 10000000;

b) The nint _ str is shifted left by 1 bit and temporarily stored as nint _ str _ a =01010100, corresponding to decimal 84;

c) Judging whether carry is carried out or not according to whether the highest bit of nfrac _ str is 1 or not, and when the highest bit of nfrac _ str is 1, carrying out 1 bit on an integer, namely nint _ str _ a +1= nint \\/str expand to obtain 01010101 which corresponds to 85 decimal;

d) Then shifting nfrac _ str to the left by 1 to obtain nfrac _ str _ expand

nfrac _ str _ expand =00000000, corresponding to decimal 0;

e) From the above verification, 42.5 × 2=85.

2) When odiv _ trm =1, i.e., terminating the odiv division ratio at 1 division, nint _ trm _ expand = nint _ trm, nfrac _ trm _ expand = nfrac _ trm, i.e., nint _ trm _ expand =00101111, nfrac _trm _expand =10000000.

In the state S1, the division ratio of the power divider 2 is indicated to change from the high division ratio 2 to the low division ratio 1 in the up-going frequency sweep and from the low division ratio 1 to the high division ratio 2 in the down-going frequency sweep. And judging the state of the current phase-locked loop through the locking indication LDT, and entering the next state S2 if the phase-locked loop is in a locking state. And if the phase-locked loop is in the unlocking state, switching from the S1 state to the S5 state, entering a re-locking process, returning to the S1 state after locking is finished, and immediately switching to the S2 state.

In the S2 state, firstly, judging a frequency sweeping mode, and when an uplink frequency sweeping mode is adopted, switching from the S2 state to the S3 state, entering an uplink frequency sweeping stage, and storing odiv _ str =2 in a temporary register odiv _ tmp because a continuous bidirectional frequency sweeping mode is adopted by design requirements.

In the S3 state, nfrac _ tmp is accumulated by stepping step =5000 to obtain the increment of the frequency dividing ratio of the frequency dividing module so as to realize the up-going frequency dividing, the stepping is controlled by a clk _ swp clock, namely, every time when the rising edge of clk _ swp comes, the values of nint _ tmp and nfrac _ tmp are updated once, after the step is completed, if the abnormality of losing lock occurs, the step needs to be immediately shifted to an abnormality processing stage after losing lock, namely, the phase-locked loop judges whether to carry out state switching or not through locking indication LDT, in the embodiment of the invention, the phase-locked loop still keeps locking, and then the state is continued (S3); a pointer signal indicating an octave switching is set. Meanwhile, whether the nint _ tmp and the nfrac _ tmp reach the final integer frequency division ratio nint _ trm _ expand and the final decimal frequency division ratio nfrac _ trm _ expand is judged, if the conditions are not met in the case, the state is continued (S3). When the octave is scanned, the sweep frequency range is 2125M-4250 MHz in this case. Indicating signal odiv _ up =1, indicating that the next octave needs to be entered, the lock will be lost, and the uplink lock losing processing state S6 is immediately entered. In this case, switching from the high division ratio 2 to the low division ratio 1 enters the second octave stage.

In the S6 state, in response to the indication signal of odiv _ up =1, divide by 2 is performed on nint _ tmp and nfrac _ tmp, and in binary, the operation is performed by shifting 1 bit to the right, and the operation enters the relock stage, and returns to the S3 state after locking.

And continuing to perform the ascending frequency sweep incremental operation in the second octave stage in the S3 state, and if the targets of stopping the integer frequency division ratio and stopping the decimal frequency division ratio are met, namely when one of the following conditions is met:

Then the state S8 is entered, the uplink sweep range of the second octave is 4250M-4750 MHz, and the continuous switching of the two octaves realizes the uplink sweep range of 2125M-4750 MHz.

In S8, judging that the continuous bidirectional frequency sweeping is performed according to the frequency sweeping mode, and switching to S2. In S2, the sweep frequency is changed from the up sweep frequency to the down sweep frequency, and S2 is switched to S4.

In S4, nfrac _ tmp is decreased by a step =5000 to obtain a gradual decrease of the frequency division ratio of the frequency sweep module, so as to realize a downward frequency sweep, where the step is controlled by a clk _ swp clock, that is, every time a rising edge of clk _ swp comes, the values of nint _ tmp and nfrac _ tmp are updated once, after the step is completed, if an abnormality of losing lock occurs, it is required to immediately shift to an abnormality processing stage after losing lock, that is, it is required to determine whether to perform state switching by a lock indication LDT, in the present embodiment, a phase-locked loop remains locked, and continues the present state (S4), and at the same time, it is determined whether nint _ tmp and nfrac _ tmp reach a start integer frequency division ratio nint _ str and a stop decimal frequency division ratio nfrac _ str, and continues the present state (S4) when the values do not meet the start integer frequency division ratio, nfrac _ tmp and the stop decimal frequency division ratio nfrac _ str. When the octave is scanned, the sweep frequency range is 4750M-4250 MHz in this case. The indication signal odiv _ dw =1 indicates that the next octave needs to be entered, and the lock losing occurs, and the uplink lock losing processing state S7 is immediately shifted to. In this case, switching from a low division ratio of 1 to a high division ratio of 2 enters the second octave stage.

In the S7 state, in response to the indication signal of odiv _ dw =1, the operation of multiplying nint _ tmp and nfrac _ tmp by 2 is performed, and in the binary process, the operation is performed by shifting 1 bit to the left, and the operation enters the relock stage, and the state returns to the S4 state after locking.

And continuing to perform the decrement operation of the uplink frequency sweep of the second octave stage in the S4 state, if the target of reaching the initial integer frequency division ratio and the initial decimal frequency division ratio is met, namely when one of the following conditions is met:

1) The current divide ratio of the power-of-2 divider is odiv _ str and nint _ tmp < nint _ str _ expand;

Then the state S8 is entered, the uplink frequency sweep range of the second octave is 4250M-2125 MHz, and the continuous switching of the two octaves realizes the downlink frequency sweep range of 4750M-2125 MHz.

In S8, judging that the continuous bidirectional frequency sweeping is performed according to the frequency sweeping mode, and switching to S2. And in the S2, the frequency sweep from the downlink frequency sweep to the uplink frequency sweep is excessive, the S2 is switched to the S3, and the operation steps are repeated, so that the continuous bidirectional frequency sweep is realized.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A frequency multiplication frequency sweeping method is characterized in that the frequency multiplication frequency sweeping method is applied to a frequency sweeping device, and the frequency sweeping device comprises: the device comprises a frequency sweep module, a delta-sigma decimal modulator module, a frequency divider and a phase-locked loop; clocks of the frequency sweeping module and the delta-sigma decimal modulator module are respectively controlled by a phase discrimination clock and a frequency division clock of the phase-locked loop, a locking indication signal LDT output by the phase-locked loop is connected with the input of the frequency sweeping module, an integer frequency division ratio and a decimal frequency division ratio output by the frequency sweeping module are used as the input of the delta-sigma decimal modulator module, and the delta-sigma decimal modulator module outputs the frequency division ratio to the phase-locked loop;

the method comprises the following steps:

setting a plurality of working states of the frequency sweeping device;

2. A frequency multiplication frequency sweeping method according to claim 1, wherein the frequency sweeping device comprises 8 working states, which are respectively: an initialization and locking judgment state S1, a frequency sweep mode judgment state S2, an uplink frequency sweep state S3, a downlink frequency sweep state S4, an initial lock losing processing state S5, an uplink lock losing processing state S6, a downlink lock losing processing state S7 and a termination state S8;

performing downlink frequency sweeping control in a state S4, switching to a state S8 if the frequency sweeping frequency returns to the initial frequency dividing ratio and the phase-locked loop is locked, and switching to a state S7 if the phase-locked loop is unlocked;

and in the state S8, determining to enter a next sweep frequency state according to the sweep frequency mode, if the sweep frequency is a continuous sweep frequency, switching to the state S2, and if the sweep frequency is a trigger sweep frequency, switching to the state S1.

3. The frequency multiplication frequency sweeping method according to claim 1, wherein the frequency sweep signal comprises a plurality of frequency sweep signal segments connected in sequence, the frequency sweeping direction of each frequency sweep signal segment is any one of an uplink frequency sweep, a downlink frequency sweep and a parallel frequency sweep, and each frequency sweep signal segment corresponds to a corresponding frequency sweep duration.

4. The frequency multiplication frequency sweeping method according to claim 3, wherein before frequency sweeping, the method further comprises marking the initial integer frequency division ratio and the initial fractional frequency division ratio of each frequency sweeping signal segment respectively to obtain marking information, and configuring condition information required to be met by the marking information according to the frequency sweeping signals.

5. Frequency multiplication frequency sweeping method according to claim 2, characterized in that in state S1 comprises the following steps:

processing the input termination integer frequency division ratio nint _ trm, the termination fractional frequency division ratio nfrac _ trm and the termination frequency division ratio odiv _ trm to obtain a termination integer frequency division ratio nint _ trm _ expand and an expansion termination fractional frequency division ratio nfrac _ trm _ expand;

6. Frequency multiplication frequency sweeping method according to claim 2, characterized in that in state S2 it comprises the following steps:

7. Frequency multiplication frequency sweeping method according to claim 2, characterized in that in state S3 comprises the following steps:

8. A frequency multiplication frequency sweeping method according to claim 2, comprising the following steps in state S4:

whether the temporary registers nint _ tmp and nfrac _ tmp reach the initial integer frequency division ratio and the initial fractional frequency division ratio of the first stage or not is judged, if yes, the state S4 is switched to the state S8, and if yes, the state S4 is kept continuously.

9. Frequency multiplication frequency sweeping method according to claim 2, characterized in that in state S6 it comprises the following steps:

in state S7 the following steps are included:

the timer is started from 0 by configuring the duration of the timer externally, and the state S7 is switched back to the state S4 after the timer is expired.

10. A frequency multiple sweep method as claimed in claim 4, wherein the frequency sweep signal is an up sawtooth waveform frequency sweep signal, or the frequency sweep signal is a down sawtooth waveform frequency sweep signal, or the frequency sweep signal is a triangular waveform frequency sweep signal, or the frequency sweep signal is a trapezoidal waveform frequency sweep signal.