CN212569115U

CN212569115U - Detection device of synthesizer and radar system

Info

Publication number: CN212569115U
Application number: CN202022020191.1U
Authority: CN
Inventors: 安发志; 周文婷
Original assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Current assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Priority date: 2019-11-22
Filing date: 2020-09-15
Publication date: 2021-02-19
Anticipated expiration: 2030-09-15
Also published as: CN111025245A; CN112098962A

Abstract

The utility model relates to a radar technical field especially relates to a detection device and radar system. The utility model provides a detection device includes: the input circuit is connected with the synthesizer to receive the frequency modulation continuous wave signal and down-converts and shapes the frequency modulation continuous wave signal to generate a first clock signal; a ring register link for updating values of corresponding data bits in the indicating data according to clock edges of the first clock signal; and the processing circuit samples the indicating data based on the second clock signal to obtain a measured value, and provides detection result data according to the measured value to indicate whether the frequency of the frequency-modulated continuous wave signal is normal or not. The frequency of the first clock signal changes linearly in the detection interval, the frequency of the second clock signal is smaller than that of the first clock signal, and the measured value is controlled by the number of clock edges of the first clock signal in the detection interval. The radar system and the detection device provided by the disclosure can be used for judging whether the frequency of the frequency-modulated continuous wave signal is normal or not.

Description

Detection device of synthesizer and radar system

Technical Field

The utility model relates to a radar technical field, more specifically relates to a detection device and radar system.

Background

In a radar system, a Frequency difference between an echo signal and a transmitted signal can be obtained by transmitting and receiving Frequency Modulated Continuous Wave (FMCW), so as to obtain information such as a distance and a speed of a target according to the Frequency difference. The modulation mode adopting the frequency modulation continuous wave has the outstanding advantages of simple realization structure, simple signal processing process, low cost, low power and the like, and is widely applied to the fields of vehicle-mounted radars and the like.

Because the frequency of the frequency modulation continuous wave is constantly changed in the working process of the radar system, the frequency state of the frequency modulation continuous wave can be used for judging whether modules such as a phase-locked loop and the like in the radar system are in a normal working state.

Based on this, it is desirable to provide a frequency detection scheme for frequency modulated continuous waves, which is used to determine whether the radar system and the synthesizer are in a normal operation state.

SUMMERY OF THE UTILITY MODEL

In order to solve the problem that above-mentioned prior art exists, the utility model provides a radar system and detection device can carry out real time monitoring to the frequency of frequency modulation continuous wave signal to judge whether frequency variation of frequency modulation continuous wave signal is in normal condition.

According to a first aspect of the embodiments of the present invention, there is provided a detection apparatus for a synthesizer, the synthesizer is used for outputting a frequency modulated continuous wave signal, the detection apparatus includes: the input circuit is connected with the synthesizer to receive the frequency modulation continuous wave signal and performs frequency reduction and shaping processing on the frequency modulation continuous wave signal to generate a first clock signal in a square wave form, and the frequency of the first clock signal changes linearly in a detection interval; a ring register link coupled to the input circuit to receive the first clock signal, to provide indicating data, and to update values of corresponding data bits in the indicating data according to respective clock edges of the first clock signal; and a processing circuit, coupled to the ring register link, for: and sampling the indicating data based on a second clock signal to obtain a measured value, and providing detection result data according to the measured value, wherein the detection result data represents whether the frequency of the frequency-modulated continuous wave signal is normal or not, the frequency of the second clock signal is less than that of the first clock signal, and the measured value is controlled by the number of clock edges of the first clock signal in the detection interval.

Optionally, for each detection interval, the ring register link is adapted to: circularly updating the value of each data bit of the indicating data under the triggering of each clock edge in turn; and updating the value of a respective one of the data bits in the indicating data triggered by each of the clock edges.

Optionally, the processing circuit includes: a sampling unit, connected to the ring register link, for: sampling the indication data based on the second clock signal to obtain a start value and an end value of the indication data within a detection interval, wherein the detection interval corresponds to one or more sampling periods of the second clock signal; a storage unit, configured to store a relationship lookup table in advance to indicate sequence numbers respectively corresponding to a plurality of state values of the indication data in an output logic sequence of the ring register link, where the plurality of state values include the start value and the end value, and the sequence numbers include a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; and a first judging unit, configured to obtain the measurement value according to a difference between the first sequence number and the second sequence number, and judge whether the offset between the measurement value and a preset expected value of the detection interval is greater than a first threshold, if yes, the first judging unit sets a first bit result value of the detection result data to be in an effective state to indicate that an average value of the frequency-modulated continuous wave signal in the detection interval does not satisfy an expected range, and if not, the first judging unit sets the first bit result value to be in an ineffective state to indicate that the average value of the frequency-modulated continuous wave signal in the detection interval satisfies the expected range.

Optionally, the preset expected value is: calculating the obtained data value based on a total number of the plurality of state values and an expected number of occurrences of a clock edge of the first clock signal within the detection interval.

Optionally, for each detection interval: the measured value is equal to the difference value, the preset expected value is equal to a remainder obtained by dividing twice of a set value corresponding to the detection interval by the total number of the plurality of state values, and the set value is equal to a product of an expected average value of the frequency of the first clock signal in the detection interval and the duration of the detection interval.

Optionally, the processing circuit further includes: a counter for providing a count value in accordance with the first bit result value, the counter being responsive to the first bit result value in an active state to increment the count value by 1 and responsive to the first bit result value in an inactive state to reset the count value to an initial value; and the comparator is used for judging whether the counting value is larger than a second threshold value or not, if so, the comparator sets a second bit result value of the detection result data to be in an effective state to represent that the frequency change of the frequency modulation continuous wave signal is in an abnormal state, and if not, the comparator sets the second bit result value to be in an ineffective state to represent that the frequency change of the frequency modulation continuous wave signal is in a normal state.

Optionally, the synthesizer includes: and the phase-locked loop structure comprises a voltage-controlled oscillator, wherein the voltage-controlled oscillator generates the frequency-modulated continuous wave signal according to the frequency control voltage, and the frequency of the frequency-modulated continuous wave signal changes along with the voltage value of the frequency control voltage.

For example, when the offset obtained by calculation is less than or equal to the first threshold, the detection apparatus disclosed in the embodiment of the present invention may determine that the phase-locked loop structure is in the normal operating state, otherwise, the phase-locked loop structure is in the abnormal operating state; and in order to promote the accurate nature of judgement, the embodiment of the utility model discloses a detection device can judge respectively to a plurality of detection intervals and handle, and only in all or the detection interval of predetermineeing the proportion, the offset all is less than/equal to foretell first threshold value, and present the change of certain law simultaneously or change amplitude is less hour, just judges this phase-locked loop structure and be in normal operating condition. Wherein, the judgment of the magnitude of the variation amplitude can be set based on the actual precision requirement.

In addition, to being in the phase-locked loop structure of abnormal operating condition, the embodiment of the utility model provides a detection device still can judge the change law of the different detection interval gained offsets through further analysis, confirms whether the phase-locked loop structure is in locking state or unstable state (promptly in this application embodiment, abnormal operating condition can include locking state and unstable state). For example, when the offset obtained in adjacent sampling periods (corresponding to adjacent detection intervals) changes randomly or the change amplitude is large, it may be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, it may be considered that some devices in the phase-locked loop structure may be damaged at this time; otherwise, the phase-locked loop structure may be considered to be in a locked state in the abnormal state.

According to a second aspect of the embodiments of the present invention, there is provided a radar system, which includes any one of the detection device and the synthesizer provided by the embodiments of the present invention; and a radar transceiver providing a transmit signal and/or processing an echo signal in dependence on the frequency modulated continuous wave signal.

In an alternative embodiment, the radar system may be integrated in the same chip structure.

In an alternative embodiment, the chip structure is an Aip (packaged antenna) radar chip.

According to the utility model provides a radar system and detection device, through falling the frequency modulation continuous wave signal and the first clock signal that the shaping obtained the square wave form, the value of corresponding data bit in the data is instructed along the update to each clock according to first clock signal, and sample in order to obtain the measured value that is controlled by the clock edge number of first clock signal based on the second clock signal to instruction data, thereby can obtain the testing result data according to the measured value, whether normal with the frequency of sign frequency modulation continuous wave signal, the detection to the frequency of frequency modulation continuous wave signal has been realized. The utility model discloses in the radar system of embodiment, because the frequency of frequency modulation continuous wave signal is controlled by the synthesizer, whether the detection result data that consequently detection device provided can instruct the synthesizer to work unusually, whether radar system works unusually.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of a radar system according to an embodiment of the present invention;

FIG. 2 shows a schematic diagram of an embodiment of the synthesizer of FIG. 1;

fig. 3 is a schematic diagram showing waveforms of the frequency modulated continuous wave signal, the first clock signal and the frequency control voltage according to the embodiment of the present invention;

fig. 4 shows a schematic block diagram of a detection apparatus of an embodiment of the present invention;

fig. 5 shows a schematic structural diagram of a ring register link according to an embodiment of the present invention;

FIG. 6 is a circuit diagram of the registers of FIG. 5;

FIG. 7 shows a schematic block diagram of one implementation of the processing circuit of FIG. 4;

FIG. 8 shows a schematic block diagram of another implementation of the processing circuit of FIG. 4;

fig. 9 shows a schematic flow chart of a detection method according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

Overview of the System

Fig. 1 shows a schematic structural diagram of a radar system according to an embodiment of the present invention. Fig. 2 shows a schematic diagram of an embodiment of the synthesizer of fig. 1. Fig. 3 is a schematic diagram of waveforms of the frequency modulated continuous wave signal, the first clock signal and the frequency control voltage according to the embodiment of the present invention.

As shown in fig. 1, a radar system according to an embodiment of the present invention includes: the device comprises a transceiving antenna, a receiving channel, a transmitting channel, a synthesizer, a signal processing module and a detection device. The receiving and transmitting antenna, the receiving channel, the transmitting channel and the signal processing module are used as radar transceivers, and the radar transceivers provide transmitting signals and/or process echo signals according to frequency modulation continuous wave signals provided by the synthesizer.

The following describes each part of the radar system based on the frequency modulated continuous wave system according to the present embodiment with reference to fig. 1 to 3. However, the embodiments of the present invention are not limited thereto, and a/some conventional structure/modules not mentioned may also be included in the radar system of the embodiments of the present invention.

(1) Transceiver antenna

The transceiving antenna comprises a transmitting antenna 1 and a receiving antenna 2. The transmitting antenna 1 provides a space radiation electromagnetic wave based on the transmitting signal, the electromagnetic wave is reflected on the surface of the target object, the reflected electromagnetic wave is captured by the receiving antenna, so that the receiving antenna 2 obtains an echo signal. Because in the radar system 100 of the embodiment of the present invention, the transmitting signal is a frequency modulated continuous wave with a constantly changing frequency, so the radar system 100 of the frequency modulated continuous wave system can obtain information such as the distance and the speed of the target object according to the frequency difference between the transmitting signal and the echo signal, wherein the speed of the target object can be obtained by, for example, multiple distance measurement calculations.

(2) Synthesizer

The synthesizer 6 is used for generating a frequency-modulated continuous wave signal S with a continuously variable frequency_FMThe frequency of the frequency modulated continuous wave signal changes in a trend such as a triangular wave or a sawtooth wave, and has a linear change trend in the detection area. Frequency modulated continuous wave signal S_FMThe signal may be a periodic signal or a non-periodic signal, which is not limited in this application.

As an alternative embodiment, the synthesizer 6 is, for example, a Phase Locked Loop (PLL) shown in fig. 2, and includes modules such as a Charge Pump (CP) 610, a Loop Filter (LP) 620, a Voltage Controlled Oscillator (VCO) 630, a feedback Frequency divider 640, and a Phase Frequency Detector (PFD) 650.

Wherein, the phase frequency detector 650, the charge pump 610, the loop filter 620 and the voltage-controlled oscillator 630 are cascaded in sequence, and the output end of the voltage-controlled oscillator 630 provides the output frequency-modulated continuous wave signal S_FM. The feedback frequency divider 640 receives the frequency-modulated continuous wave signal S output by the voltage-controlled oscillator 630_FMFrequency-modulated continuous wave signal S_FMFrequency division is carried out to obtain a frequency-down scanning signal S_{FM_div}And down-converting the frequency-down scanning signal S_{FM_div}Is provided to a phase frequency detector 650 forming a feedback control loop in a phase locked loop configuration.

The feedback frequency Divider 640 is, for example, a Multi-Modulus Divider (MMD) capable of dividing the frequency-modulated continuous wave signal S according to a frequency division ratio set by the mode control signal_FMDividing the frequency to obtain a down-converted scanning signal S_{FM_div}Thereby implementing a programmable frequency division function. When the frequency dividing ratio set by the mode control signal is continuously changed, the frequency-modulated continuous wave signal S_FMCan be continuously operatedAnd (4) changing.

The phase frequency detector 650 detects the frequency and phase of the reference signal Fref and the down-converted scanning signal S_{FM_div}Are compared to generate a first status signal Qa and a second status signal Qb characterizing the comparison result. As an example, the reference signal Fref may be provided by a crystal oscillator, or may be provided by other circuits or modules, which are not limited in this application.

The charge pump 610 generates the analog voltage signal Vo according to the received first and second state signals Qa and Qb, which are respectively used for up-and down-regulating the voltage value of the analog voltage signal Vo.

The analog voltage signal Vo is filtered by the loop filter 620 to obtain a frequency control voltage Vc, so that the voltage-controlled oscillator 630 generates a frequency modulation continuous wave signal S under the control of the frequency control voltage Vc_FMThe frequency modulated continuous wave signal S_FMCorresponds to the voltage value of the frequency control voltage Vc. Under the control of the above phase-locked loop structure, as shown in fig. 3, the voltage value of the frequency control voltage Vc has a linear variation trend within each linear interval Tchrip _ up, for example: the frequency control voltage Vc is linearly increased from a preset voltage at the start time of each linear interval, and the frequency-modulated continuous wave signal provided by the voltage-controlled oscillator 630 under the action of the preset voltage has the minimum frequency F_L(ii) a At the end of each linear interval, the frequency control voltage Vc reaches the highest voltage, and the frequency modulated continuous wave signal provided by the voltage controlled oscillator 630 under the action of the highest voltage has the maximum frequency F_H(ii) a In the waiting interval between every two adjacent linear intervals, the frequency control voltage Vc is reset to a preset voltage. Thus, the voltage controlled oscillator 630 provides a frequency modulated continuous wave signal S_FMIs linearly varied with the frequency control voltage Vc within each linear interval.

In some optional embodiments, the time lengths of the linear intervals Tchrip _ up are equal, and the time lengths of the waiting intervals are equal, and the linear intervals and the waiting intervals are alternately distributed in a time domain, so that the frequency control voltage Vc has a frame period and is in a triangular wave or a sawtooth wave in each frame period.

The synthesizer 6 is described in the present embodiment by taking the above phase-locked loop structure as an example, however, the synthesizer of the present invention is not limited thereto, and the synthesizer 6 may be implemented by other circuits capable of generating a frequency modulated continuous wave signal.

When the radar system works, the phase-locked loop structure containing the voltage-controlled oscillator must be ensured to be in a normal working state, so how to detect the working state of the phase-locked loop structure (or a synthesizer of other structures) is the key for ensuring the normal operation of the radar system. The utility model discloses a frequency modulation continuous wave signal after detection amplitude reduction and the plastic realizes the control of phase-locked loop structure's operating condition to judge whether synthesizer and radar system are in normal operating condition.

(3) Receiving channel and transmitting channel

The transmit path 3 and the receive path 4 are coupled to the transmit antenna 1 and the receive antenna 2, respectively. The transmission channel 3 is connected to a synthesizer 6 for receiving a frequency modulated continuous wave signal S_FMAnd the transmission channel 3 is based on the frequency modulated continuous wave signal S_FMProviding a transmission signal in the form of a frequency modulated continuous wave to a transmission antenna 1 and modulating the frequency modulated continuous wave signal S_FMProcessing is performed to generate a first signal S1. The receiving channel 4 is connected to the receiving antenna 2 to receive the echo signal, and performs filtering and the like on the echo signal, thereby generating a second signal S2.

(4) Frequency mixing unit

The mixing unit 5 is connected to the transmit path 3 and the receive path 4 to receive the first signal S1 and the second signal S2 to obtain a beat signal S based on the first signal S1 and the second signal S2_D. The beat signal S_DIs the difference between the frequency of the first signal S1 and the frequency of the second signal S2, so as to be able to characterize the difference between the time when the echo signal is received and the time when the emission signal is emitted, the difference being related to the information of the distance, the speed, etc. of the target object. Beat signal S_DFor example, is proportional to the distance between the target and the radar.

(5) Signal processing module

The signal processing module 8 receives the beat signal S provided by the mixing unit 5_DAccording to beatSignal S_DObtains a detection result Sdata including information of a distance, a speed, and the like of the target with respect to the radar system.

The signal processing module 8 for example comprises a processor for processing the beat signal S_DThe device comprises modules such as an analog-to-digital converter for generating corresponding digital signals, and an arithmetic unit for calculating and processing the digital signals.

(6) Detection device

The utility model discloses radar system still includes detection device 7, and this detection device 7 is to frequency modulation continuous wave signal S that synthesizer 6 provided_FMAnd (6) detecting.

As shown in fig. 2, the detection means 7 may be coupled to an output of the synthesizer 6 for receiving the frequency modulated continuous wave signal S_FMFor aligning frequency-modulated continuous wave signals S_FMDown-conversion and shaping are performed to obtain the first clock signal Sclk. Frequency modulated continuous wave signal S_FMIs in a set ratio N with the frequency of the first clock signal Sclk_divAnd the first clock signal Sclk is a continuous wave signal S with a frequency smaller than the frequency modulation_FMSo that the detection result data obtained by the detection device 7 detecting the frequency of the first clock signal Sclk may also represent the frequency modulated continuous wave signal S_FMWhether or not an abnormality occurs in the frequency of (2). Due to the frequency-modulated continuous-wave signal S generated by the synthesizer 6_FMIn practical applications, it is usual to have a relatively high frequency (for example, varying in the frequency range of 30GHz to 300 GHz), so that the detection device 7 can be calibrated by matching the frequencies according to the set ratio N_divThe first clock signal Sclk obtained by frequency reduction is detected to indirectly realize the frequency modulation continuous wave signal S_FMThe frequency monitoring of (2) thus improves the detection precision, and also makes the working frequency range of the detection device 7 unnecessarily high, i.e. reduces the performance requirement on the detection device 7; frequency-modulated continuous wave signal S, on the other hand_FMThe signal being generally in the form of a sine wave, the detection means 7 supplying a frequency-modulated continuous wave signal S_FMThe shaping of the first clock signal Sclk in the form of a square wave further enables a more accurate frequency detection by the detection means 7.

In addition to this, the detection means 7 are also arranged to provide indication dataAnd updating the indication data Dstate according to each clock edge of the first clock signal Sclk (i.e. the level change edge of the first clock signal Sclk, which may include each rising edge and/or each falling edge) in the detection interval, so as to determine the frequency-modulated continuous wave signal S in the detection interval according to the indication data Dstate_FMWhether the frequency of (2) is normal. For example, the detecting device 7 may update the corresponding data bits in the indicating data Dstate at each rising edge and each falling edge of the first clock signal Sclk, or may update the corresponding data bits in the indicating data Dstate only at each rising edge or each falling edge of the first clock signal Sclk.

It should be noted that, in the embodiment of the present invention, the linear interval Tchrip _ up shown in fig. 3 may be directly used as the detection interval. However, the embodiments of the present invention are not limited thereto, and in other embodiments, the detection interval may be a part of the linear interval Tchrip _ up.

Fig. 4 shows a schematic block diagram of a detection apparatus according to an embodiment of the present invention. The detection device 7 of the present embodiment will be described in detail below with reference to fig. 4.

As shown in fig. 4, the detection means 7 comprises an input circuit 7300, a ring register link 7100 and a processing circuit 7200.

Input circuit 7300 for coupling frequency modulated continuous wave signal S_FMA shaping process and a frequency reduction process are performed to generate the first clock signal Sclk. The shaping process can be realized by circuit structures such as a buffer, a phase inverter and the like, so that the first clock signal Sclk has a square waveform; the frequency-down process may be implemented by a frequency divider with a fixed or adjustable division ratio to frequency-modulate the continuous-wave signal S_FMIs in a set ratio N with the frequency of the first clock signal Sclk_divAnd the first clock signal Sclk satisfies the operating frequency of the ring register link 7100. It should be noted that the frequency reduction process may be performed before the shaping process or after the shaping process, which is not limited in this application.

The ring register link 7100 is used for providing indicating data Dstate with a plurality of data bits, and updating each data bit D1-Dn in the indicating data Dstate according to the clock edge of the first clock signal Sclk, wherein n is a natural number greater than 1.

For example, when the first clock signal Sclk has a rising edge, the logic state of a corresponding one of the data bits Di in the indicating data Dstate changes (from 1 to 0 or from 0 to 1, abbreviated as "i" update), and then, when the first clock signal Sclk has a falling edge, the logic state of another data bit Dj in the indicating data Dstate after the i "update changes (abbreviated as" j "update), and so on, it can be known that: in each frame period, the first clock signal Sclk has a rising edge and a falling edge, indicating that the data Dstate can be updated 2 times, i.e. indicating that the data Dstate has two corresponding data bits updated. Wherein i and j are respectively non-zero natural numbers less than or equal to n.

In some alternative embodiments, j is equal to i +1 when i is less than n, and j is equal to 1 when i is equal to n, so that the respective data bits D1 to Dn in the indicating data Dstate can be cyclically updated according to the clock edge of the first clock signal Sclk.

In the above description, the i-th update of the indicating data Dstate occurs when the first clock signal Sclk has a rising edge, it should be noted that in some other equivalent embodiments, the i-th update of the indicating data Dstate may occur when the first clock signal Sclk has a falling edge, and correspondingly, the j-th update of the indicating data Dstate may occur when the first clock signal Sclk has a rising edge. Furthermore, in the description of the embodiments of the present invention, the update of one data bit in the indication data Dstate means that the logical value of the data bit is updated from 1 to 0 or from 0 to 1.

The various data values that the indicating data Dstate may provide during the course of continuous update are referred to herein as the respective state values of the indicating data Dstate.

The processing circuit 7200 is connected to the output of the ring register link 7100 to receive the indication data Dstate. The processing circuit 7200 is configured to obtain preset expected values of the indication data Dstate corresponding to the detection intervals, and determine whether an average value of the frequency of the first clock signal Sclk in the detection interval meets an expected range according to a start value and an end value of the indication data Dstate in each detection interval and the preset expected value corresponding to the detection interval.

In the linear interval, the processing circuit 7200 may sample the indicating data Dstate triggered by a clock edge (rising edge or falling edge) of the second clock signal clk _ cs to obtain a start value and an end value of the indicating data Dstate in each detection interval. In this case, each detection interval corresponds to a respective one of the sampling periods in the second clock signal clk _ cs, and the start time and the end time of each detection interval correspond to two adjacent and co-directional clock edges of the second clock signal clk _ cs. The second clock signal clk _ cs is set to have a frequency less than that of the first clock signal Sclk. This embodiment will be described in detail below, however, the embodiment of the present invention is not limited thereto, and each detection interval is not limited to correspond to one sampling period of the second clock signal, but may correspond to a plurality of consecutive sampling periods.

Specifically, in each detection interval, the processing circuit 7200 may sample a start value of the indicating data Dstate at a start time of the detection interval, and each data bit D1-Dn in the indicating data Dstate is updated cyclically with the occurrence of the clock edge of the first clock signal Sclk; the processing circuit 7200 obtains an end value of the indicating data Dstate at the end time of the detection interval, and it is known that the difference between the end value and the start value is related to the number of times the indicating data Dstate is updated, that is, the total number of clock edges of the first clock signal Sclk occurring in the detection interval. Therefore, the difference between the start value and the end value of the indication data Dstate in the detection interval is related to the average frequency of the first clock signal Sclk in the detection interval. Based on this, the processing circuit 7200 may obtain a measurement value according to a difference between a start value and an end value of the indication data Dstate in each detection interval, and provide the detection result data Sout according to a preset expected value corresponding to the measurement value and the sampling period, so that the detection result data Sout can represent whether an average value of the frequency of the first clock signal Sclk in each detection interval satisfies an expected range, if soIf yes, then the frequency modulated continuous wave signal S is described_FMIs in a normal state in the detection area, if not, the frequency modulation continuous wave signal S is indicated_FMIs abnormal in the detection interval.

The "start value" disclosed herein is a data value indicating data Dstate at the start time of the detection interval; the "end value" is a data value indicating data Dstate at the end time of the detection interval. Wherein the start value and the end value are each one of the respective state values of the indicating data Dstate.

In some alternative embodiments, the preset expected value may represent an expected number of occurrences of the clock edge of the first clock signal Sclk within the detection interval, for example, an expected average value of the frequency of the first clock signal Sclk within the detection interval. Based on this, the processing circuit 7200 may calculate a predicted end value of the indicating data Dstate in the detection interval according to a start value of the indicating data in the detection interval, a preset expected value corresponding to the detection interval, and a duration of the detection interval; subsequently, the processing circuit 7200 may compare the sampled end value with the calculated predicted end value, and if the two values are within the error tolerance range, it indicates that the average value of the frequency of the first clock signal Sclk in the detection interval satisfies the expected range, and if the two values are not within the error tolerance range, it indicates that the average value of the frequency of the first clock signal Sclk in the detection interval does not satisfy the expected range, and the synthesizer 6 (shown in fig. 1) and the radar system operate abnormally.

In other alternative embodiments, the preset expected value may be a value calculated according to the total number of the state values that may be provided by the specifying data Dstate and the expected number of occurrences of the clock edge of the first clock signal Sclk within the detection interval. Based on this, for each detection interval, the processing circuit 7200 may determine whether the average value of the frequency of the first clock signal Sclk in the detection interval satisfies the desired range according to the difference between the start value and the end value of the first clock signal Sclk in the detection interval and the preset desired value corresponding to the detection interval. The following detailed description of the embodiments will be omitted.

In the embodiment shown in fig. 4, the ring register link 7100 has a clock terminal that directly receives the first clock signal Sclk, such that the ring register link takes the first clock signal Sclk as the clock signal clk. As mentioned above, the first clock signal Sclk is a frequency modulated continuous wave signal S_FMSo that it can be based on the frequency modulated continuous wave signal S_FMA known set ratio N to the frequency of the first clock signal Sclk_divAnd the detection result data Sout provided by the processing circuit 7200 acquires the frequency-modulated continuous wave signal S_FMWhether the average of the frequencies in the detection interval meets the expected frequency range, i.e.: the detection result data Sout provided by the processing circuit 7200 can also characterize the frequency modulated continuous wave signal S_FMWhether the average value of the frequencies in the detection interval satisfies the expected range. When the detection result data Sout indicates that the average value of the frequency of the first clock signal Sclk in the detection interval meets the expected range, the synthesizer works normally and the frequency-modulated continuous wave signal S is indicated_FMThe frequency change is correct, and at the moment, the radar system can work normally; when the detection result data Sout indicates that the average value of the frequency of the first clock signal Sclk in the detection interval does not conform to the expected range, the abnormal operation of the synthesizer and the frequency modulation continuous wave signal S are indicated_FMDoes not meet the expected range, and the radar system works abnormally.

The ring register link 7100 and the processing circuit 7200 of embodiments of the present invention are described in detail below.

Ring register link

Fig. 5 shows a schematic structural diagram of a ring register link according to an embodiment of the present invention. Fig. 6 shows a schematic circuit diagram of each register in fig. 5. The ring register link according to an embodiment of the present invention is described in detail below with reference to fig. 5 and 6.

As shown in fig. 5, the ring register link 7100 includes a plurality of registers 7110 cascaded in sequence, with the last level registers cascaded before the first level registers to form the ring link.

Each stage of register 7110 generates the output signal DOUT of the stage and the corresponding data bit in the indicating data Dstate according to the clock signal clk, the inverted clock signal clkb and the input signal DIN of the stage, respectively, and each stage of register 7110 corresponds to different data bits in the indicating data Dstate.

The ring register chain 7100 further comprises an odd number of inverters INV1 cascaded between the first stage register and the last stage register, so that the first stage register can obtain the input signal of the present stage according to the inverted signal of the output signal provided by the last stage register. And each stage of registers except the first stage of registers respectively obtains the input signal of the stage according to the output signal provided by the register cascaded at the previous stage.

The ring register link 7100 also comprises an odd number of inverters INV0 for generating an inverted clock signal clkb from the clock signal clk, such that the inverted clock signal clkb is the inverted signal of the clock signal clk.

In an alternative embodiment, as shown in fig. 5, the number n of data bits of the indicating data Dstate is an even number different from zero, and each stage of the register 7110 corresponds to two adjacent data bits of the indicating data Dstate, for example, the first stage register 7110 is used for outputting the data bit D1 and the data bit D2 in the indicating data Dstate, the second stage register 7110 is used for outputting the data bit D3 and the data bit D4 in the indicating data Dstate, and so on.

As an example, each stage register 7110 may update a corresponding first data bit Dk (output by the DF1 terminal of the stage register) in the indicating data Dstate according to a rising edge of the clock signal clk, and update a corresponding second data bit Dp (output by the DF2 terminal of the stage register) in the indicating data Dstate according to a falling edge of the clock signal clk. Where k and p are respectively non-zero natural numbers of n or less, and p is preferably k + 1.

In other embodiments, each stage of the register 7110 may update the corresponding first data bit Dk in the indicating data Dstate according to the falling edge of the clock signal clk, and update the corresponding second data bit Dp in the indicating data Dstate according to the rising edge of the clock signal clk, which has the same principle as the above embodiments and is not described again.

It should be noted that "updating a certain data bit" as described herein refers to resetting the corresponding data bit according to the current state of each relevant signal, that is, updating the corresponding data bit in the indication data Dstate may or may not change the logic state of the data bit.

As an alternative embodiment, each stage of registers 7110 includes at least two stages of sample and hold modules as shown in fig. 6. The number of sample-and-hold blocks cascaded in each stage of registers 7110 may be the same as the number of bits of the indicating data corresponding to each stage of registers. In this embodiment, 2 data bits are corresponding to each stage of register, and each stage of register includes a first stage sample-and-hold module and a second stage sample-and-hold module.

As shown in fig. 6, the first stage sample-and-hold block 7111 samples the input signal DIN of the present stage register in the sample state to generate the transfer signal DZ, and the second stage sample-and-hold block 7112 samples the transfer signal DZ in the sample state to generate the output signal DOUT of the present stage register.

The first stage sample and hold module 7111 has a sample state and a hold state and alternately enters the sample state and the hold state according to a clock signal clk. In a sampling state, the first stage sample-and-hold module 7111 updates the transfer signal DZ according to the input signal DIN of the present stage register; in the hold state, the first stage sample and hold module 7111 holds the pass signal unchanged.

As an alternative embodiment, the first stage sample and hold module 7111 may include a transmission gate controlled by the clock signal clk. The transmission gate includes, for example, field effect transistors M11 and M12, sources of the field effect transistors M11 and M12 are connected to receive the input signal DIN of the present stage register 7110, and drains of the field effect transistors M11 and M12 are connected to provide the transfer signal DZ; the gates of field effect transistors M11 and M12 receive clock signal clk and inverted clock signal clkb, respectively.

The first stage sample-and-hold block 7111 may further include an even number of inverters (not gates) for buffering the input signal DIN input to the transmission gate and/or buffering the transfer signal DZ output from the transmission gate.

The second stage sample-and-hold block 7112 and the first stage sample-and-hold block 7111 may have the same circuit structure, the second stage sample-and-hold block 7112 may include, for example, a transmission gate formed by field effect transistors M21 and M22, sources of the field effect transistors M21 and M22 may be coupled to receive the transfer signal DZ provided by the first stage sample-and-hold block 7111, drains of the field effect transistors M21 and M22 may be coupled to provide the output signal DOUT of the present stage register, and gates of the field effect transistors M21 and M22 may receive the clock signal clk and the inverted clock signal clkb, respectively. The second stage sample and hold block 7112 may also include an even number of inverters to buffer the pass signal DZ input to the transmission gate and/or to buffer the output signal DOUT provided by the present stage register.

In an alternative embodiment, the transmission gate in the first stage sample-and-hold block 7111 is cascaded between two inverters, and the transmission gate in the second stage sample-and-hold block 7112 is cascaded between two other inverters, so that a simple circuit structure can be used to implement an accurate sample-and-hold function.

In order to make the second stage sample-and-hold module 7112 and the first stage sample-and-hold module 7111 operate in different states at the same time, that is, the first stage sample-and-hold module 7112 and the first stage sample-and-hold module 7111 alternately enter a sampling state and a holding state, the transmission gate in the second stage sample-and-hold module 7112 and the transmission gate in the first stage sample-and-hold module 7111 are alternately turned on under the control of the clock signal clk.

As an alternative embodiment, the gates of the field effect transistors M12 and M21 receive the inverted clock signal clkb, the gates of the field effect transistors M11 and M22 receive the clock signal clk, the field effect transistors M11 and M21 are for example PMOS transistors, and the field effect transistors M12 and M22 are for example NMOS transistors. Therefore, when the clock signal clk is at a low level, the transmission gate in the first stage sample-and-hold module 7111 is turned on, so that the transmission signal DZ is the same as the input signal DIN received by the register of the current stage, and at this time, the first stage sample-and-hold module 7111 operates in a sampling state and the second stage sample-and-hold module 7112 operates in a holding state; when the clock signal clk is at a high level, the transmission gate in the second stage sample-and-hold module 7112 is turned on, so that the output signal DOUT provided by the register of the present stage is the same as the transmission signal DZ provided by the first stage sample-and-hold module 7111, and at this time, the first stage sample-and-hold module 7111 operates in a hold state and the second stage sample-and-hold module 7112 operates in a sampling state.

As shown in fig. 6, each stage of registers 7110 further includes a first stage buffer module 7113 and a second stage buffer module 7114. The first stage buffer module 7113 buffers the transmission signal DZ output by the first stage sample-and-hold module 7111 to drive/shape the first data bit Dk corresponding to the current stage register in the indicating data Dstate, and the second stage buffer module 7114 buffers the output signal DOUT provided by the second stage sample-and-hold module 7112 to drive/shape the second data bit Dp corresponding to the current stage register in the indicating data Dstate. The first-stage buffer module 7113 and the second-stage buffer module 7114 include, for example, an even number of cascaded inverters (not gates), respectively.

In the above embodiments, each stage of the sample-and-hold module and each stage of the buffer module receive the same power supply voltage, for example, the high-level power supply voltage VDD and the low-level voltage VSS.

Processing circuit

Fig. 7 shows a schematic block diagram of one implementation of the processing circuit of fig. 4.

The processing circuit according to the embodiment of the present invention is described and illustrated below according to the implementation manner shown in fig. 7, however, the embodiment of the present invention is not limited thereto, and other implementation principles of the processing circuit are described above, and those skilled in the art may also adopt other determination manners to determine whether the average value of the frequency of the first clock signal and the frequency of the frequency modulated continuous wave signal in the detection interval is within the expected range.

As shown in fig. 7, the processing circuit 7200 includes a sampling unit 7210, a storage unit 7220, and a first determination unit 7230.

The sampling unit 7210 is configured to sample the indicating data Dstate provided by the ring register link 7100 at a start time of a detection interval to obtain a start value Dstate _ ini of the indicating data within the detection interval, and sample the indicating data Dstate provided by the ring register link 7100 at an end time of the detection interval to obtain an end value Dstate _ end of the indicating data within the detection interval. The sampling unit 7210 receives a second clock signal clk _ cs, the frequency of the second clock signal clk _ cs is less than the frequency of the clock signal clk of the ring register link 7100, and the sampling period Tsample of the second clock signal clk _ cs corresponds to a detection interval, so that the sampling unit 7210 can obtain the start value Dstate _ ini and the end value Dstate _ end by sampling under the control of the second clock signal clk _ cs.

The storage unit 7220 is configured to store in advance various status values Dstate _1 to Dstate _2n that may occur indicating data, and store sequence numbers corresponding to the respective status values of the indicating data in the output logic sequence of the ring register link, so as to establish a lookup table of relationships between different status values and the sequence numbers. The memory unit 7220 may be provided in the signal processing module 8 shown in fig. 1, may be a memory provided separately, or may be provided in the same module as other circuits.

The storage unit 7220 stores, for example, a relationship lookup table as shown in table 1 below.

Table 1 prestored relation lookup table between different state values and sequence numbers

In each detection interval, the first determining unit 7230 is configured to obtain a difference Δ a between the sequence number a2 corresponding to the end value Dstate _ end of the indication data in the detection interval and the sequence number a1 corresponding to the start value Dstate _ ini of the indication data in the detection interval according to the relationship lookup table, and obtain the measurement value of the detection interval according to the difference Δ a. Further, the first determining unit 7230 may be configured to determine whether an offset a _ os between the measurement value of the detection interval and the preset expected value a _ ref is greater than a first threshold, if so, set the first bit result value Sout [0] of the detection result data Sout to be in an active state (e.g., 1, or 0 in other embodiments), and if not, set the first bit result value Sout [0] of the detection result data Sout to be in an inactive state (e.g., 0, or 1 in other embodiments), so that the first bit result value Sout [0] may represent whether an average value of the frequency of the first clock signal Sclk in the detection interval satisfies a desired range, for the following reasons:

as described above, the clock signal clk of the ring register link 7100 is the first clock signal Sclk, so the synthesizer provides the frequency modulated continuous wave signal S_FMHas a set ratio N to the frequency of the clock signal clk_divThe set ratio is usually a positive real number equal to or greater than 1.

Pseudo frequency modulated continuous wave signal S_FMThe frequency of the detection interval is fixed to f0, and the duration of the detection interval is equal to one sampling period Tsample of the second clock signal clk _ cs, then the frequency of the clock signal clk is f0/N in the detection interval_divThe number of times that the indication data Dstate provided by the ring register link 7100 is updated in the detection interval is equal to:

2*Tsample/[1/(f0/N_div)]

but due to frequency modulated continuous wave signal S_FMIn fact, it is linearly increasing in each detection interval, so that between each two adjacent sampling points, the expected number of times the indicating data Dstate output by the loop register link 7100 is updated is equal to:

{2*Tsample/[1/(F_y-1/N_div)]+2*Tsample/[1/(F_y/N_div)]}/2

namely:

Tsample*(F_y-1+F_y)/N_div

wherein y is a natural number of 1 or more, F_yAnd F_y-1Frequency modulated continuous wave signals S corresponding to the current sampling points (the current clock edge of the second clock signal clk _ cs)_FMAnd the frequency modulated continuous wave signal S corresponding to the next previous sampling point (the next clock edge of the second clock signal clk _ cs)_FMThe desired frequency of (c). F_y-1And F_yFor example corresponding to the frequencies F shown in fig. 3, respectively₁And F₂。

Table 1 illustrates 16 (i.e., 2n) state values for ring register link 7100 as an example of 8-bit indicating data Dstate (i.e., n-8), which in this example may comprise 4 stages of registers, each stage of registers corresponding to a corresponding 2 data bits in the indicating data. The ring register link 7100 cyclically outputs 16 state values indicating data Dstate in output logic order with 16 outputs as one cycle, and the 16 state values are sequentially numbered from 1 to 16 in order according to the output logic order of the ring register link 7100.

As can be seen from the above analysis, two adjacent clock edges in the second clock signal clk _ cs may define a detection interval, and a remainder obtained by dividing 16 by an expected number of times that the indication data Dstate is updated in the detection interval may be calculated to obtain a preset expected value a _ ref corresponding to the detection interval, where the preset expected value represents an ideal value of the difference Δ a calculated by the first determining unit 7230.

Based on this, the first determination unit 7230 may determine whether an offset amount a _ os between the difference Δ a (i.e., the measured value) and the preset desired value a _ ref is greater than a first threshold value. If so, it indicates that the deviation between the difference Δ a and the preset expected value a _ ref is too large and exceeds the allowable range determined by the first threshold, and the first determining unit 7230 may determine the first result value Sout [0] of the detection result data Sout]Set to an active state to indicate the first clock signal Sclk and the frequency modulated continuous wave signal S_FMIs not in the expected range, so that the first bit result value Sout [0] of the valid state can be used]Learning that the synthesizer and the radar system are in abnormal working states; if not, it indicates that the deviation between the difference Δ a and the preset expected value a _ ref is within the allowable range determined by the first threshold, and at this time, the first determining unit 7230 may determine the first result value Sout [0] of the detection result data Sout]Set to an invalid state to indicate the firstClock signal Sclk and frequency modulated continuous wave signal S_FMThe average value of the frequency of (1) in the detection interval satisfies a desired range, so that it is possible to obtain a first bit result value Sout [0] according to the invalid state]And the synthesizer and the radar system are in a normal working state.

As an alternative embodiment, the first judgment unit 7230 may include: a search module for searching the corresponding sequence numbers a1 and a2 in the storage unit 7220 according to the start value and the end value provided by the sampling unit 7210; the calculating module is used for calculating a difference value delta a according to the sequence numbers a1 and a2 and calculating the offset between the difference value delta a and a preset expected value a _ ref; a comparison module for comparing the offset with a first threshold to generate a first bit result value Sout [0 ].

Fig. 8 shows a schematic block diagram of yet another implementation of the processing circuit of fig. 4.

As a further optimized embodiment, as shown in fig. 8, the processing circuit 7200 may further include a second determination unit 7240 in addition to the sampling unit 7210, the storage unit 7220, and the first determination unit 7230 described in the above-described embodiment. The second determining unit 7240 is configured to provide a second bit result value Sout [1] in the detection result data Sout, so as to further provide detection result information of the modulated continuous wave signal.

As shown in FIG. 8, the second determining unit 7240 is configured to generate a second bit result value Sout [1] according to the first bit result value Sout [0], and the second determining unit 7240 includes a counter 7241 and a comparator 7242.

Wherein, the counter 7241 is used for outputting the first bit result value Sout [0]]A count num is provided. When the first bit result value Sout [0]]When the count value is in the valid state, the counter 7241 increments the count value num by 1; and when the first bit result value Sout [0] is received by the counter 7241]In the invalid state, the counter 7241 resets the count value num to the initial value. The count num may thus characterize the first bit result Sout [0]]Number of sampling cycles continuously characterising abnormal operating conditions, i.e. frequency-modulated continuous-wave signal S_FMIs continuously not in compliance with the preset frequency.

The comparator 7242 is configured to compare the count value num provided by the counter 7241 with a second threshold valuemax _ ref is compared to obtain a second bit result Sout [1]]. When the count num is greater than the second threshold max _ ref, the comparator 7242 outputs a second bit result Sout [1] of the valid state]To indicate the first clock signal Sclk and the fm continuous wave signal S_FMThe average value of the frequency in a plurality of continuous detection intervals/sampling periods which exceed the expected number does not meet the expected range, and at the moment, the synthesizer and the radar system are in an abnormal working state for a long time and are not easy to restore to normal automatically; when the count num is less than or equal to the second threshold max _ ref, the comparator 7242 outputs a second bit result Sout [1] of an invalid state]To characterize the first clock signal Sclk and the frequency modulated continuous wave signal S_FMIs expected to vary in frequency.

In alternative embodiments, the subsequent stage circuit connected to the comparator 7242 may be triggered by the second bit result value Sout [1] of the valid state to initiate an early warning prompt, which includes but is not limited to an audio prompt, a pop-up prompt, an optical prompt, and the like. When the second bit result value Sout [1] is in an invalid state, the post-stage circuit does not need to initiate early warning prompt.

The utility model also provides a detection device for judge first clock signal Sclk and frequency modulation continuous wave signal S as above-mentioned each embodiment_FMWhether the average value of the frequencies in the respective detection intervals meets the expected range. The radar system can be integrated in the same chip structure, for example, the chip structure is an Aip (packaged antenna) radar chip. In addition, the radio frequency signal transmitted by the radar chip can be a millimeter wave signal or other high frequency signal.

For example, for a synthesizer of a phase-locked loop structure, when the calculated offset is smaller than or equal to the first threshold, the detection apparatus and the radar system provided by the embodiment of the present invention may determine that the phase-locked loop structure is in a normal operating state, otherwise, the phase-locked loop structure is in an abnormal operating state; in order to improve the judgment accuracy, the judgment processing can be performed on the plurality of detection intervals respectively, and the phase-locked loop structure is judged to be in the normal working state only when the offsets of the detection intervals are smaller than or equal to the first threshold and the detection intervals show a certain regular change or a smaller change amplitude. Wherein, the judgment of the magnitude of the variation amplitude can be set based on the actual precision requirement.

In addition, to being in the phase-locked loop structure of abnormal operating condition, the embodiment of the utility model provides a detection device and radar system still can judge the change law of the different detection interval gained offsets through further analysis, confirm whether the phase-locked loop structure is in locking state or unstable state (namely in this application embodiment, abnormal operating condition can include locking state and unstable state). For example, when the offset obtained in adjacent sampling periods (corresponding to adjacent detection intervals) changes randomly or the change amplitude is large, it may be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, it may be considered that some devices in the phase-locked loop structure may be damaged at this time; otherwise, the phase-locked loop structure may be considered to be in a locked state in the abnormal state.

Fig. 9 shows a schematic flow chart of a detection method according to an embodiment of the present invention. Including steps S810 through S850. The method is applied to the detection device and the radar system of each of the above embodiments, for example.

In step S810, the frequency modulated continuous wave signal is down-converted and shaped to generate a first clock signal in the form of a square wave, and the frequency of the frequency modulated continuous wave signal is proportional to the frequency of the first clock signal. The frequency of the frequency modulated continuous wave signal varies linearly within the detection interval, and therefore the frequency of the first clock signal also varies linearly within the detection interval.

In step S820, indication data having a plurality of data bits is provided, and corresponding data bits in the indication data are updated according to clock edges of the first clock signal.

As an alternative embodiment, each rising edge and/or each falling edge of the first clock signal may be used as a clock edge for updating the indication data. Step S820 may include: circularly updating the value of each data bit of the indicating data under the triggering of each clock edge in turn; and updating a value indicative of a respective one of the data bits at the trigger of each clock edge.

In step S830, the indicating data is sampled based on the second clock signal to obtain a measurement value, and the detection result data is provided according to the measurement value. The measured value is controlled by the number of clock edges of the first clock signal in the detection interval, the detection result data represents whether the frequency of the frequency modulation continuous wave signal and the frequency of the first clock signal are normal or not, and the frequency of the second clock signal is smaller than the frequency of the first clock signal.

As an alternative embodiment, step S830 may include: sampling the indicating data based on a second clock signal to obtain a start value and an end value of the indicating data within a detection interval, the detection interval may correspond to one or more sampling periods of the second clock signal; obtaining a relation lookup table, wherein the relation lookup table is used for providing sequence numbers corresponding to a plurality of state values of the indicating data respectively in the output logic sequence, the plurality of state values of the indicating data comprise the starting value and the ending value, and the sequence numbers comprise a first sequence number corresponding to the starting value and a second sequence number corresponding to the ending value; obtaining a measured value according to a difference value between the first sequence number and the second sequence number; and judging whether the offset between the measured value and the preset expected value of the detection interval is larger than a first threshold value, if so, setting a first bit result value of the detection result data to be in an effective state to indicate that the average value of the frequency-modulated continuous wave signal in the detection interval does not meet the expected range, and if not, setting the first bit result value to be in an ineffective state to indicate that the average value of the frequency-modulated continuous wave signal in the detection interval meets the expected range.

As an alternative embodiment, step S830 may further include: and calculating to obtain a preset expected value based on the total number of the plurality of state values of the indicating data and the expected occurrence number of the clock edges of the first clock signal in the detection interval.

As an alternative embodiment, for each detection interval, the measured value may be equal to a difference value between the first sequence number and the second sequence number, and the preset expected value is equal to a remainder obtained by dividing twice a set value corresponding to the detection interval by a total number of a plurality of state values of the indicating data, where the set value is equal to a product between a preset frequency average value of the first clock signal in the detection interval and a duration of the detection interval.

As an alternative embodiment, in step S830, the step of providing the detection result data according to the measurement value may further include: providing a count value according to the first bit result value, adding 1 to the count value when the first bit result value is in an effective state, and restoring the count value to an initial value when the first bit result value is in an ineffective state; and judging whether the count value is larger than a second threshold value, if so, setting a second bit result value of the detection result data to be in an effective state to represent that the frequency change of the frequency modulation continuous wave signal is in an abnormal state, and if not, setting the second bit result value to be in an ineffective state to represent that the frequency change of the frequency modulation continuous wave signal is in a normal state.

It should be noted that the detection method provided by the embodiment of the present invention may include the technical details and features provided in the description of the detection device and the radar system of each embodiment, and the description of the same parts is omitted here for brevity.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A detection apparatus for a synthesizer, the synthesizer being configured to output a frequency modulated continuous wave signal, the detection apparatus comprising:

the input circuit is connected with the synthesizer to receive the frequency modulation continuous wave signal and performs frequency reduction and shaping processing on the frequency modulation continuous wave signal to generate a first clock signal in a square wave form, and the frequency of the first clock signal changes linearly in a detection interval;

a ring register link coupled to the input circuit to receive the first clock signal, configured to provide indicating data, and to update values of corresponding data bits in the indicating data according to respective clock edges of the first clock signal; and

processing circuitry, coupled to the ring register link, configured to: sampling the indicating data based on a second clock signal to obtain a measured value, and providing detection result data according to the measured value, wherein the detection result data represents whether the frequency of the frequency-modulated continuous wave signal is normal or not,

the frequency of the second clock signal is less than that of the first clock signal, and the measured value is controlled by the number of clock edges of the first clock signal occurring in the detection interval.

2. The detection apparatus according to claim 1, wherein for each of the detection intervals, the ring register link is configured to be adapted to:

circularly updating the value of each data bit of the indicating data under the triggering of each clock edge in turn; and

updating the value of a respective one of the data bits in the indicating data triggered by each of the clock edges.

3. The detection device of claim 1, wherein the processing circuit comprises:

a sampling unit, connected to the ring register link, for: sampling the indication data based on the second clock signal to obtain a start value and an end value of the indication data within a detection interval, wherein the detection interval corresponds to one or more sampling periods of the second clock signal;

a storage unit, configured to store a relationship lookup table in advance to indicate sequence numbers respectively corresponding to a plurality of state values of the indication data in an output logic sequence of the ring register link, where the plurality of state values include the start value and the end value, and the sequence numbers include a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; and

a first judging unit, configured to obtain the measurement value according to a difference between the first sequence number and the second sequence number, and judge whether an offset between the measurement value and a preset expected value of the detection interval is greater than a first threshold,

if so, the first judgment unit sets the first bit result value of the detection result data to be in an effective state to indicate that the average value of the frequency modulation continuous wave signal in the detection interval does not meet the expected range,

if not, the first judgment unit sets the first bit result value to be in an invalid state so as to indicate that the average value of the frequency modulation continuous wave signal in the detection interval meets the expected range.

4. The detection device according to claim 3, wherein the preset desired value is: calculating the obtained data value based on a total number of the plurality of state values and an expected number of occurrences of a clock edge of the first clock signal within the detection interval.

5. The detection apparatus according to claim 4, wherein for each of the detection intervals:

the measured value is equal to the difference value,

the preset expected value is equal to a remainder obtained by dividing twice of a set value corresponding to the detection interval by the total number of the plurality of state values,

the set value is equal to the product of the desired average value of the frequency of the first clock signal within the detection interval and the duration of the detection interval.

6. The detection device of claim 4, wherein the processing circuit further comprises:

a counter for providing a count value in accordance with the first bit result value, the counter being responsive to the first bit result value in an active state to increment the count value by 1 and responsive to the first bit result value in an inactive state to reset the count value to an initial value; and

a comparator for determining whether the count value is greater than a second threshold value,

if yes, the comparator sets a second bit result value of the detection result data to be in an effective state so as to represent that the frequency change of the frequency modulation continuous wave signal is in an abnormal state,

if not, the comparator sets the second bit result value to be in an invalid state so as to represent that the frequency change of the frequency modulation continuous wave signal is in a normal state.

7. The detection apparatus according to claim 1, wherein the synthesizer comprises:

and the phase-locked loop structure comprises a voltage-controlled oscillator, wherein the voltage-controlled oscillator generates the frequency-modulated continuous wave signal according to the frequency control voltage, and the frequency of the frequency-modulated continuous wave signal changes along with the voltage value of the frequency control voltage.

8. A radar system, comprising:

a detection apparatus and synthesizer according to any one of claims 1 to 7; and

and the radar transceiver provides a transmitting signal and/or processes an echo signal according to the frequency modulation continuous wave signal.

9. The radar system of claim 8, integrated in a same chip structure.

10. The radar system of claim 9, wherein the chip structure is an Aip radar chip.