CN202261236U - Phase-locked annular frequency synthesizer and programmable radiofrequency programmable frequency divider - Google Patents
Phase-locked annular frequency synthesizer and programmable radiofrequency programmable frequency divider Download PDFInfo
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Abstract
The utility model provides a phase-locked annular frequency synthesizer and a programmable radiofrequency programmable frequency divider, which comprise a reference oscillator, an R frequency divider, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator and a digital interface circuit and are characterized in that the radiofrequency input end of the programmable radiofrequency programmable frequency divider receives a radiofrequency signal output by the voltage controlled oscillator, the mode number control end of the programmable radiofrequency programmable frequency divider receives an encoding signal output by the digital interface circuit, the frequency division ratio of the programmable radiofrequency programmable frequency divider is determined by the encoding signal output by the digital interface circuit, and the received radiofrequency signal is treated by frequency division by the programmable radiofrequency programmable frequency divider and is output to the phase detector, wherein the programmable radiofrequency programmable frequency divider comprises n 2/3 frequency division units, n is a natural number larger than or equal to 2, and all the 2/3 frequency division units are in asynchronous serial connection. The phase-locked annular frequency synthesizer and a programmable radiofrequency programmable frequency divider have the advantages of simpleness in structure, low cost, small volume, low power consumption, excellent performance and flexibility and convenience in use and have good application prospect.
Description
Technical field
The utility model relates to frequency synthesizer, is specifically related to a kind of phase-locked ring type frequency synthesizer and radio frequency programmable frequency divider able to programme.
Background technology
The phase-locked ring type frequency synthesizer is a kind of vitals of in radio communication, being used widely, and it can also be used for completion and modulate, separate functions such as mediation carrier wave recovery as the local oscillated signal of various transceivers.Having comprised high-frequency model, low frequency module and digital circuit in the phase-locked ring type frequency synthesizer, is the D/A/radio frequency hybrid system of a complicacy.Shown in Figure 1 is existing phase-locked ring type frequency synthesizer system; The frequency characteristic of system is subject to high-frequency model---programmable frequency divider usually, and programmable frequency divider uses front end dual-mode frequency divider, M counter and A counter to realize with the frequency division scheme that gulps down pulse technique usually.In the prior art scheme, gulping down front end P/ (P+1) dual-mode frequency divider in the pulse programmable frequency divider has several kinds of frequency division moduluses such as 8/9,10/11,16/17,32/33,64/65 usually.When frequency division modulus value from 8/9 to 64/65; The structure of its circuit just becomes increasingly complex, the time delay of feedback signal is also increasing; Therefore; Along with the operating frequency of whole phase-locked ring type frequency synthesizer system improves constantly, the needed operating current of dual-mode frequency divider will increase greatly, thereby have the very big shortcoming of power consumption.And, very high when the RF application that is applied to GHz to the frequency characteristic requirement of front end dual-mode frequency divider, normally increase operating current and improve its operating frequency, thereby cause the total system power consumption very big.
The utility model content
One of the utility model technical problem to be solved is to provide a kind of phase-locked ring type frequency synthesizer.
Two of the utility model technical problem to be solved is to provide a kind of radio frequency programmable frequency divider able to programme that constitutes the phase-locked ring type frequency synthesizer.
In order to solve the problems of the technologies described above; First technical scheme of the utility model is; A kind of phase-locked ring type frequency synthesizer comprises reference oscillator, R frequency divider, phase discriminator, charge pump, loop filter, voltage controlled oscillator and digital interface circuit, is characterized in: the rf inputs of radio frequency programmable frequency divider able to programme receives the radiofrequency signal of voltage controlled oscillator output; The modulus control end receives the code signal of digital interface circuit output; And confirm the frequency dividing ratio of radio frequency programmable frequency divider able to programme by the code signal of digital interface circuit output, radio frequency programmable frequency divider able to programme carries out frequency division with the radiofrequency signal of receiving to be handled, and outputs to phase discriminator; Wherein:
Said radio frequency programmable frequency divider able to programme comprises n 2/3 frequency unit, and n is the natural number more than or equal to 2, and all 2/3 frequency units adopt asynchronous serial to connect.
What the utility model directly used that a radio frequency programmable frequency divider able to programme substitutes the prior art scheme gulps down the pulse programmable frequency divider, does not need M counter and A counter, makes the designs simplification of system, power consumption is very little, performance is more excellent.In the present technique scheme, the asynchronous serial frame mode that is based on 2/3 frequency unit that radio frequency programmable frequency divider able to programme adopts realizes that 2/3 frequency unit wherein is the minimum frequency unit of a frequency division modulus value in dual-mode frequency divider; So structure is the simplest; Low in energy consumption, and the radio frequency programmable frequency divider able to programme of the utility model is because 2/3 frequency units at different levels are asynchronous serial work; The first order 2/3 frequency unit has determined the maximum operating frequency of whole radio frequency programmable frequency divider able to programme; Along with frequency reduces step by step, can reduce operating current step by step, reduce the power consumption of system effectively.So, simplified system structure design effectively, greatly reduced the power consumption of total system.
A kind of preferred version according to the described a kind of phase-locked ring type frequency synthesizer of the utility model; The rf inputs of said radio frequency programmable frequency divider able to programme is provided with dc bias circuit and radio frequency buffering device; The radio frequency buffering device provides dc offset voltage by dc bias circuit; The radio frequency buffering device receives the radiofrequency signal of voltage controlled oscillator output, and after the radiofrequency signal that receives handled, outputs to 2/3 frequency unit.
The rf inputs of radio frequency programmable frequency divider able to programme is a pair of differential input end; Rf inputs at radio frequency programmable frequency divider able to programme is provided with dc bias circuit and radio frequency buffering device; Allow AC coupling input; Can single-ended input or the difference input drive, flexible and convenient to use, applied widely.
According to a kind of preferred version of the described a kind of phase-locked ring type frequency synthesizer of the utility model, each 2/3 frequency unit constitutes by d type flip flop DR1, DR2 and gate IC1, IC2, IC3; Wherein, The data input pin D1 of the first d type flip flop DR1, DN1 connect the first gate IC1 respectively with non-output and and output; The input of the first gate IC1 connects the second output Q2-of the second d type flip flop DR2; Another input of the first gate IC1 is the data input pin Din of 2/3 frequency unit; The first output Q1+ of the first d type flip flop DR1 connects the input of the second gate IC2; Another input of the second gate IC2 is the modulus control end M of 2/3 frequency unit; Receive the code signal of digital interface circuit output, the output of the second gate IC2 connects the input of the 3rd gate IC3, and another input of the 3rd gate IC3 connects the first output Q2+ of the second d type flip flop DR2; The data input pin D2 of the second d type flip flop DR2, DN2 connect the 3rd gate IC3 respectively with non-output and and output, the clock pulse input terminal C2 of the second d type flip flop DR2, CN2 connect clock pulse input terminal CN1, the C2 of the first d type flip flop DR1 respectively; Output Q2+, the Q2-of the second d type flip flop DR2 is respectively signal output part Qout, the Qout-of 2/3 frequency unit; Clock pulse input terminal C1, the CN1 of the first d type flip flop DR1 is respectively clock pulse input terminal CK+, the CK-of 2/3 frequency unit, and the second output Q1-of the first d type flip flop DR1 is the output Q-of 2/3 frequency unit.
Because the clock synchronization of two d type flip flops has the edge and triggers sensitive, the fast characteristics of upset speed, is easy to reach the purpose of radio frequency low-power consumption.
Second technical scheme of the utility model is; A kind of radio frequency programmable frequency divider able to programme that constitutes the phase-locked ring type frequency synthesizer; Be characterized in: radio frequency programmable frequency divider able to programme comprises n 2/3 frequency unit; N is the natural number more than or equal to 2, and all 2/3 frequency units adopt asynchronous serial to connect.
According to the described a kind of a kind of preferred version that constitutes the radio frequency programmable frequency divider able to programme of phase-locked ring type frequency synthesizer of the utility model; Said radio frequency programmable frequency divider able to programme also comprises dc bias circuit and radio frequency buffering device; By dc bias circuit dc offset voltage is provided; The radio frequency buffering device outputs to 2/3 frequency unit after the radiofrequency signal that receives is handled.
According to the described a kind of a kind of preferred version that constitutes the radio frequency programmable frequency divider able to programme of phase-locked ring type frequency synthesizer of the utility model, each 2/3 frequency unit constitutes by d type flip flop DR1, DR2 and gate IC1, IC2, IC3; Wherein, The data input pin of the first d type flip flop DR1 (D1, DN1) connect the first gate IC1 respectively with non-output and and output; The input of the first gate IC1 connects the second output Q2-of the second d type flip flop DR2; Another input of the first gate IC1 is the data input pin Din of 2/3 frequency unit; The first output Q1+ of the first d type flip flop DR1 connects the input of the second gate IC2; Another input of the second gate IC2 is the modulus control end M of 2/3 frequency unit; Receive the code signal of digital interface circuit output, the output of the second gate IC2 connects the input of the 3rd gate IC3, and another input of the 3rd gate IC3 connects the first output Q2+ of the second d type flip flop DR2; The data input pin D2 of the second d type flip flop DR2, DN2 connect the 3rd gate IC3 respectively with non-output and and output, the clock pulse input terminal C2 of the second d type flip flop DR2, CN2 connect clock pulse input terminal CN1, the C2 of the first d type flip flop DR1 respectively; Output Q2+, the Q2-of the second d type flip flop DR2 is respectively signal output part Qout, the Qout-of 2/3 frequency unit; Clock pulse input terminal C1, the CN1 of the first d type flip flop DR1 is respectively clock pulse input terminal CK+, the CK-of 2/3 frequency unit, and the second output Q1-of the first d type flip flop DR1 is the output Q-of 2/3 frequency unit.
The beneficial effect of described a kind of phase-locked ring type frequency synthesizer of the utility model and radio frequency programmable frequency divider able to programme is: what the utility model used directly that a radio frequency programmable frequency divider able to programme substitutes the prior art scheme gulps down the pulse programmable frequency divider, makes the designs simplification of system, power consumption is very little, performance is more excellent; Radio frequency programmable frequency divider able to programme adopts and realizes based on the asynchronous serial frame mode of 2/3 frequency unit; So structure is the simplest; Low in energy consumption; And the radio frequency programmable frequency divider able to programme of the utility model reduces the power consumption of system effectively because 2/3 frequency units at different levels are asynchronous serial work;
And,Rf inputs at radio frequency programmable frequency divider able to programme is provided with dc bias circuit and radio frequency buffering device, allows AC coupling input, can single-ended input or the difference input drive; Use flexibly, scope is wide, wherein; 2/3 frequency unit is made up of d type flip flop and gate; Because the clock synchronization of two d type flip flops has the edge and triggers sensitive, the fast characteristics of upset speed, is easy to reach the purpose of radio frequency low-power consumption; The utility model system configuration is simple, cost is low, volume is little, low in energy consumption, performance is excellent, uses flexibly, have a good application prospect.
Description of drawings
Fig. 1 is the theory diagram of existing phase-locked ring type frequency synthesizer system.
Fig. 2 is the theory diagram of the described a kind of phase-locked ring type frequency synthesizer of the utility model.
Fig. 3 is the schematic diagram of radio frequency programmable frequency divider able to programme.
Fig. 4 is the schematic diagram of 2/3 frequency unit circuit.
When Fig. 5 is specific embodiment n=6, the circuit theory diagrams of radio frequency programmable frequency divider able to programme.
Fig. 6 is at single-power voltage 3V, clock input range (V
CK+-V
CK-)=0.8V
P-PThe time, the I/O transient waveform of emulation.
Fig. 7 is the I/O waveform of 6 radio frequency programmable frequency divider simulating, verifyings able to programme.
Fig. 8 is that the radio-frequency input signals frequency is the radio frequency programmable frequency divider output phase noise curve able to programme of 3GHz.
Embodiment
Referring to Fig. 2 to Fig. 4; A kind of phase-locked ring type frequency synthesizer; Comprise reference oscillator 1, R frequency divider 2, phase discriminator 3, charge pump 4, loop filter 5, voltage controlled oscillator 6 and digital interface circuit 7; The rf inputs of radio frequency programmable frequency divider 8 able to programme receives the radiofrequency signal of voltage controlled oscillator 6 outputs, and the modulus control end receives the code signal of digital interface circuit 7 outputs, and confirms the frequency dividing ratio of radio frequency programmable frequency divider 8 able to programme by the code signal of digital interface circuit 7 outputs; Radio frequency programmable frequency divider 8 able to programme carries out frequency division with the radiofrequency signal of receiving to be handled, and outputs to phase discriminator 3; The reference clock of reference oscillator 1 output outputs to phase discriminator 3 after through R frequency divider 2 frequency divisions; The radiofrequency signal of voltage controlled oscillator 6 outputs outputs to phase discriminator 3 through behind radio frequency programmable frequency divider 8 frequency divisions able to programme, and after 3 pairs of signals of phase discriminator carried out phase discrimination processing, output voltage signal was to charge pump 4; Charge pump 4 outputs a control signal to loop filter 5; Control loop filter 5 carries out filtering, and loop filter 5 controlled voltages output to voltage controlled oscillator 6,6 work of control voltage controlled oscillator; Voltage controlled oscillator 6 carries out the voltage/frequency conversion, and frequency of oscillation is locked on the frequency that needs.
Said radio frequency programmable frequency divider 8 able to programme is by n 2/3 frequency unit 81,82,83 ... 8n
-1, 8n, dc bias circuit 812, radio frequency buffering device 811, logic voltage change-over circuit 813 and reverser 814 constitute, wherein, n be the natural number more than or equal to 2, all 2/3 frequency units adopt asynchronous serials connections; Be upper level 2/3 frequency unit with next stage 2/3 frequency unit between adopt asynchronous serial to be connected.Wherein, radio frequency buffering device 811 provides dc offset voltage by dc bias circuit 812, and radio frequency buffering device 811 receives the radiofrequency signal of voltage controlled oscillator 6 outputs; And after the radiofrequency signal that receives handled; Output to the first order 2/3 frequency unit 81, n 2/3 frequency unit carries out frequency division to the radiofrequency signal of receiving to be handled, and outputs to logic voltage change-over circuit 813; Simultaneously, n 2/3 frequency unit 81,82,83 ... 8n
-1, 8n receives the code signal of digital interface circuit 7 output respectively, and confirms frequency dividing ratio by the code signal of digital interface circuit 7 outputs; The fractional frequency signal amplitude that 813 pairs of logic voltage change-over circuits are received carries out outputing to phase discriminator 3 after the logic voltage conversion.
In specific embodiment; The clock pulse input terminal CK+ of the first order 2/3 frequency unit 81, CK-connect the output of radio frequency buffering device 811; The input of radio frequency buffering device 11 connects dc bias circuit 812, and connects the output of voltage controlled oscillator 6 simultaneously, and radio frequency buffering device 811 provides dc offset voltage by dc bias circuit 812; Radio frequency buffering device 811 receives the radiofrequency signal of voltage controlled oscillator 6 outputs, outputs to clock pulse input terminal CK+, the CK-of the first order 2/3 frequency unit after the processing; The data input pin Din of the first order 2/3 frequency unit 81 connects the output Q-of the second level 2/3 frequency unit 82; Signal output part Qout, the Qout-of the first order 2/3 frequency unit 81 connects clock pulse input terminal CK+, the CK-of the second level 2/3 frequency unit 82 respectively; And the like, the data input pin Din of n-1 level 2/3 frequency unit connects the output Q-of n level 2/3 frequency unit; The signal output part Qout of n-1 level 2/3 frequency unit, Qout-connect clock pulse input terminal CK+, the CK-of n level 2/3 frequency unit respectively, and clock pulse input terminal CK+, the CK-of n-1 level 2/3 frequency unit connect signal output part Qout, the Qout-of n-2 level 2/3 frequency unit; The output Q-of n-1 level 2/3 frequency unit connects the data input pin Din of n-2 level 2/3 frequency unit;
The data input pin Din of n level 2/3 frequency unit connects the output of inverter 814; The signal output part Qout of N level 2/3 frequency unit, Qout-connect the input of logic voltage change-over circuit 813 respectively; The input of inverter 814 connects power supply; The output of logic voltage change-over circuit 813 connects an input of phase discriminator 3.
The modulus control end M of the first order 2/3 frequency unit 81 to n level 2/3 frequency unit 8n connects the binary data output able to programme of digital interface circuit 7 respectively; The encoding state of binary data able to programme is directly confirmed the frequency dividing ratio N of radio frequency programmable frequency divider able to programme.
In specific embodiment, each 2/3 frequency unit constitutes by d type flip flop DR1, DR2 and gate IC1, IC2, IC3; Wherein, The data input pin D1 of the first d type flip flop DR1, DN1 receive the first gate IC1 respectively with non-output and with the signal of output output; The input of the first gate IC1 receives the signal of the second output Q2-output of the second d type flip flop DR2; Another input of the first gate IC1 is the data input pin Din of 2/3 frequency unit; The first output Q1+ output signal of the first d type flip flop DR1 is to the input of the second gate IC2; Another input of the second gate IC2 is the modulus control end M of 2/3 frequency unit; Receive the code signal of digital interface circuit 7 outputs, the input of second gate IC2 output signal to the, three gate IC3, another input of the 3rd gate IC3 receives the signal of the first output Q2+ output of the second d type flip flop DR2; The data input pin D2 of the second d type flip flop DR2, DN2 receive the 3rd gate IC3 respectively with non-output and with the signal of output output, the clock pulse input terminal C2 of the second d type flip flop DR2, CN2 are connected with clock pulse input terminal CN1, the C2 of the first d type flip flop DR1 respectively; Output Q2+, the Q2-of the second d type flip flop DR2 is respectively signal output part Qout, the Qout-of 2/3 frequency unit; Clock pulse input terminal C1, the CN1 of the first d type flip flop DR1 is respectively clock pulse input terminal CK+, the CK-of 2/3 frequency unit, and the second output Q1-of the first d type flip flop DR1 is the output Q-of 2/3 frequency unit.
In specific embodiment; The data input pin D1 of the first d type flip flop DR1, DN1 connect the first gate IC1 respectively with non-output and and output; The input of the first gate IC1 connects the second output Q2-of the second d type flip flop DR2; Another input of the first gate IC1 is the data input pin Din of 2/3 frequency unit; The first output Q1+ of the first d type flip flop DR1 connects the input of the second gate IC2; Another input of the second gate IC2 is the modulus control end M of 2/3 frequency unit; Receive the code signal of digital interface circuit 7 outputs, the output of the second gate IC2 connects the input of the 3rd gate IC3, and another input of the 3rd gate IC3 connects the first output Q2+ of the second d type flip flop DR2; The data input pin D2 of the second d type flip flop DR2, DN2 connect the 3rd gate IC3 respectively with non-output and and output, the clock pulse input terminal C2 of the second d type flip flop DR2, CN2 connect clock pulse input terminal CN1, the C2 of the first d type flip flop DR1 respectively; Output Q2+, the Q2-of the second d type flip flop DR2 is respectively signal output part Qout, the Qout-of 2/3 frequency unit; Clock pulse input terminal C1, the CN1 of the first d type flip flop DR1 is respectively clock pulse input terminal CK+, the CK-of 2/3 frequency unit, and the second output Q1-of the first d type flip flop DR1 is the output Q-of 2/3 frequency unit.
A kind of radio frequency programmable frequency divider able to programme that constitutes the phase-locked ring type frequency synthesizer, said radio frequency programmable frequency divider 8 able to programme is by n 2/3 frequency unit 81,82,83 ... 8n
-1, 8n, dc bias circuit 812 and radio frequency buffering device 811, logic voltage change-over circuit 813, reverser 814 constitute; Wherein, N is the natural number more than or equal to 2; All 2/3 frequency units adopt asynchronous serials to connect, and promptly the employing asynchronous serial is connected between upper level 2/3 frequency unit and next stage 2/3 frequency unit.
In specific embodiment; The clock pulse input terminal CK+ of the first order 2/3 frequency unit 81, CK-connect the output of radio frequency buffering device 811; The input of radio frequency buffering device 11 connects dc bias circuit 812, and connects the output of voltage controlled oscillator 6 simultaneously, and radio frequency buffering device (811) provides dc offset voltage by dc bias circuit (812); Radio frequency buffering device 811 receives the radiofrequency signal of voltage controlled oscillator 6 outputs, outputs to the first order 2/3 frequency unit 81 after the processing; The data input pin Din of the first order 2/3 frequency unit 81 connects the output Q-of the second level 2/3 frequency unit 82; Signal output part Qout, the Qout-of the first order 2/3 frequency unit 81 connects clock pulse input terminal CK+, the CK-of the second level 2/3 frequency unit 82 respectively; And the like, the data input pin Din of n-1 level 2/3 frequency unit 8n-1 connects the output Q-of n level 2/3 frequency unit 8n; Clock pulse input terminal CK+, CK-that the signal output part Qout of n-1 level 2/3 frequency unit 8n-1, Qout-connect n level 2/3 frequency unit 8n respectively, clock pulse input terminal CK+, the CK-of n-1 level 2/3 frequency unit 8n-1 connect signal output part Qout, the Qout-of n-2 level 2/3 frequency unit; The output Q-of n-1 level 2/3 frequency unit 8n-1 connects the data input pin Din of n-2 level 2/3 frequency unit;
The data input pin Din of n level 2/3 frequency unit 8n connects the output of inverter 814; The input that the signal output part Qout of n level 2/3 frequency unit 8n, Qout-connect logic voltage change-over circuit 813 respectively; The input MT of inverter 814 is digital input ends of highest order, is set to the logical one level usually; The output of logic voltage change-over circuit connects an input of phase discriminator 3.And the output OUT of logic voltage change-over circuit and the input MT of inverter 814 design are compatible with the CMOS level, can be connected in series with the CMOS program divider of low-power consumption, can conveniently constitute the more radio frequency programmable frequency divider able to programme of seniority top digit.
The modulus control end M of the first order 2/3 frequency unit to the n level 2/3 frequency unit connects the binary data output able to programme of digital interface circuit 7 respectively; The encoding state of binary data able to programme is directly confirmed the frequency dividing ratio N of whole radio frequency programmable frequency divider able to programme.
In specific embodiment, each 2/3 frequency unit constitutes by d type flip flop DR1, DR2 and gate IC1, IC2, IC3; Wherein, The data input pin D1 of the first d type flip flop DR1, DN1 connect the first gate IC1 respectively with non-output and and output; The input of the first gate IC1 connects the second output Q2-of the second d type flip flop DR2; Another input of the first gate IC1 is the data input pin Din of 2/3 frequency unit; The first output Q1+ of the first d type flip flop DR1 connects the input of the second gate IC2; Another input of the second gate IC2 is the programmable data input M of 2/3 frequency unit; Receive the code signal of digital interface circuit 7 outputs, the output of the second gate IC2 connects the input of the 3rd gate IC3, and another input of the 3rd gate IC3 connects the first output Q2+ of the second d type flip flop DR2; The data input pin of the second d type flip flop DR2 (D2, DN2) connect the 3rd gate IC3 respectively with non-output and and output, the clock pulse input terminal C2 of the second d type flip flop DR2, CN2 connect clock pulse input terminal CN1, the C2 of the first d type flip flop DR1 respectively; Output Q2+, the Q2-of the second d type flip flop DR2 is respectively signal output part Qout, the Qout-of 2/3 frequency unit; Clock pulse input terminal C1, the CN1 of the first d type flip flop DR1 is respectively clock pulse input terminal CK+, the CK-of 2/3 frequency unit, and the second output Q1-of the first d type flip flop DR1 is the output Q-of 2/3 frequency unit.
2/3 frequency unit is the minimum frequency unit of a frequency division modulus value in dual-mode frequency divider, so structure is the simplest; When data terminal Din was set to logical zero, modulus control end M=" 0 " realized ÷ 2 functions, and modulus control end M=" 1 " realizes ÷ 3 functions.2/3 frequency unit division function is seen table 1.
Table 1 2/3 frequency unit division function
| Modulus control end M | Frequency division ratio | Explanation |
| 0 | 2 | Q
OUTOutput frequency equals 1/2 of |
| 1 | 3 | Q OUTOutput frequency equals 1/3 of CK clock frequency |
Simulation results shows: the operation of 2/3 frequency unit circuit function is correct, at single-power voltage 3V, clock input range V
CK+-V
CK-=0.8V
P-PThe time, the I/O transient waveform of emulation is seen shown in Figure 6, and, read from simulator, up to when the 3.4GHz, operating current has only 1.6mA in operating frequency.
Referring to Fig. 5; Fig. 5 is the circuit theory diagrams of 6 bit string level types radio frequency programmable frequency divider able to programme; Said 6 bit string level types radio frequency programmable frequency divider able to programme is by 6 2/3 frequency units 81,82,83 ... 86, dc bias circuit 812 and radio frequency buffering device 811, logic voltage change-over circuit 813, reverser 814 constitute, and 2/3 frequency unit 81～86 adopts asynchronous serial to connect, and the clock of 2/3 frequency units at different levels is asynchronous workings; The first order 2/3 frequency unit 81 has determined the maximum operating frequency of whole programmable frequency divider; Along with frequency reduces step by step, can reduce operating current step by step, reduce the power consumption of integrated circuit effectively.
M0～M5 connects the binary data output able to programme of digital interface circuit 7, with the CMOS logical consistency.M0 is a lowest order, and M5 is a highest order, and the binary coding state of M0～M5 has directly determined the frequency division ratio of radio frequency programmable frequency divider able to programme.
Work as M5 ... When M0 was " 000000 " state, 6 2/3 frequency units are ÷ 2 all, and promptly the frequency dividing ratio of 6 grades of cascade arrangements is 2
6=64; Work as M5 ... The binary coding state of M0 is when " 000000 " changes to " 111111 " successively, and corresponding decimal value is 0～63.So the scope of total frequency dividing ratio value of this radio frequency programmable frequency divider able to programme is 64～127, sees table 2.
Input of table 2 binary coding and frequency division ratio correspondence table
Fig. 7 has provided the I/O waveform of 6 radio frequency programmable frequency divider simulating, verifyings able to programme, and 7A is that frequency is the radio-frequency input signals waveform of 3.0GHz; 7B is that N=64 is M5 ... Output waveform during M0=" 000000 "; 7C is that N=127 is M5 ... Output waveform during M0=" 111111 ".Can know that by Fig. 7 the feature operation of circuit is correct.
It is the programmable frequency divider output phase noise curve of 3GHz that Fig. 8 has provided the radio-frequency input signals frequency.Can know that by Fig. 8 the phase noise of 10KHz frequency deviation is-133.5dBc/Hz that the phase noise of 100KHz frequency deviation is-143dBc/Hz.
In radio-frequency input signals frequency 3.0GHz, input signal power-5dBm～5dBm scope, the feature operation of radio frequency programmable frequency divider able to programme is all correct.Under the 3V operating voltage, the total current that circuit consumed has only 4mA, and power consumption is 12mW only.Gulp down the pulse programmable frequency divider and compare with existing, not only the structure of system obtains simplifying, and the overall operation electric current can be reduced to 1/3 of former scheme simultaneously.
In sum, adopt the radio frequency programmable frequency divider able to programme of the utility model, simplified system structure design in original scheme effectively, greatly reduced the power consumption of total system.
Embodiment to the utility model is described above, still, and the scope that is not limited only to embodiment of the utility model protection.
Claims (6)
1. phase-locked ring type frequency synthesizer; Comprise reference oscillator (1), R frequency divider (2), phase discriminator (3), charge pump (4), loop filter (5), voltage controlled oscillator (6) and digital interface circuit (7); It is characterized in that: the rf inputs of radio frequency programmable frequency divider able to programme (8) receives the radiofrequency signal of voltage controlled oscillator (6) output; The modulus control end receives the code signal of digital interface circuit (7) output; And confirm the frequency dividing ratio of radio frequency programmable frequency divider able to programme (8) by the code signal of digital interface circuit (7) output; Radio frequency programmable frequency divider able to programme (8) carries out frequency division with the radiofrequency signal of receiving to be handled, and outputs to phase discriminator (3); Wherein:
Said radio frequency programmable frequency divider able to programme (8) comprises n 2/3 frequency unit, and wherein, n is the natural number more than or equal to 2, and all 2/3 frequency units adopt asynchronous serial to connect.
2. a kind of phase-locked ring type frequency synthesizer according to claim 1; It is characterized in that: the rf inputs of said radio frequency programmable frequency divider able to programme (8) is provided with dc bias circuit (812) and radio frequency buffering device (811); Radio frequency buffering device (811) provides dc offset voltage by dc bias circuit (812); Radio frequency buffering device (811) receives the radiofrequency signal of voltage controlled oscillator (6) output, and after the radiofrequency signal that receives handled, outputs to 2/3 frequency unit.
3. a kind of phase-locked ring type frequency synthesizer according to claim 1 and 2 is characterized in that: each 2/3 frequency unit constitutes by d type flip flop (DR1, DR2) and gate (IC1, IC2, IC3); Wherein, The data input pin of first d type flip flop (DR1) (D1, DN1) receive first gate (IC1) respectively with non-output and with the signal of output output; An input of first gate (IC1) receives the signal of second output (Q2-) output of second d type flip flop (DR2); Another input of first gate (IC1) is the data input pin (Din) of 2/3 frequency unit; First output (Q1+) the output signal of first d type flip flop (DR1) is to an input of second gate (IC2); Another input of second gate (IC2) is the modulus control end (M) of 2/3 frequency unit; Receive the code signal of digital interface circuit (7) output; An input of second gate (IC2) output signal to the three gates (IC3); Another input of the 3rd gate (IC3) receives the signal of first output (Q2+) output of second d type flip flop (DR2), the data input pin of second d type flip flop (DR2) (D2, DN2) receive the 3rd gate (IC3) respectively with non-output and with the signal of output output, the clock pulse input terminal of second d type flip flop (DR2) (C2, CN2) is connected with the clock pulse input terminal (CN1, C2) of first d type flip flop (DR1) respectively; The output of second d type flip flop (DR2) (Q2+, Q2-) is respectively the signal output part (Qout, Qout-) of 2/3 frequency unit; The clock pulse input terminal of the first d type flip flop DR1 (C1, CN1) is respectively the clock pulse input terminal (CK+, CK-) of 2/3 frequency unit, and second output (Q1-) of first d type flip flop (DR1) is the output (Q-) of 2/3 frequency unit.
4. radio frequency programmable frequency divider able to programme that constitutes the phase-locked ring type frequency synthesizer; It is characterized in that: radio frequency programmable frequency divider able to programme (8) comprises n 2/3 frequency unit; Wherein, n is the natural number more than or equal to 2, and all 2/3 frequency units adopt asynchronous serial to connect.
5. a kind of radio frequency programmable frequency divider able to programme that constitutes the phase-locked ring type frequency synthesizer according to claim 4; It is characterized in that: said radio frequency programmable frequency divider able to programme (8) also comprises dc bias circuit (812) and radio frequency buffering device (811); Radio frequency buffering device (811) provides dc offset voltage by dc bias circuit (812); After the radiofrequency signal that receives handled, output to 2/3 frequency unit.
6. a kind of radio frequency programmable frequency divider able to programme that constitutes the phase-locked ring type frequency synthesizer according to claim 5 is characterized in that: each 2/3 frequency unit constitutes by d type flip flop (DR1, DR2) and gate (IC1, IC2, IC3); Wherein, The data input pin of first d type flip flop (DR1) (D1, DN1) receive first gate (IC1) respectively with non-output and with the signal of output output; An input of first gate (IC1) receives the signal of second output (Q2-) output of second d type flip flop (DR2); Another input of first gate (IC1) is the data input pin (Din) of 2/3 frequency unit; First output (Q1+) the output signal of first d type flip flop (DR1) is to an input of second gate (IC2); Another input of second gate (IC2) is the modulus control end (M) of 2/3 frequency unit; Receive the code signal of digital interface circuit (7) output; An input of second gate (IC2) output signal to the three gates (IC3); Another input of the 3rd gate (IC3) receives the signal of first output (Q2+) output of second d type flip flop (DR2), the data input pin of second d type flip flop (DR2) (D2, DN2) receive the 3rd gate (IC3) respectively with non-output and with the signal of output output, the clock pulse input terminal of second d type flip flop (DR2) (C2, CN2) is connected with the clock pulse input terminal (CN1, C2) of first d type flip flop (DR1) respectively; The output of second d type flip flop (DR2) (Q2+, Q2-) is respectively the signal output part (Qout, Qout-) of 2/3 frequency unit; The clock pulse input terminal of the first d type flip flop DR1 (C1, CN1) is respectively the clock pulse input terminal (CK+, CK-) of 2/3 frequency unit, and second output (Q1-) of first d type flip flop (DR1) is the output (Q-) of 2/3 frequency unit.
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| CN2011203940044U CN202261236U (en) | 2011-10-17 | 2011-10-17 | Phase-locked annular frequency synthesizer and programmable radiofrequency programmable frequency divider |
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| CN2011203940044U CN202261236U (en) | 2011-10-17 | 2011-10-17 | Phase-locked annular frequency synthesizer and programmable radiofrequency programmable frequency divider |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102394642A (en) * | 2011-10-17 | 2012-03-28 | 重庆西南集成电路设计有限责任公司 | Phase-locked loop type frequency synthesizer and radio frequency program-controlled frequency divider |
| CN110011673A (en) * | 2017-12-29 | 2019-07-12 | 德州仪器公司 | Radiofrequency launcher based on digimigration frequency generator |
-
2011
- 2011-10-17 CN CN2011203940044U patent/CN202261236U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102394642A (en) * | 2011-10-17 | 2012-03-28 | 重庆西南集成电路设计有限责任公司 | Phase-locked loop type frequency synthesizer and radio frequency program-controlled frequency divider |
| CN102394642B (en) * | 2011-10-17 | 2013-09-18 | 重庆西南集成电路设计有限责任公司 | Phase-locked loop type frequency synthesizer and radio frequency program-controlled frequency divider |
| CN110011673A (en) * | 2017-12-29 | 2019-07-12 | 德州仪器公司 | Radiofrequency launcher based on digimigration frequency generator |
| US11206051B2 (en) | 2017-12-29 | 2021-12-21 | Texas Instruments Incorporated | Digital offset frequency generator based radio frequency transmitter |
| CN110011673B (en) * | 2017-12-29 | 2022-09-30 | 德州仪器公司 | Radio frequency transmitter based on digital offset frequency generator |
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