CN203608181U - Frequency synthesizer - Google Patents
Frequency synthesizer Download PDFInfo
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- CN203608181U CN203608181U CN201320804314.8U CN201320804314U CN203608181U CN 203608181 U CN203608181 U CN 203608181U CN 201320804314 U CN201320804314 U CN 201320804314U CN 203608181 U CN203608181 U CN 203608181U
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- 238000004891 communication Methods 0.000 abstract description 8
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- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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Abstract
The utility model discloses a frequency synthesizer comprising a low-phase noise constant temperature crystal oscillator which is connected with a first PLL phase-locked loop chip. The low-phase noise constant temperature crystal oscillator is connected with a second PLL phase-locked loop chip. The frequency synthesizer also comprises an FPGA and an either-or switch. The FPGA is connected with the first PLL phase-locked loop chip and outputs a control signal to the first PLL phase-locked loop chip. The FPGA is connected with the second PLL phase-locked loop chip and outputs the control signal to the second PLL phase-locked loop chip. The FPGA is connected with the either-or switch. Requirements of high stray suppression degree, high-speed frequency switching, low power consumption and small volume can be realized simultaneously so that a high-quality signal source is provided for radar and communication systems and thus overall performance of the radar and communication systems is enhanced.
Description
Technical field
The utility model relates to a kind of frequency synthesizer, is specifically related to a kind of high-purity frequency synthesizer.
Background technology
As benchmark, can produce a series of high definition frequency sources with certain frequency interval by synthetic technology with high-precision crystal oscillator, divide directly synthetic and phase-locked loop to synthesize two kinds.Frequency source is frequency synthesizer, is the important component part of contemporary electronic systems, is called as " heart " of many electronic systems.In the equipment such as communication, radar and navigation, it is the exciting signal source of transmitter, is again the local oscillator of receiver; In testing equipment, it can be used as standard signal source.Along with the development of modern electrical and electronic technology, people are more and more higher to the requirement of frequency source, and the frequency source of performance brilliance is all realized by the technology of frequency synthesis.
The main performance index of frequency source is: the purity (being noise restraint) of frequency spectrum, phase noise, frequency switching time etc.The low frequency source spuious and that fast frequency switches of high-purity is the difficult point of design and development.The performance index of frequency source directly produce basic impact to the overall performance of radar system and communication system.Traditional frequency source scheme all can not meet high noise restraint and the index of fast frequency switching and the requirement of low power consumption and small volume simultaneously at present, and the overall performance of radar and communication system is impacted.
Utility model content
The utility model has overcome the deficiencies in the prior art, a kind of frequency synthesizer is provided, can not meet high noise restraint and the index of fast frequency switching and the requirement of low power consumption and small volume to prior art medium frequency synthesizer to be solved, to problems such as the overall performance of radar and communication system impact simultaneously.
For solving above-mentioned technical problem, the utility model by the following technical solutions:
A kind of frequency synthesizer, comprises low phase noise constant-temperature crystal oscillator; Described low phase noise constant-temperature crystal oscillator connects a PLL phase-locked loop chip, and described low phase noise constant-temperature crystal oscillator connects the 2nd PLL phase-locked loop chip; Described frequency synthesizer also comprises that FPGA, 2 selects 1 switch; Described FPGA is connected with a described PLL phase-locked loop chip, and described FPGA is to a described PLL phase-locked loop chip output control signal; Described FPGA is connected with described the 2nd PLL phase-locked loop chip, and described FPGA is to described the 2nd PLL phase-locked loop chip output control signal; Described FPGA and described 2 selects 1 switch to be connected; A described PLL phase-locked loop chip connects the first loop filter circuit, and described the first loop filter circuit connects the first voltage controlled oscillator, and described the first voltage controlled oscillator connects the first isolating amplifier circuit, and described the first isolating amplifier circuit connects 2 and selects 1 switch; Described the 2nd PLL phase-locked loop chip connects the second loop filtering circuit, and described the second loop filtering circuit connects the second voltage controlled oscillator, and described the second voltage controlled oscillator connects the second isolating amplifier circuit, and described the second isolating amplifier circuit connects 2 and selects 1 switch.
Further technical scheme is that described FPGA is connected by Le, Data, Clk tri-lines with a described PLL phase-locked loop chip.
Further technical scheme is that the described phase-locked chip of a PLL is identical with the phase-locked chip of described the 2nd PLL.
Further technical scheme is that the described phase-locked chip of a PLL is identical running time with the phase-locked chip of described the 2nd PLL.
Further technical scheme is that described 2 to select 1 switch be single-pole double-throw switch (SPDT).
Compared with prior art, the beneficial effects of the utility model are: the utility model can realize high noise restraint simultaneously and fast frequency switches and the requirement of low power consumption and small volume, for radar and communication system provide high-quality signal source, thereby promote the overall performance of radar and communication system.
Accompanying drawing explanation
Fig. 1 is the theory diagram of an embodiment of the utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further elaborated.
As shown in Figure 1, Fig. 1 shows the theory diagram of an embodiment of the utility model, and the present embodiment frequency synthesizer comprises 100MHz low phase noise constant-temperature crystal oscillator; 100MHz low phase noise constant-temperature crystal oscillator connects a PLL phase-locked loop chip, and MHz low phase noise constant-temperature crystal oscillator connects the 2nd PLL phase-locked loop chip; The present embodiment frequency synthesizer also comprises that FPGA, 2 selects 1 switch, and specific embodiment is, in the present embodiment, 2 to select 1 switch can be single-pole double-throw switch (SPDT), can be being also used in combination of single-pole single-throw switch (SPST) and single-pole double-throw switch (SPDT); FPGA is connected with a PLL phase-locked loop chip, and FPGA is connected by Le, Data, Clk tri-lines with a PLL phase-locked loop chip, and FPGA is to a PLL phase-locked loop chip output control signal; FPGA is connected with the 2nd PLL phase-locked loop chip, and FPGA is connected by Le, Data, Clk tri-lines with the 2nd PLL phase-locked loop chip.FPGA is to the 2nd PLL phase-locked loop chip output control signal; FPGA and 2 selects 1 switch to be connected; The one PLL phase-locked loop chip connects the first loop filter circuit, and the first loop filter circuit connects the first voltage controlled oscillator, and the first voltage controlled oscillator connects the first isolating amplifier circuit, and the first isolating amplifier circuit connects 2 and selects 1 switch; The 2nd PLL phase-locked loop chip connects the second loop filtering circuit, and the second loop filtering circuit connects the second voltage controlled oscillator, and the second voltage controlled oscillator connects the second isolating amplifier circuit, and the second isolating amplifier circuit connects 2 and selects 1 switch.Wherein the first loop filter circuit is consistent with the second loop filtering circuit, the first voltage controlled oscillator is consistent with the first voltage controlled oscillator, the first isolating amplifier circuit is consistent with the second isolating amplifier circuit, and parameter and the device of a PLL phase-locked loop chip and the 2nd PLL phase-locked loop chip are in full accord.The present embodiment has adopted two traditional PLL phase-locked loops to carry out the frequency of phase-locked generation similar frequency bands, and parameter and the device of two PLL phase-locked loops are in full accord.In the present embodiment, PLL phase-locked loop chip can adopt the ADF4106 chip of integral frequency divisioil; Utilize one 2 and select 1 switch to carry out the selection of output frequency to switch.Two PLL phase-locked loops, for work simultaneously, have utilized the advantage of switch energy high speed switching channel, and the high speed that has realized frequency is switched.Because the spuious index of traditional digital phase-locked loop can be accomplished higher level, and its volume and power consumption all can be accomplished very little.So the present embodiment has high noise restraint and fast frequency switches and the advantage of low power consumption and small volume.The operation principle of the phase-locked loop part of the present embodiment is consistent with traditional digital phase-locked loop operation principle.Principle is: adopt the constant-temperature crystal oscillator of the low phase noise of a 100MHz to provide phase-locked needed reference clock signal for PLL digital phase-locked loop chip.VCO is voltage controlled oscillator, produces the free oscillation signal needing in frequency range, and the reference clock signal that Fen Yilu feeds back to phase-locked loop chip and 100MHz carries out phase demodulation.The parameter settings such as concrete frequency step, reference frequency output and phase demodulation frequency are the configuration to PLL digital phase-locked loop chip by realization by FPGA, FPGA receives after parallel frequency hopping control code, phase-locked loop chip is configured, makes it carry out work by the requirement of frequency hopping control code.The signal that the clock signal of 100MHz and VCO are voltage controlled oscillator carries out after phase demodulation at PLL chip internal, by PLL chip output phase error electric current, be in the frequency that the Frequency Locking of the spuious rear control VCO of loop filter filtering phase demodulation requires at frequency hopping control code by LF.Thereby obtain the signal that can be controlled by frequency hopping control code.
When the present embodiment frequency synthesizer works on power, FPGA controls two digital phase-locked loops and works simultaneously, and produces the output frequency that parallel frequencies control code is controlled, and FPGA also controls 2 and selects the wherein signal output of any one phase-locked loop of 1 switch acquiescence selection simultaneously.The not selected digital phase-locked loop of exporting of another one just can be undertaken preset by outside control.Its preset mode is: initialize switch S0 is set high to level, frequency hopping control code is preset on the Frequency point needing simultaneously, now the output frequency of the digital phase-locked loop of selected output has not jumped on preset Frequency point.Because S0 sets high level, FPGA does not change configuration to the phase-locked loop frequency of selecting output.In the time that needs frequency is switched, S0 is set low to level, change the logic level of S1 simultaneously, make switch select the preset digital phase-locked loop output completing.S0 can be set high to level again at this moment, change frequency hopping control code simultaneously and carry out the preset of next frequency.Cyclically carry out thus preset and switching frequency.
The control of frequency and the control of switch have all adopted high-speed programmable logical circuit FPGA, therefore its time can be accomplished ns magnitude, owing to having adopted the preset working method of Double-number phase-locked loop " table tennis ", next frequency is the preset generation of institute in the time of another phase-locked loop operation, and this just does not need to consider the locking time of single phase-locked loop.And only depend on the select time of switch the switching time of two frequencies.And the select time of switch can reach ns magnitude, so adopt this kind of scheme, frequency switching time can be accomplished below 1 μ s.Realize the function that fast frequency switches.
" embodiment ", " another embodiment ", " embodiment " that spoken of in this manual, etc., refer to specific features, structure or the feature described in conjunction with this embodiment and be included at least one embodiment that the application's generality describes.In specification, multiple local appearance statement of the same race is not necessarily to refer to same embodiment.Furthermore, while describing a specific features, structure or feature in conjunction with any embodiment, what advocate is to realize this feature, structure or feature in conjunction with other embodiment also to drop in scope of the present utility model.
Although the utility model is described with reference to the multiple explanatory embodiment of utility model here, but, should be appreciated that, those skilled in the art can design a lot of other modification and execution modes, and these are revised and within execution mode will drop on the disclosed principle scope and spirit of the application.More particularly, in the scope of, accompanying drawing open in the application and claim, can carry out multiple modification and improvement to the building block of subject combination layout and/or layout.Except modification that building block and/or layout are carried out with improving, to those skilled in the art, other purposes will be also obvious.
Claims (5)
1. a frequency synthesizer, comprises low phase noise constant-temperature crystal oscillator; It is characterized in that: described low phase noise constant-temperature crystal oscillator connects a PLL phase-locked loop chip, described low phase noise constant-temperature crystal oscillator connects the 2nd PLL phase-locked loop chip; Described frequency synthesizer also comprises that FPGA, 2 selects 1 switch; Described FPGA is connected with a described PLL phase-locked loop chip, and described FPGA is to a described PLL phase-locked loop chip output control signal; Described FPGA is connected with described the 2nd PLL phase-locked loop chip, and described FPGA is to described the 2nd PLL phase-locked loop chip output control signal; Described FPGA and described 2 selects 1 switch to be connected; A described PLL phase-locked loop chip connects the first loop filter circuit, and described the first loop filter circuit connects the first voltage controlled oscillator, and described the first voltage controlled oscillator connects the first isolating amplifier circuit, and described the first isolating amplifier circuit connects 2 and selects 1 switch; Described the 2nd PLL phase-locked loop chip connects the second loop filtering circuit, and described the second loop filtering circuit connects the second voltage controlled oscillator, and described the second voltage controlled oscillator connects the second isolating amplifier circuit, and described the second isolating amplifier circuit connects 2 and selects 1 switch.
2. frequency synthesizer according to claim 1, is characterized in that described FPGA is connected by Le, Data, Clk tri-lines with a described PLL phase-locked loop chip.
3. frequency synthesizer according to claim 1, is characterized in that the described phase-locked chip of a PLL is identical with the phase-locked chip of described the 2nd PLL.
4. according to the frequency synthesizer described in claim 1 or 3, it is characterized in that the described phase-locked chip of a PLL is identical running time with the phase-locked chip of described the 2nd PLL.
5. frequency synthesizer according to claim 1, it is single-pole double-throw switch (SPDT) that 2 described in it is characterized in that selected 1 switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320804314.8U CN203608181U (en) | 2013-12-09 | 2013-12-09 | Frequency synthesizer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320804314.8U CN203608181U (en) | 2013-12-09 | 2013-12-09 | Frequency synthesizer |
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| CN203608181U true CN203608181U (en) | 2014-05-21 |
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| CN201320804314.8U Expired - Lifetime CN203608181U (en) | 2013-12-09 | 2013-12-09 | Frequency synthesizer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104202047A (en) * | 2014-08-22 | 2014-12-10 | 武汉中元通信股份有限公司 | Monolithic integration frequency synthesizer based on VHF (very high frequency) band |
| CN104320135A (en) * | 2014-11-03 | 2015-01-28 | 成都赛英科技有限公司 | High-purity frequency source |
| CN105406862A (en) * | 2015-12-07 | 2016-03-16 | 扬州海科电子科技有限公司 | Low stray broadband 10-20GHz phase lock loop device |
-
2013
- 2013-12-09 CN CN201320804314.8U patent/CN203608181U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104202047A (en) * | 2014-08-22 | 2014-12-10 | 武汉中元通信股份有限公司 | Monolithic integration frequency synthesizer based on VHF (very high frequency) band |
| CN104320135A (en) * | 2014-11-03 | 2015-01-28 | 成都赛英科技有限公司 | High-purity frequency source |
| CN105406862A (en) * | 2015-12-07 | 2016-03-16 | 扬州海科电子科技有限公司 | Low stray broadband 10-20GHz phase lock loop device |
| CN105406862B (en) * | 2015-12-07 | 2019-01-08 | 扬州海科电子科技有限公司 | A kind of low spurious broadband 10~20GHz phase-locked loop apparatus |
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Granted publication date: 20140521 |