CN204103898U - A kind of frequency synthesizer - Google Patents
A kind of frequency synthesizer Download PDFInfo
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- CN204103898U CN204103898U CN201420538822.0U CN201420538822U CN204103898U CN 204103898 U CN204103898 U CN 204103898U CN 201420538822 U CN201420538822 U CN 201420538822U CN 204103898 U CN204103898 U CN 204103898U
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Abstract
The utility model relates to a kind of frequency synthesizer.This frequency synthesizer comprises the first variable division phase discriminator, first ring path filter, the second variable division phase discriminator, the second loop filter, loop selector switch, the first voltage controlled oscillator, the first splitter, amplifilter, frequency mixer, constant-temperature crystal oscillator, the 3rd splitter, the 3rd variable division phase discriminator, Three links theory filter, the second voltage controlled oscillator and the second splitter.Frequency synthesizer of the present utility model, by adopting double loop mixing Phase Lock Technique, can reduce the phase noise outputed signal when broadband exports.Meanwhile, frequency synthesizer of the present utility model, by the preset VCO technology of phase-locked loop, ensure that phase-locked loop correctly locks, and decreases the loop-locking time.
Description
Technical field
The utility model relates to the communications field, particularly relates to a kind of frequency synthesizer.
Background technology
At present, in the field of wireless communication, the frequency synthesizer used in Receiver And Transmitter all adopts frequency synthesis mode to realize.The spectral purity of frequency synthesizer signal, is directly connected to the dynamic range of receiver and the spectral purity of transmitter.Along with the increase of communication system working band, the working frequency range of required frequency synthesizer is also in corresponding increase.
Nominal frequencies synthesis mode has direct modeling synthetic method, phase-locked loop synthetic method and direct digital synthesizers (Direct Digital Synthesis is called for short DDS).Direct modeling synthetic method frequency switching time is fast, phase noise good, but adopts the volume of the frequency synthesizer of direct modeling synthetic method, power consumption larger.Phase-locked loop synthetic method completes the adding of frequency by phase-locked loop, subtracts, multiplication and division computing.The frequency synthesizer architecture of employing phase-locked loop synthetic method simplifies, volume is little.The phase noise of phase-locked loop synthetic method is except the impact being subject to reference signal, also relevant with phase discriminator and frequency dividing ratio.The frequency synthesizer conversion speed of direct digital synthesizers method is very fast, but direct digital synthesizers is subject to the restriction of the operating frequency of digital to analog converter (Digital to Analog Converter is called for short DAC), and its output frequency is also restricted.
Consider the factor such as complexity, volume, power consumption size of phase noise, spuious, frequency range, realization, phase-locked loop synthetic method is when volume, power consumption are smaller, in the frequency range of relative narrower, good phase noise and spuious index can be reached.In correlation technique, the frequency synthesizer of phase-locked loop synthetic method is adopted to generally include phase discriminator, loop filter, voltage controlled oscillator and frequency divider.But there is following problem in the PLL frequency synthesize method widely applied at present: by the restriction of voltage controlled oscillator output frequency, causes frequency range narrow; Along with the increase of voltage controlled oscillator reference frequency output, voltage controlled oscillator tuning change of sensitivity increases, and causes loop filter and voltage controlled oscillator to be not suitable with, finally causes phase of output signal noise sharply to worsen.Such as, when voltage controlled oscillator output area is 4GHz ~ 7GHz, be 5.1GHz ~ 5.3GHz in output signal frequency scope, phase noise can reach-90dBc/Hz@10kHz; And high-end at output frequency, within the scope of such as 6.9GHz ~ 7.0GHz, phase noise can only reach-85dBc/Hz@10kHz.
Along with the development of the communication technology, require that the reference frequency output of frequency synthesizer is more and more wider, and also more and more higher to the requirement of phase noise, the PLL frequency synthesize mode in correlation technique can not meet the requirement to reference frequency output and phase noise.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of frequency synthesizer, reduces phase noise.
For solving the problems of the technologies described above, the utility model proposes a kind of frequency synthesizer, comprise the first variable division phase discriminator, first ring path filter, second variable division phase discriminator, second loop filter, loop selector switch, first voltage controlled oscillator, first splitter, amplifilter, frequency mixer, constant-temperature crystal oscillator, 3rd splitter, 3rd variable division phase discriminator, Three links theory filter, second voltage controlled oscillator and the second splitter, wherein, the output of constant-temperature crystal oscillator described in the input termination of described 3rd splitter, first of described 3rd splitter exports the first input end of the first variable division phase discriminator described in termination, second output of the first splitter described in second input termination of described first variable division phase discriminator, the input of first ring path filter described in the output termination of described first variable division phase discriminator, the first input end of loop selector switch described in the output termination of described first ring path filter, the first input end of described second variable division phase discriminator connects the second output of described 3rd splitter, the output of amplifilter described in second input termination of described second variable division phase discriminator, the input of the second loop filter described in the output termination of described second variable division phase discriminator, the second input of loop selector switch described in the output termination of described second loop filter, the input of the first voltage controlled oscillator described in the output termination of described loop selector switch, the input of the first splitter described in the output termination of described first voltage controlled oscillator, the first output of described first splitter is the output of described frequency synthesizer, the first input end of described 3rd variable division phase discriminator connects the 3rd output of described 3rd splitter, second output of the second splitter described in second input termination of described 3rd variable division phase discriminator, the input of Three links theory filter described in the output termination of described 3rd variable division phase discriminator, the input of the second voltage controlled oscillator described in the output termination of described Three links theory filter, the input of the second splitter described in the output termination of described second voltage controlled oscillator, the first input end of described frequency mixer connects the 3rd output of described first splitter, the first output of the second splitter described in the second input termination of described frequency mixer, the input of amplifilter described in the output termination of described frequency mixer.
Further, said frequencies synthesizer also can have following characteristics, described first variable division phase discriminator comprises the first parametric frequency divider, first feedback divider and the first phase discriminator, the first input end of the first phase discriminator described in the output termination of described first parametric frequency divider, second input of the first phase discriminator described in the output termination of described first feedback divider, the input of described first parametric frequency divider is the first input end of the first variable division phase discriminator, the input of described first feedback divider is the second input of described first variable division phase discriminator, the output of described first phase discriminator is the output of described first variable division phase discriminator,
Described second variable division phase discriminator comprises the second parametric frequency divider, second feedback divider and the second phase discriminator, the first input end of the second phase discriminator described in the output termination of described second parametric frequency divider, second input of the second phase discriminator described in the output termination of described second feedback divider, the input of described second parametric frequency divider is the first input end of described second variable division phase discriminator, the input of described second feedback divider is the second input of described second variable division phase discriminator, the output of described second phase discriminator is the output of described second variable division phase discriminator,
Described 3rd variable division phase discriminator comprises the 3rd parametric frequency divider, 3rd feedback divider and the 3rd phase discriminator, the first input end of the 3rd phase discriminator described in the output termination of described 3rd parametric frequency divider, second input of the 3rd phase discriminator described in the output termination of described 3rd feedback divider, the input of described 3rd parametric frequency divider is the first input end of described 3rd variable division phase discriminator, the input of described 3rd feedback divider is the second input of described 3rd variable division phase discriminator, the output of described 3rd phase discriminator is the output of described 3rd variable division phase discriminator.
Further, said frequencies synthesizer also can have following characteristics, and described first voltage controlled oscillator, the second voltage controlled oscillator are broadband Integrated VCO.
Further, said frequencies synthesizer also can have following characteristics, and described first ring path filter, the second loop filter, Three links theory filter are three rank active loop filters.
Further, said frequencies synthesizer also can have following characteristics, and described loop selector switch is high voltage low noise electronic switch.
Frequency synthesizer of the present utility model, by adopting double loop mixing Phase Lock Technique, can reduce the phase noise outputed signal when broadband exports.Meanwhile, frequency synthesizer of the present utility model, by the preset VCO technology of phase-locked loop, ensure that phase-locked loop correctly locks, and decreases the loop-locking time.
Accompanying drawing explanation
Fig. 1 is a kind of structure chart of the utility model embodiment frequency synthesizer.
Fig. 2 is a kind of structure chart of variable division phase discriminator.
Fig. 3 is a kind of concrete structure figure of the utility model embodiment frequency synthesizer.
Embodiment
Be described principle of the present utility model and feature below in conjunction with accompanying drawing, example, only for explaining the utility model, is not intended to limit scope of the present utility model.
Fig. 1 is a kind of structure chart of the utility model embodiment frequency synthesizer.As shown in Figure 1, in the present embodiment, frequency synthesizer comprises the first variable division phase discriminator 1, first ring path filter 2, second variable division phase discriminator 3, second loop filter 4, loop selector switch 5, first voltage controlled oscillator 6, first splitter 7, amplifilter 8, frequency mixer 9, constant-temperature crystal oscillator 11, the 3rd splitter 10, the 3rd variable division phase discriminator 13, Three links theory filter 12, second voltage controlled oscillator 14 and the second splitter 15.Wherein, the output of the input termination constant-temperature crystal oscillator 11 of the 3rd splitter 10, first of 3rd splitter 10 exports the first input end of termination first variable division phase discriminator 1, second output of the second input termination first splitter 7 of the first variable division phase discriminator 1, the input of the output termination first ring path filter 2 of the first variable division phase discriminator 1, the first input end of the output T-Ring road selector switch 5 of first ring path filter 2.The first input end of the second variable division phase discriminator 3 connects the second output of the 3rd splitter 10, the output of the second input termination amplifilter 8 of the second variable division phase discriminator 3, the input of output termination second loop filter 4 of the second variable division phase discriminator 3, the second input of the output T-Ring road selector switch 5 of the second loop filter 4.The input of output termination first voltage controlled oscillator 6 of loop selector switch 5, the input of output termination first splitter 7 of the first voltage controlled oscillator 6, the first output of the first splitter 7 is the output of frequency synthesizer.The first input end of the 3rd variable division phase discriminator 13 connects the 3rd output of the 3rd splitter 10, second output of the second input termination second splitter 15 of the 3rd variable division phase discriminator 13, the input of the output termination Three links theory filter 12 of the 3rd variable division phase discriminator 13, the input of output termination second voltage controlled oscillator 14 of Three links theory filter 12, the input of output termination second splitter 14 of the second voltage controlled oscillator 14.The first input end of frequency mixer 9 connects the 3rd output of the first splitter 7, the first output of the second input termination second splitter 15 of frequency mixer 9, the input of the output termination amplifilter 8 of frequency mixer 9.
Wherein, the first voltage controlled oscillator 6, second voltage controlled oscillator 14 can be broadband Integrated VCO.
Wherein, first ring path filter 2, second loop filter 4, Three links theory filter 12 can be three rank active loop filters.
Wherein, loop selector switch 5 can be high voltage low noise electronic switch.
Wherein, the first variable division phase discriminator 1 can adopt model to be the variable division phase discriminator of ADF4108BCPZ.Second variable division phase discriminator 3 can adopt model to be the variable division phase discriminator of HMC698LP5E.3rd variable division phase discriminator 13 can adopt model to be the variable division phase discriminator of HMC698LP5E.Loop selector switch 5 can adopt model to be the electronic switch of ADG419.
In the utility model embodiment, the first variable division phase discriminator 1, second variable division phase discriminator 3, the 3rd variable division phase discriminator 13 can adopt variable division phase discriminator as shown in Figure 2.
Fig. 2 is a kind of structure chart of variable division phase discriminator.As shown in Figure 2, in the present embodiment, variable division phase discriminator comprises the first frequency divider 210, second frequency divider 220 and phase discriminator 230.Wherein, the first frequency divider 210, second frequency divider 220 is connected with phase discriminator 230 respectively.
Fig. 3 is a kind of concrete structure figure of the utility model embodiment frequency synthesizer.As shown in Figure 3, in the present embodiment, the general structure of frequency synthesizer is identical with Fig. 1, and difference is, the first variable division phase discriminator 1, second variable division phase discriminator 3, the 3rd variable division phase discriminator 13 have employed the structure shown in Fig. 2.The structure identical with Fig. 1 repeats no more here, here only illustratively with the difference part of Fig. 1.In Fig. 3, the first variable division phase discriminator 1 comprises the first parametric frequency divider 17, first feedback divider 16 and the first phase discriminator 18.The first input end of output termination first phase discriminator 18 of the first parametric frequency divider 17, second input of output termination first phase discriminator 18 of the first feedback divider 16, the input of the first parametric frequency divider 17 is the first input end of the first variable division phase discriminator 1, the first input end of this first variable division phase discriminator 1 connects the first output of the 3rd splitter 10, the input of the first feedback divider 16 is the second input of the first variable division phase discriminator 1, second output of the second input termination first splitter 7 of this first variable division phase discriminator 1, the output of the first phase discriminator 18 is the output of the first variable division phase discriminator 1, the input of the output termination first ring path filter 2 of this first variable division phase discriminator 1.From the reference signal of constant-temperature crystal oscillator 11 after the first parametric frequency divider 17 frequency division, with the signal of feedback signal after the first feedback divider 16 frequency division exported from the first voltage controlled oscillator 6, phase demodulation is carried out in the first phase discriminator 18, generation error voltage exports, as the input signal of first ring path filter 2.
As shown in Figure 3, the second variable division phase discriminator 3 comprises the second parametric frequency divider 19, second feedback divider 21 and the second phase discriminator 20.The first input end of output termination second phase discriminator 20 of the second parametric frequency divider 19, second input of output termination second phase discriminator 20 of the second feedback divider 21, the input of the second parametric frequency divider 19 is the first input end of the second variable division phase discriminator 3, the first input end of this second variable division phase discriminator 3 connects the second output of the 3rd splitter 10, the input of the second feedback divider is the second input of described second variable division phase discriminator, the output of the second input termination amplifilter 8 of this second variable division phase discriminator 3, the output of the second phase discriminator 20 is the output of the second variable division phase discriminator 3, the input of output termination second loop filter 4 of this second variable division phase discriminator 3.From the reference signal of constant-temperature crystal oscillator 11 after the second parametric frequency divider 19 frequency division, with the signal of feedback signal after the second feedback divider 21 frequency division exported from the first voltage controlled oscillator 6, phase demodulation is carried out in the second phase discriminator 20, generation error voltage exports, as the input signal of the second loop filter 4.
As shown in Figure 3, 3rd variable division phase discriminator 13 comprises the 3rd parametric frequency divider 22, 3rd feedback divider 24 and the 3rd phase discriminator 23, the first input end of output termination the 3rd phase discriminator 23 of the 3rd parametric frequency divider 22, second input of output termination the 3rd phase discriminator 23 of the 3rd feedback divider 24, the input of the 3rd parametric frequency divider 22 is the first input end of the 3rd variable division phase discriminator 13, the first input end of the 3rd variable division phase discriminator 13 connects the 3rd output of the 3rd splitter 10, the input of the 3rd feedback divider 24 is the second input of the 3rd variable division phase discriminator 13, second output of the second input termination second splitter 15 of the 3rd variable division phase discriminator 13, the output of the 3rd phase discriminator 23 is the output of the 3rd variable division phase discriminator 13, the input of the output termination Three links theory filter 12 of the 3rd variable division phase discriminator 13.From the reference signal of constant-temperature crystal oscillator 11 after the 3rd parametric frequency divider 22 frequency division, with the signal of feedback signal after the 3rd feedback divider 24 frequency division exported from the first voltage controlled oscillator 6, phase demodulation is carried out in the 3rd phase discriminator 23, generation error voltage exports, as the input signal of Three links theory filter 12.
Below the operation principle of frequency synthesizer shown in Fig. 3 is described.The operation principle of frequency synthesizer shown in Fig. 3 is as follows:
The signal that constant-temperature crystal oscillator 11 exports through the 3rd splitter 10 along separate routes after, as with reference to signal.The signal that first voltage controlled oscillator 6 exports, be divided into three tunnels through the first splitter 7, wherein a road is as the output signal of frequency synthesizer, and two-way is respectively as feedback signal in addition.
When loop starts to lock, the road signal that first splitter 7 exports, enter the first variable division phase discriminator 1, after the first feedback divider 16 frequency division, with the signal of constant-temperature crystal oscillator 11 after the first parametric frequency divider 17 frequency division in the first phase discriminator 18 after phase demodulation, by first ring path filter 2 filtering.Now, the output voltage of loop selector switch 5 gating first ring path filter 2, as the tuning voltage of the first voltage controlled oscillator 6, realizes the first locking of the first voltage controlled oscillator 6.The object of first locking makes the first voltage controlled oscillator 6 export required correct frequency.
The other road signal that first voltage controlled oscillator 6 exports through the first splitter 7, through the signal mixing that frequency mixer 9 and the second voltage controlled oscillator 14 export, the intermediate-freuqncy signal obtained, after amplifilter 8, enters the second variable division phase discriminator 3.This signal is after the second feedback divider 21, and with the signal of constant-temperature crystal oscillator 11 after the second parametric frequency divider 10 frequency division, phase demodulation in the second phase discriminator 20, the voltage that phase demodulation obtains exports through the second loop filter 4.Under the first locking of the first voltage controlled oscillator 6, the voltage of now loop selector switch 5 gating second loop filter 4 output, as the control voltage of the first voltage controlled oscillator 6, keeps the lock-out state of the first voltage controlled oscillator 6.First voltage controlled oscillator 6, can output band is wide, phase noise is little signal after secondary locking.
Frequency synthesizer working frequency range of the present utility model can be C frequency range (such as 4000MHz ~ 8000MHz).In experiment, contrast test is done to the frequency synthesizer of the employing monocycle scheme in correlation technique and frequency synthesizer of the present utility model.Experiment adopts the N9030A frequency spectrograph of Agilent, uses 100MHz constant-temperature crystal oscillator (≤-165dBc/Hz 10kHz) as reference source.In experiment, the output signal frequency of frequency synthesizer of the present utility model is 4GHz ~ 8GHz.The test data obtained by this experiment is as shown in table 1.
The test data of table 1 monocycle frequency synthesizer and frequency synthesizer of the present utility model
By the Data Comparison of table 1, can find out, frequency synthesizer of the present utility model is at offset carrier 10kHz and 100kHz place phase noise lower than monocycle frequency synthesizer 20dB, and visible, the phase noise of frequency synthesizer of the present utility model is obviously better than the monocycle frequency synthesizer in correlation technique.
Frequency synthesizer of the present utility model, by adopting double loop mixing Phase Lock Technique, can reduce the phase noise outputed signal when broadband exports.Meanwhile, frequency synthesizer of the present utility model, by the preset VCO technology of phase-locked loop, ensure that phase-locked loop correctly locks, and decreases the loop-locking time.
The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.
Claims (5)
1. a frequency synthesizer, it is characterized in that, comprise the first variable division phase discriminator, first ring path filter, second variable division phase discriminator, second loop filter, loop selector switch, first voltage controlled oscillator, first splitter, amplifilter, frequency mixer, constant-temperature crystal oscillator, 3rd splitter, 3rd variable division phase discriminator, Three links theory filter, second voltage controlled oscillator and the second splitter, wherein, the output of constant-temperature crystal oscillator described in the input termination of described 3rd splitter, first of described 3rd splitter exports the first input end of the first variable division phase discriminator described in termination, second output of the first splitter described in second input termination of described first variable division phase discriminator, the input of first ring path filter described in the output termination of described first variable division phase discriminator, the first input end of loop selector switch described in the output termination of described first ring path filter, the first input end of described second variable division phase discriminator connects the second output of described 3rd splitter, the output of amplifilter described in second input termination of described second variable division phase discriminator, the input of the second loop filter described in the output termination of described second variable division phase discriminator, the second input of loop selector switch described in the output termination of described second loop filter, the input of the first voltage controlled oscillator described in the output termination of described loop selector switch, the input of the first splitter described in the output termination of described first voltage controlled oscillator, the first output of described first splitter is the output of described frequency synthesizer, the first input end of described 3rd variable division phase discriminator connects the 3rd output of described 3rd splitter, second output of the second splitter described in second input termination of described 3rd variable division phase discriminator, the input of Three links theory filter described in the output termination of described 3rd variable division phase discriminator, the input of the second voltage controlled oscillator described in the output termination of described Three links theory filter, the input of the second splitter described in the output termination of described second voltage controlled oscillator, the first input end of described frequency mixer connects the 3rd output of described first splitter, the first output of the second splitter described in the second input termination of described frequency mixer, the input of amplifilter described in the output termination of described frequency mixer.
2. frequency synthesizer according to claim 1, is characterized in that:
Described first variable division phase discriminator comprises the first parametric frequency divider, first feedback divider and the first phase discriminator, the first input end of the first phase discriminator described in the output termination of described first parametric frequency divider, second input of the first phase discriminator described in the output termination of described first feedback divider, the input of described first parametric frequency divider is the first input end of the first variable division phase discriminator, the input of described first feedback divider is the second input of described first variable division phase discriminator, the output of described first phase discriminator is the output of described first variable division phase discriminator,
Described second variable division phase discriminator comprises the second parametric frequency divider, second feedback divider and the second phase discriminator, the first input end of the second phase discriminator described in the output termination of described second parametric frequency divider, second input of the second phase discriminator described in the output termination of described second feedback divider, the input of described second parametric frequency divider is the first input end of described second variable division phase discriminator, the input of described second feedback divider is the second input of described second variable division phase discriminator, the output of described second phase discriminator is the output of described second variable division phase discriminator,
Described 3rd variable division phase discriminator comprises the 3rd parametric frequency divider, 3rd feedback divider and the 3rd phase discriminator, the first input end of the 3rd phase discriminator described in the output termination of described 3rd parametric frequency divider, second input of the 3rd phase discriminator described in the output termination of described 3rd feedback divider, the input of described 3rd parametric frequency divider is the first input end of described 3rd variable division phase discriminator, the input of described 3rd feedback divider is the second input of described 3rd variable division phase discriminator, the output of described 3rd phase discriminator is the output of described 3rd variable division phase discriminator.
3. frequency synthesizer according to claim 1, is characterized in that, described first voltage controlled oscillator, the second voltage controlled oscillator are broadband Integrated VCO.
4. frequency synthesizer according to claim 1, is characterized in that, described first ring path filter, the second loop filter, Three links theory filter are three rank active loop filters.
5. frequency synthesizer according to claim 1, is characterized in that, described loop selector switch is high voltage low noise electronic switch.
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| CN201420538822.0U CN204103898U (en) | 2014-09-16 | 2014-09-16 | A kind of frequency synthesizer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106018907A (en) * | 2015-03-31 | 2016-10-12 | 特克特朗尼克公司 | Band overlay separator |
| CN109491714A (en) * | 2018-11-05 | 2019-03-19 | 浙江理工大学 | A kind of data communication equipment and method |
| CN110719099A (en) * | 2019-11-19 | 2020-01-21 | 中国电子科技集团公司第二十九研究所 | Synthesizer-based in-loop mixing type phase-locked loop |
-
2014
- 2014-09-16 CN CN201420538822.0U patent/CN204103898U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106018907A (en) * | 2015-03-31 | 2016-10-12 | 特克特朗尼克公司 | Band overlay separator |
| CN106018907B (en) * | 2015-03-31 | 2020-12-08 | 特克特朗尼克公司 | Frequency band overlapping separator |
| CN109491714A (en) * | 2018-11-05 | 2019-03-19 | 浙江理工大学 | A kind of data communication equipment and method |
| CN109491714B (en) * | 2018-11-05 | 2021-08-10 | 杭州华移技术有限公司 | Data communication device and method |
| CN110719099A (en) * | 2019-11-19 | 2020-01-21 | 中国电子科技集团公司第二十九研究所 | Synthesizer-based in-loop mixing type phase-locked loop |
| CN110719099B (en) * | 2019-11-19 | 2023-05-05 | 中国电子科技集团公司第二十九研究所 | In-loop mixing phase-locked loop based on synthesizer |
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