CN104202047A - Monolithic integration frequency synthesizer based on VHF (very high frequency) band - Google Patents
Monolithic integration frequency synthesizer based on VHF (very high frequency) band Download PDFInfo
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- CN104202047A CN104202047A CN201410416556.9A CN201410416556A CN104202047A CN 104202047 A CN104202047 A CN 104202047A CN 201410416556 A CN201410416556 A CN 201410416556A CN 104202047 A CN104202047 A CN 104202047A
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Abstract
The invention discloses a monolithic integration frequency synthesizer based on a VHF (very high frequency) band. The monolithic integration frequency synthesizer based on the VHF band comprises five portions of a module composed of an input interface and a power supply filter circuit 1, an FPGA (field programmable gate array) time sequence control circuit 2, a PLL (phase locking loop) circuit 3, a module composed of a crystal oscillator and an amplification filter circuit 4 and a module composed of a buffer amplification circuit and an output interface 5, wherein the five portions are combined into a whole body. A monolithic integration PLL and VCO circuit is used to form a frequency synthesizer module. A chip is designed to work in a fractional frequency division mode, and a VCO automatic calibration frequency mode is adopted, and therefore frequency can be obtained through quick switching, and good power flatness is achieved in approximately three octaves of a work frequency band. Compared with direct frequency synthesis of a DDS (direct digital synthesizer), spurious phase noise of frequency spectra obtained by using a PLL chip circuit is low. Compared with a VCO circuit composed of discrete elements, the PLL chip circuit is good in temperature characteristic and low in lock losing cycle skipping probability. A monolithic integration PLL and VCO chip is used, and therefore debugging difficulty of the monolithic integration frequency synthesizer based on the VHF band is substantially reduced, the size of the monolithic integration frequency synthesizer based on the VHF band is small, and reliability of the monolithic integration frequency synthesizer based on the VHF band is substantially improved.
Description
Technical field
The present invention relates to a kind of frequency synthesizer, particularly a kind of monolithic integrate frequency synthesizer based on VHF frequency range.
Background technology
Along with wireless communication technology develop rapidly in recent years, Wireless Telecom Equipment is just more superior towards performance, function is more diversified, volume is miniaturization more, the direction of with low costization is constantly progressive, simultaneously also more and more higher to the requirement of its reliability, and frequency synthesizer in equipment is good and bad, the status of frequency synthesizer in Wireless Telecom Equipment directly affect Key Performance Indicator, reliability and the Electromagnetic Compatibility of whole communication equipment, so can not be ignored.
The frequency synthesizer circuit complexity based on VHF frequency range is in the past various, bulky, cost is high, spuious make an uproar mutually large, debugging difficulty is high, reliability is low, very easily causes communication station fault; How to realize miniaturization, low cost, high performance requirements, realize reliable efficient communication, become insider's important topic urgently to be resolved hurrily.
Summary of the invention
Object of the present invention is exactly in order to overcome the deficiency of above-mentioned prior art, provides a kind of reasonable in design, the monolithic integrate frequency synthesizer based on VHF frequency range simple in structure.
In order to achieve the above object, the technical solution used in the present invention is:
A kind of monolithic integrate frequency synthesizer based on VHF frequency range, include: input interface and electric source filter circuit 1, FPGA sequential control circuit 2, PLL phase-locked loop circuit 3, crystal oscillator and filtering and amplifying circuit 4, buffer amplifier circuit and output interface 5, totally 5 parts combine and form an integral body, wherein:
Described PLL phase-locked loop circuit 3, comprises again phase-locked integrated chip circuit 31 and loop filter circuit 32; For phase discriminator, receive the PLL control code that FPGA sequential control circuit is brought, carry out frequency discrimination/phase demodulation, reach quick lock in, frequency switching, lock-in detection and power stage, synthetic required frequency;
Described FPGA sequential control circuit 2, comprises again fpga chip circuit 21 and eeprom chip circuit 22; For the treatment of the frequency word information of outside excuse, generate the control code of phase-locked integrated chip, control the various operating states of phase-locked integrated chip, to outside excuse, provide lock-in detection state;
Described crystal oscillator and filtering and amplifying circuit 4, comprise again temperature compensating crystal oscillator output amplifier 41 and five rank Low-pass Elliptic Filters 42; For obtaining the clock signal of firm power, to fpga chip, provide master clock, simultaneously for phase demodulation reference clock being provided to phase-locked integrated chip;
Described input interface and electric source filter circuit 1, comprise again input interface 11 and electric source filter circuit 12; For the input and output of frequency word signal, power filter process and to provide+1.5V of unit ,+3.3V and+5V supply voltage;
Described buffer amplifier circuit and output interface 5, comprise again buffer amplifier circuit 51 and output interface 52.For local oscillation signal, through Hyblid Buffer Amplifier, output matching is delivered to radio frequency output interface output.
Fundamental design idea of the present invention comprises four aspects: chip controls design, the design of PLL phase-locked loop circuit, temperature compensating crystal oscillator and filtering and amplifying circuit design, buffer amplifier circuit design.
1, chip controls design: owing to adopting a broadband phase-looked loop chip HMC832LP6G, it is inner integrated phase discriminator and VCO.For these data, write to control and require CMOS level, employing be the form of spi bus, external control signal is write into the register of chip internal by SCK, SDI and SEN pin with the form of spi bus.Employing fpga chip A3P125 can be according to controlling this chip operation of sequencing control.Because frequency needs to switch fast, the required FREQUENCY CONTROL code of HMC832LP6G is kept in EEPROM in advance, after being read by FPGA, send to chip controls.Eeprom chip adopts AT24C-256B;
2, PLL phase-locked loop circuit design: by changing chip internal register data, realize frequency and switch fast, reach frequency hopping object.When there is losing lock in frequency, by chip, return to low level signal, without carrying peripheral circuit, detect.Setting filter is passive quadravalence low pass filter, and circuit two ends are connected on respectively CP pin and the VTUNE pin of chip.Design this chip operation in fractional frequency division pattern, and under this pattern, adopt VCO automatic calibration frequency mode, make can switch rapidly acquisition at specified conditions lower frequencies such as frequency hoppings;
3, crystal oscillator and filtering and amplifying circuit design: temperature compensating crystal oscillator adopts output signal to enter the reverse amplifying signal of single diode negative feedback, and filter the humorous clutter that involves through five rank Low-pass Elliptic Filters, obtain stable reference signal and enter fpga chip A3P060 as master clock signal, enter phase-locked integrated chip HMC830LP6GE as with reference to clock;
4, buffer amplifier circuit design: exporting typical power output due to chip is 7dBm, and can take 3dB as step-by-step adjustment.Output selects SGA2486 that local oscillator is amplified after mating by connecting resistance attenuation network, finally by coupling, exports.
The course of work of the present invention is: temperature compensating crystal oscillator amplifies and fpga chip is exported in filtering and integrated chip HMC830LP6G is used as master clock and reference clock, outside frequency signal is sent into FPGA by input interface and is analyzed, FPGA reads FREQUENCY CONTROL code corresponding in EEPROM according to frequency word information, sending 4 timing control signals controls HMC830LP6GE and carries out the working methods such as phase-locked, frequency switching, power stage, obtain local oscillation signal through Hyblid Buffer Amplifier, output matching is delivered to radio frequency output interface output.
In a word, the present invention adopts the integrated phase-locked chip of monolithic to form frequency synthesizer, in nearly 3 octaves of working band, has realized good power flatness; Adopt PLL+VCO integrated chip circuit, than the direct frequency synthesis of DDS chip, the frequency spectrum that obtains is spuious make an uproar mutually less; Than discrete component, form VCO circuit, its temperature characterisitic is better, and losing lock cycle-skipping probability is lower; Adopt monolithic integrated PLL+VCO chip, its debugging difficulty significantly reduces, volume is less, and unfailing performance is significantly improved.
Accompanying drawing explanation
Fig. 1 electrical schematic diagram of the present invention;
Fig. 2 overall structure schematic diagram of the present invention.
Symbol description in figure:
The 1st, input interface and electric source filter circuit;
The 2nd, FPGA sequential control circuit;
The 3rd, PLL phase-locked loop circuit;
The 4th, crystal oscillator and filtering and amplifying circuit;
The 5th, buffer amplifier circuit and output interface;
The 11st, input interface;
The 12nd, electric source filter circuit;
The 21st, fpga chip circuit;
The 22nd, eeprom chip circuit;
The 31st, phase-locked integrated chip circuit;
The 32nd, loop filter circuit;
The 41st, crystal oscillator and amplifying circuit;
42 is five rank low-pass filter circuits;
The 51st, buffer amplifier circuit;
The 52nd, output interface.
Embodiment
Referring to shown in Fig. 1 and Fig. 2, is the specific embodiment of the invention.
Visible in conjunction with Fig. 1 and Fig. 2: to have the present invention includes input interface and electric source filter circuit 1, FPGA control circuit 2, phase-locked integrated chip circuit and loop filter circuit 3, crystal oscillator and filtering and amplifying circuit 4, buffer amplifier circuit and output interface 5, totally five parts combine and form an integral body, wherein:
A. described PLL phase-locked loop circuit 3, comprises again phase-locked integrated chip circuit 31 and loop filter circuit 32; And in phase-locked integrated chip circuit 31, the 15th pin of phase-locked integrated chip U3 and build-out resistor R11 one end and matching capacitance C7 output intersect at A point; The 4th pin of phase-locked integrated chip U3 and the one end of capacitor C 8, resistance R 4 and R5 in loop filter circuit 32 intersect at B point; The 23rd pin of phase-locked integrated chip U3 and the input of the resistance R 6 in loop filter circuit 32 and capacitor C 11 intersect at D point, the 29th pin of phase-locked integrated chip U3 is connected with the input of matching capacitance C12, phase-locked integrated chip U3 the 30th to 33 pin are connected respectively at the 30th pin, the 29th pin, the 28th pin and the 32nd pin of U1 in FPGA sequential control circuit 2 successively, and in the output of matching capacitance C12 and buffer amplifier circuit and output interface 5, the input of resistance R 7 and R8 intersects at Q point;
B. described FPGA sequential control circuit 2, comprises again fpga chip circuit 21 and eeprom chip circuit 22, and the 34th pin that comprises U1 in fpga chip circuit 21, the 35th pin successively respectively with eeprom chip circuit 22 in the 5th pin of U2, the 6th pin is connected, the 34th pin of U1, 35 pin successively respectively with the 5th pin of U2, the 6th pin is connected, the 6th pin of U1, the 7th pin, the 8th pin, the 99th pin successively respectively with input interface and electric source filter circuit 1 in the 12nd pin of input interface J1, the 5th pin, the 3rd pin is connected with the 8th pin, the 11st pin of U1 is connected with the input of capacitor C 15, inductance L 3 outputs and capacitor C 6 outputs in the output of capacitor C 15 and crystal oscillator and filtering and amplifying circuit 4 intersect at H point.
Described crystal oscillator and filtering and amplifying circuit 4, comprise again temperature compensating crystal oscillator output amplifier 41, five rank Low-pass Elliptic Filters 42; And the 2nd pin of temperature compensating crystal oscillator U4 is powered by be connected to+VCC of filter inductance L4 in temperature compensating crystal oscillator output amplifier 41, the 1st pin of temperature compensating crystal oscillator U4 and the 3rd pin ground connection, temperature compensating crystal oscillator U4 the 4th pin is connected with matching capacitance C1 input; Matching capacitance C1 output simultaneously intersects at E point with the 1st pin of biasing resistor R1 and R2 one end, triode V1, and feedback resistance R3 and capacitor C 2 are connected in the 2nd pin of V1 simultaneously, and filter inductance L1 and matching capacitance C3 are connected in the 3rd pin of V1 simultaneously; Capacitor C 4 and inductance L 2 in the output of matching capacitance C3 and five rank Low-pass Elliptic Filters 42 intersect at F point.
Described input interface and electric source filter circuit 1, include again input interface 11, electric source filter circuit 12; And the 6th pin of input interface J1, the 15th pin and the 13rd pin are connected respectively at the 1st pin in electric source filter circuit 12, the 2nd pin, the 3rd pin successively.
Described buffer amplifier circuit and output interface 5, comprise again buffer amplifier circuit 51 and output interface 52; And in buffer amplifier circuit 51, the 1st pin of U5 is connected with matching capacitance C13 output, the 3rd pin of U5 is connected with the input of matching capacitance C14, the 4th pin of U5 is connected with the output of biasing resistor R10, biasing resistor R10 is again by be connected to+VCC of filter inductance L4, the input of matching capacitance C13 and resistance R 8, R9 intersect at J point, and the output of matching capacitance C14 is connected with the J2 in output interface 52.
What deserves to be explained is, in the present invention, main devices model is followed successively by: in FPGA sequential control circuit, U1 is used A3P060 chip, and U2 is used AT24C-256B chip; In PLL phase-locked loop circuit, U3 is used HMC830LP6GE chip; In crystal oscillator and filtering and amplifying circuit, U4 is used VC-TCXO-6.4MHz temperature compensating crystal oscillator; In buffer amplifier circuit and output interface, U5 is used SGA4586 chip; All the other are technical grade device and accurately machined self-making structure part.
Above embodiment is only better enforcement of the present invention, in order to technical characterictic of the present invention and exploitativeness to be described; Above description simultaneously, for knowing those skilled in the art, should understand and be implemented, therefore, other is not departing from equivalent change or the modification completing under disclosed prerequisite, all should be included within claim scope of the present invention.
Claims (4)
1. the monolithic integrate frequency synthesizer based on VHF frequency range, include: input interface and electric source filter circuit (1), FPGA sequential control circuit (2), PLL phase-locked loop circuit (3), crystal oscillator and filtering and amplifying circuit (4), buffer amplifier circuit and output interface (5), totally 5 parts combine and form an integral body, it is characterized in that:
A. described PLL phase-locked loop circuit (3), comprises again phase-locked integrated chip circuit (31) and loop filter circuit (32); And in phase-locked integrated chip circuit (31), the 15th pin of phase-locked integrated chip U3 and build-out resistor R11 one end and matching capacitance C7 output intersect at A point; The 4th pin of phase-locked integrated chip U3 and the one end of capacitor C 8, resistance R 4 and R5 in loop filter circuit (32) intersect at B point; The 23rd pin of phase-locked integrated chip U3 and the input of the resistance R 6 in loop filter circuit (32) and capacitor C 11 intersect at D point, the 29th pin of phase-locked integrated chip U3 is connected with the input of matching capacitance C12, phase-locked integrated chip U3 the 30th to 33 pin are connected respectively at the 30th pin, the 29th pin, the 28th pin and the 32nd pin of U1 in FPGA sequential control circuit (2) successively, and in the output of matching capacitance C12 and buffer amplifier circuit and output interface (5), the input of resistance R 7 and R8 intersects at Q point; For phase discriminator, receive the PLL control code that FPGA sequential control circuit is brought, carry out frequency discrimination/phase demodulation, reach quick lock in, frequency switching, lock-in detection and power stage, synthetic required frequency;
B. described FPGA sequential control circuit (2), comprises again fpga chip circuit (21) and eeprom chip circuit (22), and the 34th pin that comprises U1 in fpga chip circuit (21), the 35th pin successively respectively with eeprom chip circuit (22) in the 5th pin of U2, the 6th pin is connected, the 34th pin of U1, 35 pin successively respectively with the 5th pin of U2, the 6th pin is connected, the 6th pin of U1, the 7th pin, the 8th pin, the 99th pin successively respectively with input interface and electric source filter circuit (1) in the 12nd pin of input interface J1, the 5th pin, the 3rd pin is connected with the 8th pin, the 11st pin of U1 is connected with the input of capacitor C 15, inductance L 3 outputs and capacitor C 6 outputs in the output of capacitor C 15 and crystal oscillator and filtering and amplifying circuit (4) intersect at H point, for the treatment of the frequency word information of outside excuse, generate the control code of phase-locked integrated chip, control the various operating states of phase-locked integrated chip, to outside excuse, provide lock-in detection state.
2. the monolithic integrate frequency synthesizer based on VHF frequency range as claimed in claim 1, is characterized in that:
Described crystal oscillator and filtering and amplifying circuit (4), comprise again temperature compensating crystal oscillator output amplifier (41), five rank Low-pass Elliptic Filters (42); And the 2nd pin of temperature compensating crystal oscillator U4 is powered by be connected to+VCC of filter inductance L4 in temperature compensating crystal oscillator output amplifier (41), the 1st pin of temperature compensating crystal oscillator U4 and the 3rd pin ground connection, temperature compensating crystal oscillator U4 the 4th pin is connected with matching capacitance C1 input; Matching capacitance C1 output simultaneously intersects at E point with the 1st pin of biasing resistor R1 and R2 one end, triode V1, and feedback resistance R3 and capacitor C 2 are connected in the 2nd pin of V1 simultaneously, and filter inductance L1 and matching capacitance C3 are connected in the 3rd pin of V1 simultaneously; Capacitor C 4 and inductance L 2 in the output of matching capacitance C3 and five rank Low-pass Elliptic Filters (42) intersect at F point; For obtaining the clock signal of firm power, to fpga chip, provide master clock, simultaneously for phase demodulation reference clock being provided to phase-locked integrated chip.
3. the monolithic integrate frequency synthesizer based on VHF frequency range as claimed in claim 1, is characterized in that:
Described input interface and electric source filter circuit (1), include again input interface (11), electric source filter circuit (12); And the 6th pin of input interface J1, the 15th pin and the 13rd pin are connected respectively at the 1st pin in electric source filter circuit (12), the 2nd pin, the 3rd pin successively; For the input and output of frequency word signal, power filter process and to provide+1.5V of unit ,+3.3V and+5V supply voltage.
4. the monolithic integrate frequency synthesizer based on VHF frequency range as claimed in claim 1, is characterized in that:
Described buffer amplifier circuit and output interface (5), comprise again buffer amplifier circuit (51) and output interface (52); And in buffer amplifier circuit (51), the 1st pin of U5 is connected with matching capacitance C13 output, the 3rd pin of U5 is connected with the input of matching capacitance C14, the 4th pin of U5 is connected with the output of biasing resistor R10, biasing resistor R10 is again by be connected to+VCC of filter inductance L4, the input of matching capacitance C13 and resistance R 8, R9 intersect at J point, and the output of matching capacitance C14 is connected with the J2 in output interface (52); For local oscillation signal, through Hyblid Buffer Amplifier, output matching is delivered to radio frequency output interface output.
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| CN201410416556.9A CN104202047A (en) | 2014-08-22 | 2014-08-22 | Monolithic integration frequency synthesizer based on VHF (very high frequency) band |
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| CN201410416556.9A CN104202047A (en) | 2014-08-22 | 2014-08-22 | Monolithic integration frequency synthesizer based on VHF (very high frequency) band |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113612475A (en) * | 2021-07-30 | 2021-11-05 | 天津光电通信技术有限公司 | Low stray low phase noise sweep frequency source |
| CN115940941A (en) * | 2023-03-09 | 2023-04-07 | 中兵通信科技股份有限公司 | Frequency source for data link frequency hopping communication and rapid locking method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101136631A (en) * | 2006-08-31 | 2008-03-05 | 深圳市好易通科技有限公司 | Frequency synthesizer and frequency synthesis method |
| US20120112806A1 (en) * | 2010-11-09 | 2012-05-10 | Sony Corporation | Frequency synthesizer and frequency synthesizing method |
| CN203608181U (en) * | 2013-12-09 | 2014-05-21 | 成都赛英科技有限公司 | Frequency synthesizer |
| CN204068934U (en) * | 2014-08-22 | 2014-12-31 | 武汉中元通信股份有限公司 | Based on the single-chip integration frequency synthesizer of VHF frequency range |
-
2014
- 2014-08-22 CN CN201410416556.9A patent/CN104202047A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101136631A (en) * | 2006-08-31 | 2008-03-05 | 深圳市好易通科技有限公司 | Frequency synthesizer and frequency synthesis method |
| US20120112806A1 (en) * | 2010-11-09 | 2012-05-10 | Sony Corporation | Frequency synthesizer and frequency synthesizing method |
| CN203608181U (en) * | 2013-12-09 | 2014-05-21 | 成都赛英科技有限公司 | Frequency synthesizer |
| CN204068934U (en) * | 2014-08-22 | 2014-12-31 | 武汉中元通信股份有限公司 | Based on the single-chip integration frequency synthesizer of VHF frequency range |
Non-Patent Citations (2)
| Title |
|---|
| 李俊: "基于DDS+PLL的高性能VHF段频率合成器研究与实现", 《万方数据知识服务平台 湘潭大学硕士论文》 * |
| 潘玉剑 等: "基于HMC830的低相噪低杂散频率源的设计", 《电子设计工程》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113612475A (en) * | 2021-07-30 | 2021-11-05 | 天津光电通信技术有限公司 | Low stray low phase noise sweep frequency source |
| CN115940941A (en) * | 2023-03-09 | 2023-04-07 | 中兵通信科技股份有限公司 | Frequency source for data link frequency hopping communication and rapid locking method thereof |
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